intel/iwlwifi/iwl-eeprom-read.c

0001 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
0002 /*
0003  * Copyright (C) 2005-2014, 2018-2019, 2021 Intel Corporation
0004  */
0005 #include <linux/types.h>
0006 #include <linux/slab.h>
0007 #include <linux/export.h>
0008
0009 #include "iwl-drv.h"
0010 #include "iwl-debug.h"
0011 #include "iwl-eeprom-read.h"
0012 #include "iwl-io.h"
0013 #include "iwl-prph.h"
0014 #include "iwl-csr.h"
0015
0016 /*
0017  * EEPROM access time values:
0018  *
0019  * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
0020  * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
0021  * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
0022  * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
0023  */
0024 #define IWL_EEPROM_ACCESS_TIMEOUT   5000 /* uSec */
0025
0026 /*
0027  * The device's EEPROM semaphore prevents conflicts between driver and uCode
0028  * when accessing the EEPROM; each access is a series of pulses to/from the
0029  * EEPROM chip, not a single event, so even reads could conflict if they
0030  * weren't arbitrated by the semaphore.
0031  */
0032 #define IWL_EEPROM_SEM_TIMEOUT      10   /* microseconds */
0033 #define IWL_EEPROM_SEM_RETRY_LIMIT  1000 /* number of attempts (not time) */
0034
0035
0036 static int iwl_eeprom_acquire_semaphore(struct iwl_trans *trans)
0037 {
0038     u16 count;
0039     int ret;
0040
0041     for (count = 0; count < IWL_EEPROM_SEM_RETRY_LIMIT; count++) {
0042         /* Request semaphore */
0043         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
0044                 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
0045
0046         /* See if we got it */
0047         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
0048                 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
0049                 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
0050                 IWL_EEPROM_SEM_TIMEOUT);
0051         if (ret >= 0) {
0052             IWL_DEBUG_EEPROM(trans->dev,
0053                      "Acquired semaphore after %d tries.\n",
0054                      count+1);
0055             return ret;
0056         }
0057     }
0058
0059     return ret;
0060 }
0061
0062 static void iwl_eeprom_release_semaphore(struct iwl_trans *trans)
0063 {
0064     iwl_clear_bit(trans, CSR_HW_IF_CONFIG_REG,
0065               CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
0066 }
0067
0068 static int iwl_eeprom_verify_signature(struct iwl_trans *trans, bool nvm_is_otp)
0069 {
0070     u32 gp = iwl_read32(trans, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
0071
0072     IWL_DEBUG_EEPROM(trans->dev, "EEPROM signature=0x%08x\n", gp);
0073
0074     switch (gp) {
0075     case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP:
0076         if (!nvm_is_otp) {
0077             IWL_ERR(trans, "EEPROM with bad signature: 0x%08x\n",
0078                 gp);
0079             return -ENOENT;
0080         }
0081         return 0;
0082     case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
0083     case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
0084         if (nvm_is_otp) {
0085             IWL_ERR(trans, "OTP with bad signature: 0x%08x\n", gp);
0086             return -ENOENT;
0087         }
0088         return 0;
0089     case CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP:
0090     default:
0091         IWL_ERR(trans,
0092             "bad EEPROM/OTP signature, type=%s, EEPROM_GP=0x%08x\n",
0093             nvm_is_otp ? "OTP" : "EEPROM", gp);
0094         return -ENOENT;
0095     }
0096 }
0097
0098 /******************************************************************************
0099  *
0100  * OTP related functions
0101  *
0102 ******************************************************************************/
0103
0104 static void iwl_set_otp_access_absolute(struct iwl_trans *trans)
0105 {
0106     iwl_read32(trans, CSR_OTP_GP_REG);
0107
0108     iwl_clear_bit(trans, CSR_OTP_GP_REG,
0109               CSR_OTP_GP_REG_OTP_ACCESS_MODE);
0110 }
0111
0112 static int iwl_nvm_is_otp(struct iwl_trans *trans)
0113 {
0114     u32 otpgp;
0115
0116     /* OTP only valid for CP/PP and after */
0117     switch (trans->hw_rev & CSR_HW_REV_TYPE_MSK) {
0118     case CSR_HW_REV_TYPE_NONE:
0119         IWL_ERR(trans, "Unknown hardware type\n");
0120         return -EIO;
0121     case CSR_HW_REV_TYPE_5300:
0122     case CSR_HW_REV_TYPE_5350:
0123     case CSR_HW_REV_TYPE_5100:
0124     case CSR_HW_REV_TYPE_5150:
0125         return 0;
0126     default:
0127         otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
0128         if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT)
0129             return 1;
0130         return 0;
0131     }
0132 }
0133
0134 static int iwl_init_otp_access(struct iwl_trans *trans)
0135 {
0136     int ret;
0137
0138     ret = iwl_finish_nic_init(trans);
0139     if (ret)
0140         return ret;
0141
0142     iwl_set_bits_prph(trans, APMG_PS_CTRL_REG,
0143               APMG_PS_CTRL_VAL_RESET_REQ);
0144     udelay(5);
0145     iwl_clear_bits_prph(trans, APMG_PS_CTRL_REG,
0146                 APMG_PS_CTRL_VAL_RESET_REQ);
0147
0148     /*
0149      * CSR auto clock gate disable bit -
0150      * this is only applicable for HW with OTP shadow RAM
0151      */
0152     if (trans->trans_cfg->base_params->shadow_ram_support)
0153         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
0154                 CSR_RESET_LINK_PWR_MGMT_DISABLED);
0155
0156     return 0;
0157 }
0158
0159 static int iwl_read_otp_word(struct iwl_trans *trans, u16 addr,
0160                  __le16 *eeprom_data)
0161 {
0162     int ret = 0;
0163     u32 r;
0164     u32 otpgp;
0165
0166     iwl_write32(trans, CSR_EEPROM_REG,
0167             CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
0168     ret = iwl_poll_bit(trans, CSR_EEPROM_REG,
0169                  CSR_EEPROM_REG_READ_VALID_MSK,
0170                  CSR_EEPROM_REG_READ_VALID_MSK,
0171                  IWL_EEPROM_ACCESS_TIMEOUT);
0172     if (ret < 0) {
0173         IWL_ERR(trans, "Time out reading OTP[%d]\n", addr);
0174         return ret;
0175     }
0176     r = iwl_read32(trans, CSR_EEPROM_REG);
0177     /* check for ECC errors: */
0178     otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
0179     if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
0180         /* stop in this case */
0181         /* set the uncorrectable OTP ECC bit for acknowledgment */
0182         iwl_set_bit(trans, CSR_OTP_GP_REG,
0183                 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
0184         IWL_ERR(trans, "Uncorrectable OTP ECC error, abort OTP read\n");
0185         return -EINVAL;
0186     }
0187     if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
0188         /* continue in this case */
0189         /* set the correctable OTP ECC bit for acknowledgment */
0190         iwl_set_bit(trans, CSR_OTP_GP_REG,
0191                 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
0192         IWL_ERR(trans, "Correctable OTP ECC error, continue read\n");
0193     }
0194     *eeprom_data = cpu_to_le16(r >> 16);
0195     return 0;
0196 }
0197
0198 /*
0199  * iwl_is_otp_empty: check for empty OTP
0200  */
0201 static bool iwl_is_otp_empty(struct iwl_trans *trans)
0202 {
0203     u16 next_link_addr = 0;
0204     __le16 link_value;
0205     bool is_empty = false;
0206
0207     /* locate the beginning of OTP link list */
0208     if (!iwl_read_otp_word(trans, next_link_addr, &link_value)) {
0209         if (!link_value) {
0210             IWL_ERR(trans, "OTP is empty\n");
0211             is_empty = true;
0212         }
0213     } else {
0214         IWL_ERR(trans, "Unable to read first block of OTP list.\n");
0215         is_empty = true;
0216     }
0217
0218     return is_empty;
0219 }
0220
0221
0222 /*
0223  * iwl_find_otp_image: find EEPROM image in OTP
0224  *   finding the OTP block that contains the EEPROM image.
0225  *   the last valid block on the link list (the block _before_ the last block)
0226  *   is the block we should read and used to configure the device.
0227  *   If all the available OTP blocks are full, the last block will be the block
0228  *   we should read and used to configure the device.
0229  *   only perform this operation if shadow RAM is disabled
0230  */
0231 static int iwl_find_otp_image(struct iwl_trans *trans,
0232                     u16 *validblockaddr)
0233 {
0234     u16 next_link_addr = 0, valid_addr;
0235     __le16 link_value = 0;
0236     int usedblocks = 0;
0237
0238     /* set addressing mode to absolute to traverse the link list */
0239     iwl_set_otp_access_absolute(trans);
0240
0241     /* checking for empty OTP or error */
0242     if (iwl_is_otp_empty(trans))
0243         return -EINVAL;
0244
0245     /*
0246      * start traverse link list
0247      * until reach the max number of OTP blocks
0248      * different devices have different number of OTP blocks
0249      */
0250     do {
0251         /* save current valid block address
0252          * check for more block on the link list
0253          */
0254         valid_addr = next_link_addr;
0255         next_link_addr = le16_to_cpu(link_value) * sizeof(u16);
0256         IWL_DEBUG_EEPROM(trans->dev, "OTP blocks %d addr 0x%x\n",
0257                  usedblocks, next_link_addr);
0258         if (iwl_read_otp_word(trans, next_link_addr, &link_value))
0259             return -EINVAL;
0260         if (!link_value) {
0261             /*
0262              * reach the end of link list, return success and
0263              * set address point to the starting address
0264              * of the image
0265              */
0266             *validblockaddr = valid_addr;
0267             /* skip first 2 bytes (link list pointer) */
0268             *validblockaddr += 2;
0269             return 0;
0270         }
0271         /* more in the link list, continue */
0272         usedblocks++;
0273     } while (usedblocks <= trans->trans_cfg->base_params->max_ll_items);
0274
0275     /* OTP has no valid blocks */
0276     IWL_DEBUG_EEPROM(trans->dev, "OTP has no valid blocks\n");
0277     return -EINVAL;
0278 }
0279
0280 /*
0281  * iwl_read_eeprom - read EEPROM contents
0282  *
0283  * Load the EEPROM contents from adapter and return it
0284  * and its size.
0285  *
0286  * NOTE:  This routine uses the non-debug IO access functions.
0287  */
0288 int iwl_read_eeprom(struct iwl_trans *trans, u8 **eeprom, size_t *eeprom_size)
0289 {
0290     __le16 *e;
0291     u32 gp = iwl_read32(trans, CSR_EEPROM_GP);
0292     int sz;
0293     int ret;
0294     u16 addr;
0295     u16 validblockaddr = 0;
0296     u16 cache_addr = 0;
0297     int nvm_is_otp;
0298
0299     if (!eeprom || !eeprom_size)
0300         return -EINVAL;
0301
0302     nvm_is_otp = iwl_nvm_is_otp(trans);
0303     if (nvm_is_otp < 0)
0304         return nvm_is_otp;
0305
0306     sz = trans->trans_cfg->base_params->eeprom_size;
0307     IWL_DEBUG_EEPROM(trans->dev, "NVM size = %d\n", sz);
0308
0309     e = kmalloc(sz, GFP_KERNEL);
0310     if (!e)
0311         return -ENOMEM;
0312
0313     ret = iwl_eeprom_verify_signature(trans, nvm_is_otp);
0314     if (ret < 0) {
0315         IWL_ERR(trans, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
0316         goto err_free;
0317     }
0318
0319     /* Make sure driver (instead of uCode) is allowed to read EEPROM */
0320     ret = iwl_eeprom_acquire_semaphore(trans);
0321     if (ret < 0) {
0322         IWL_ERR(trans, "Failed to acquire EEPROM semaphore.\n");
0323         goto err_free;
0324     }
0325
0326     if (nvm_is_otp) {
0327         ret = iwl_init_otp_access(trans);
0328         if (ret) {
0329             IWL_ERR(trans, "Failed to initialize OTP access.\n");
0330             goto err_unlock;
0331         }
0332
0333         iwl_write32(trans, CSR_EEPROM_GP,
0334                 iwl_read32(trans, CSR_EEPROM_GP) &
0335                 ~CSR_EEPROM_GP_IF_OWNER_MSK);
0336
0337         iwl_set_bit(trans, CSR_OTP_GP_REG,
0338                 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
0339                 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
0340         /* traversing the linked list if no shadow ram supported */
0341         if (!trans->trans_cfg->base_params->shadow_ram_support) {
0342             ret = iwl_find_otp_image(trans, &validblockaddr);
0343             if (ret)
0344                 goto err_unlock;
0345         }
0346         for (addr = validblockaddr; addr < validblockaddr + sz;
0347              addr += sizeof(u16)) {
0348             __le16 eeprom_data;
0349
0350             ret = iwl_read_otp_word(trans, addr, &eeprom_data);
0351             if (ret)
0352                 goto err_unlock;
0353             e[cache_addr / 2] = eeprom_data;
0354             cache_addr += sizeof(u16);
0355         }
0356     } else {
0357         /* eeprom is an array of 16bit values */
0358         for (addr = 0; addr < sz; addr += sizeof(u16)) {
0359             u32 r;
0360
0361             iwl_write32(trans, CSR_EEPROM_REG,
0362                     CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
0363
0364             ret = iwl_poll_bit(trans, CSR_EEPROM_REG,
0365                        CSR_EEPROM_REG_READ_VALID_MSK,
0366                        CSR_EEPROM_REG_READ_VALID_MSK,
0367                        IWL_EEPROM_ACCESS_TIMEOUT);
0368             if (ret < 0) {
0369                 IWL_ERR(trans,
0370                     "Time out reading EEPROM[%d]\n", addr);
0371                 goto err_unlock;
0372             }
0373             r = iwl_read32(trans, CSR_EEPROM_REG);
0374             e[addr / 2] = cpu_to_le16(r >> 16);
0375         }
0376     }
0377
0378     IWL_DEBUG_EEPROM(trans->dev, "NVM Type: %s\n",
0379              nvm_is_otp ? "OTP" : "EEPROM");
0380
0381     iwl_eeprom_release_semaphore(trans);
0382
0383     *eeprom_size = sz;
0384     *eeprom = (u8 *)e;
0385     return 0;
0386
0387  err_unlock:
0388     iwl_eeprom_release_semaphore(trans);
0389  err_free:
0390     kfree(e);
0391
0392     return ret;
0393 }
0394 IWL_EXPORT_SYMBOL(iwl_read_eeprom);