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0001 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
0002 /*
0003  * Copyright (C) 2018-2022 Intel Corporation
0004  */
0005 #include <linux/firmware.h>
0006 #include "iwl-drv.h"
0007 #include "iwl-trans.h"
0008 #include "iwl-dbg-tlv.h"
0009 #include "fw/dbg.h"
0010 #include "fw/runtime.h"
0011 
0012 /**
0013  * enum iwl_dbg_tlv_type - debug TLV types
0014  * @IWL_DBG_TLV_TYPE_DEBUG_INFO: debug info TLV
0015  * @IWL_DBG_TLV_TYPE_BUF_ALLOC: buffer allocation TLV
0016  * @IWL_DBG_TLV_TYPE_HCMD: host command TLV
0017  * @IWL_DBG_TLV_TYPE_REGION: region TLV
0018  * @IWL_DBG_TLV_TYPE_TRIGGER: trigger TLV
0019  * @IWL_DBG_TLV_TYPE_CONF_SET: conf set TLV
0020  * @IWL_DBG_TLV_TYPE_NUM: number of debug TLVs
0021  */
0022 enum iwl_dbg_tlv_type {
0023     IWL_DBG_TLV_TYPE_DEBUG_INFO =
0024         IWL_UCODE_TLV_TYPE_DEBUG_INFO - IWL_UCODE_TLV_DEBUG_BASE,
0025     IWL_DBG_TLV_TYPE_BUF_ALLOC,
0026     IWL_DBG_TLV_TYPE_HCMD,
0027     IWL_DBG_TLV_TYPE_REGION,
0028     IWL_DBG_TLV_TYPE_TRIGGER,
0029     IWL_DBG_TLV_TYPE_CONF_SET,
0030     IWL_DBG_TLV_TYPE_NUM,
0031 };
0032 
0033 /**
0034  * struct iwl_dbg_tlv_ver_data -  debug TLV version struct
0035  * @min_ver: min version supported
0036  * @max_ver: max version supported
0037  */
0038 struct iwl_dbg_tlv_ver_data {
0039     int min_ver;
0040     int max_ver;
0041 };
0042 
0043 /**
0044  * struct iwl_dbg_tlv_timer_node - timer node struct
0045  * @list: list of &struct iwl_dbg_tlv_timer_node
0046  * @timer: timer
0047  * @fwrt: &struct iwl_fw_runtime
0048  * @tlv: TLV attach to the timer node
0049  */
0050 struct iwl_dbg_tlv_timer_node {
0051     struct list_head list;
0052     struct timer_list timer;
0053     struct iwl_fw_runtime *fwrt;
0054     struct iwl_ucode_tlv *tlv;
0055 };
0056 
0057 static const struct iwl_dbg_tlv_ver_data
0058 dbg_ver_table[IWL_DBG_TLV_TYPE_NUM] = {
0059     [IWL_DBG_TLV_TYPE_DEBUG_INFO]   = {.min_ver = 1, .max_ver = 1,},
0060     [IWL_DBG_TLV_TYPE_BUF_ALLOC]    = {.min_ver = 1, .max_ver = 1,},
0061     [IWL_DBG_TLV_TYPE_HCMD]     = {.min_ver = 1, .max_ver = 1,},
0062     [IWL_DBG_TLV_TYPE_REGION]   = {.min_ver = 1, .max_ver = 3,},
0063     [IWL_DBG_TLV_TYPE_TRIGGER]  = {.min_ver = 1, .max_ver = 1,},
0064     [IWL_DBG_TLV_TYPE_CONF_SET] = {.min_ver = 1, .max_ver = 1,},
0065 };
0066 
0067 static int iwl_dbg_tlv_add(const struct iwl_ucode_tlv *tlv,
0068                struct list_head *list)
0069 {
0070     u32 len = le32_to_cpu(tlv->length);
0071     struct iwl_dbg_tlv_node *node;
0072 
0073     node = kzalloc(sizeof(*node) + len, GFP_KERNEL);
0074     if (!node)
0075         return -ENOMEM;
0076 
0077     memcpy(&node->tlv, tlv, sizeof(node->tlv));
0078     memcpy(node->tlv.data, tlv->data, len);
0079     list_add_tail(&node->list, list);
0080 
0081     return 0;
0082 }
0083 
0084 static bool iwl_dbg_tlv_ver_support(const struct iwl_ucode_tlv *tlv)
0085 {
0086     const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0];
0087     u32 type = le32_to_cpu(tlv->type);
0088     u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE;
0089     u32 ver = le32_to_cpu(hdr->version);
0090 
0091     if (ver < dbg_ver_table[tlv_idx].min_ver ||
0092         ver > dbg_ver_table[tlv_idx].max_ver)
0093         return false;
0094 
0095     return true;
0096 }
0097 
0098 static int iwl_dbg_tlv_alloc_debug_info(struct iwl_trans *trans,
0099                     const struct iwl_ucode_tlv *tlv)
0100 {
0101     const struct iwl_fw_ini_debug_info_tlv *debug_info = (const void *)tlv->data;
0102 
0103     if (le32_to_cpu(tlv->length) != sizeof(*debug_info))
0104         return -EINVAL;
0105 
0106     IWL_DEBUG_FW(trans, "WRT: Loading debug cfg: %s\n",
0107              debug_info->debug_cfg_name);
0108 
0109     return iwl_dbg_tlv_add(tlv, &trans->dbg.debug_info_tlv_list);
0110 }
0111 
0112 static int iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans *trans,
0113                        const struct iwl_ucode_tlv *tlv)
0114 {
0115     const struct iwl_fw_ini_allocation_tlv *alloc = (const void *)tlv->data;
0116     u32 buf_location;
0117     u32 alloc_id;
0118 
0119     if (le32_to_cpu(tlv->length) != sizeof(*alloc))
0120         return -EINVAL;
0121 
0122     buf_location = le32_to_cpu(alloc->buf_location);
0123     alloc_id = le32_to_cpu(alloc->alloc_id);
0124 
0125     if (buf_location == IWL_FW_INI_LOCATION_INVALID ||
0126         buf_location >= IWL_FW_INI_LOCATION_NUM)
0127         goto err;
0128 
0129     if (alloc_id == IWL_FW_INI_ALLOCATION_INVALID ||
0130         alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
0131         goto err;
0132 
0133     if (buf_location == IWL_FW_INI_LOCATION_NPK_PATH &&
0134         alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1)
0135         goto err;
0136 
0137     if (buf_location == IWL_FW_INI_LOCATION_SRAM_PATH &&
0138         alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1)
0139         goto err;
0140 
0141     trans->dbg.fw_mon_cfg[alloc_id] = *alloc;
0142 
0143     return 0;
0144 err:
0145     IWL_ERR(trans,
0146         "WRT: Invalid allocation id %u and/or location id %u for allocation TLV\n",
0147         alloc_id, buf_location);
0148     return -EINVAL;
0149 }
0150 
0151 static int iwl_dbg_tlv_alloc_hcmd(struct iwl_trans *trans,
0152                   const struct iwl_ucode_tlv *tlv)
0153 {
0154     const struct iwl_fw_ini_hcmd_tlv *hcmd = (const void *)tlv->data;
0155     u32 tp = le32_to_cpu(hcmd->time_point);
0156 
0157     if (le32_to_cpu(tlv->length) <= sizeof(*hcmd))
0158         return -EINVAL;
0159 
0160     /* Host commands can not be sent in early time point since the FW
0161      * is not ready
0162      */
0163     if (tp == IWL_FW_INI_TIME_POINT_INVALID ||
0164         tp >= IWL_FW_INI_TIME_POINT_NUM ||
0165         tp == IWL_FW_INI_TIME_POINT_EARLY) {
0166         IWL_ERR(trans,
0167             "WRT: Invalid time point %u for host command TLV\n",
0168             tp);
0169         return -EINVAL;
0170     }
0171 
0172     return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].hcmd_list);
0173 }
0174 
0175 static int iwl_dbg_tlv_alloc_region(struct iwl_trans *trans,
0176                     const struct iwl_ucode_tlv *tlv)
0177 {
0178     const struct iwl_fw_ini_region_tlv *reg = (const void *)tlv->data;
0179     struct iwl_ucode_tlv **active_reg;
0180     u32 id = le32_to_cpu(reg->id);
0181     u8 type = reg->type;
0182     u32 tlv_len = sizeof(*tlv) + le32_to_cpu(tlv->length);
0183 
0184     /*
0185      * The higher part of the ID from version 2 is debug policy.
0186      * The id will be only lsb 16 bits, so mask it out.
0187      */
0188     if (le32_to_cpu(reg->hdr.version) >= 2)
0189         id &= IWL_FW_INI_REGION_ID_MASK;
0190 
0191     if (le32_to_cpu(tlv->length) < sizeof(*reg))
0192         return -EINVAL;
0193 
0194     /* for safe use of a string from FW, limit it to IWL_FW_INI_MAX_NAME */
0195     IWL_DEBUG_FW(trans, "WRT: parsing region: %.*s\n",
0196              IWL_FW_INI_MAX_NAME, reg->name);
0197 
0198     if (id >= IWL_FW_INI_MAX_REGION_ID) {
0199         IWL_ERR(trans, "WRT: Invalid region id %u\n", id);
0200         return -EINVAL;
0201     }
0202 
0203     if (type <= IWL_FW_INI_REGION_INVALID ||
0204         type >= IWL_FW_INI_REGION_NUM) {
0205         IWL_ERR(trans, "WRT: Invalid region type %u\n", type);
0206         return -EINVAL;
0207     }
0208 
0209     if (type == IWL_FW_INI_REGION_PCI_IOSF_CONFIG &&
0210         !trans->ops->read_config32) {
0211         IWL_ERR(trans, "WRT: Unsupported region type %u\n", type);
0212         return -EOPNOTSUPP;
0213     }
0214 
0215     if (type == IWL_FW_INI_REGION_INTERNAL_BUFFER) {
0216         trans->dbg.imr_data.sram_addr =
0217             le32_to_cpu(reg->internal_buffer.base_addr);
0218         trans->dbg.imr_data.sram_size =
0219             le32_to_cpu(reg->internal_buffer.size);
0220     }
0221 
0222 
0223     active_reg = &trans->dbg.active_regions[id];
0224     if (*active_reg) {
0225         IWL_WARN(trans, "WRT: Overriding region id %u\n", id);
0226 
0227         kfree(*active_reg);
0228     }
0229 
0230     *active_reg = kmemdup(tlv, tlv_len, GFP_KERNEL);
0231     if (!*active_reg)
0232         return -ENOMEM;
0233 
0234     IWL_DEBUG_FW(trans, "WRT: Enabling region id %u type %u\n", id, type);
0235 
0236     return 0;
0237 }
0238 
0239 static int iwl_dbg_tlv_alloc_trigger(struct iwl_trans *trans,
0240                      const struct iwl_ucode_tlv *tlv)
0241 {
0242     const struct iwl_fw_ini_trigger_tlv *trig = (const void *)tlv->data;
0243     struct iwl_fw_ini_trigger_tlv *dup_trig;
0244     u32 tp = le32_to_cpu(trig->time_point);
0245     u32 rf = le32_to_cpu(trig->reset_fw);
0246     struct iwl_ucode_tlv *dup = NULL;
0247     int ret;
0248 
0249     if (le32_to_cpu(tlv->length) < sizeof(*trig))
0250         return -EINVAL;
0251 
0252     if (tp <= IWL_FW_INI_TIME_POINT_INVALID ||
0253         tp >= IWL_FW_INI_TIME_POINT_NUM) {
0254         IWL_ERR(trans,
0255             "WRT: Invalid time point %u for trigger TLV\n",
0256             tp);
0257         return -EINVAL;
0258     }
0259 
0260     IWL_DEBUG_FW(trans,
0261              "WRT: time point %u for trigger TLV with reset_fw %u\n",
0262              tp, rf);
0263     trans->dbg.last_tp_resetfw = 0xFF;
0264     if (!le32_to_cpu(trig->occurrences)) {
0265         dup = kmemdup(tlv, sizeof(*tlv) + le32_to_cpu(tlv->length),
0266                 GFP_KERNEL);
0267         if (!dup)
0268             return -ENOMEM;
0269         dup_trig = (void *)dup->data;
0270         dup_trig->occurrences = cpu_to_le32(-1);
0271         tlv = dup;
0272     }
0273 
0274     ret = iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].trig_list);
0275     kfree(dup);
0276 
0277     return ret;
0278 }
0279 
0280 static int iwl_dbg_tlv_config_set(struct iwl_trans *trans,
0281                   const struct iwl_ucode_tlv *tlv)
0282 {
0283     const struct iwl_fw_ini_conf_set_tlv *conf_set = (const void *)tlv->data;
0284     u32 tp = le32_to_cpu(conf_set->time_point);
0285     u32 type = le32_to_cpu(conf_set->set_type);
0286 
0287     if (tp <= IWL_FW_INI_TIME_POINT_INVALID ||
0288         tp >= IWL_FW_INI_TIME_POINT_NUM) {
0289         IWL_DEBUG_FW(trans,
0290                  "WRT: Invalid time point %u for config set TLV\n", tp);
0291         return -EINVAL;
0292     }
0293 
0294     if (type <= IWL_FW_INI_CONFIG_SET_TYPE_INVALID ||
0295         type >= IWL_FW_INI_CONFIG_SET_TYPE_MAX_NUM) {
0296         IWL_DEBUG_FW(trans,
0297                  "WRT: Invalid config set type %u for config set TLV\n", type);
0298         return -EINVAL;
0299     }
0300 
0301     return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].config_list);
0302 }
0303 
0304 static int (*dbg_tlv_alloc[])(struct iwl_trans *trans,
0305                   const struct iwl_ucode_tlv *tlv) = {
0306     [IWL_DBG_TLV_TYPE_DEBUG_INFO]   = iwl_dbg_tlv_alloc_debug_info,
0307     [IWL_DBG_TLV_TYPE_BUF_ALLOC]    = iwl_dbg_tlv_alloc_buf_alloc,
0308     [IWL_DBG_TLV_TYPE_HCMD]     = iwl_dbg_tlv_alloc_hcmd,
0309     [IWL_DBG_TLV_TYPE_REGION]   = iwl_dbg_tlv_alloc_region,
0310     [IWL_DBG_TLV_TYPE_TRIGGER]  = iwl_dbg_tlv_alloc_trigger,
0311     [IWL_DBG_TLV_TYPE_CONF_SET] = iwl_dbg_tlv_config_set,
0312 };
0313 
0314 void iwl_dbg_tlv_alloc(struct iwl_trans *trans, const struct iwl_ucode_tlv *tlv,
0315                bool ext)
0316 {
0317     enum iwl_ini_cfg_state *cfg_state = ext ?
0318         &trans->dbg.external_ini_cfg : &trans->dbg.internal_ini_cfg;
0319     const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0];
0320     u32 type;
0321     u32 tlv_idx;
0322     u32 domain;
0323     int ret;
0324 
0325     if (le32_to_cpu(tlv->length) < sizeof(*hdr))
0326         return;
0327 
0328     type = le32_to_cpu(tlv->type);
0329     tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE;
0330     domain = le32_to_cpu(hdr->domain);
0331 
0332     if (domain != IWL_FW_INI_DOMAIN_ALWAYS_ON &&
0333         !(domain & trans->dbg.domains_bitmap)) {
0334         IWL_DEBUG_FW(trans,
0335                  "WRT: Skipping TLV with disabled domain 0x%0x (0x%0x)\n",
0336                  domain, trans->dbg.domains_bitmap);
0337         return;
0338     }
0339 
0340     if (tlv_idx >= ARRAY_SIZE(dbg_tlv_alloc) || !dbg_tlv_alloc[tlv_idx]) {
0341         IWL_ERR(trans, "WRT: Unsupported TLV type 0x%x\n", type);
0342         goto out_err;
0343     }
0344 
0345     if (!iwl_dbg_tlv_ver_support(tlv)) {
0346         IWL_ERR(trans, "WRT: Unsupported TLV 0x%x version %u\n", type,
0347             le32_to_cpu(hdr->version));
0348         goto out_err;
0349     }
0350 
0351     ret = dbg_tlv_alloc[tlv_idx](trans, tlv);
0352     if (ret) {
0353         IWL_ERR(trans,
0354             "WRT: Failed to allocate TLV 0x%x, ret %d, (ext=%d)\n",
0355             type, ret, ext);
0356         goto out_err;
0357     }
0358 
0359     if (*cfg_state == IWL_INI_CFG_STATE_NOT_LOADED)
0360         *cfg_state = IWL_INI_CFG_STATE_LOADED;
0361 
0362     return;
0363 
0364 out_err:
0365     *cfg_state = IWL_INI_CFG_STATE_CORRUPTED;
0366 }
0367 
0368 void iwl_dbg_tlv_del_timers(struct iwl_trans *trans)
0369 {
0370     struct list_head *timer_list = &trans->dbg.periodic_trig_list;
0371     struct iwl_dbg_tlv_timer_node *node, *tmp;
0372 
0373     list_for_each_entry_safe(node, tmp, timer_list, list) {
0374         del_timer_sync(&node->timer);
0375         list_del(&node->list);
0376         kfree(node);
0377     }
0378 }
0379 IWL_EXPORT_SYMBOL(iwl_dbg_tlv_del_timers);
0380 
0381 static void iwl_dbg_tlv_fragments_free(struct iwl_trans *trans,
0382                        enum iwl_fw_ini_allocation_id alloc_id)
0383 {
0384     struct iwl_fw_mon *fw_mon;
0385     int i;
0386 
0387     if (alloc_id <= IWL_FW_INI_ALLOCATION_INVALID ||
0388         alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
0389         return;
0390 
0391     fw_mon = &trans->dbg.fw_mon_ini[alloc_id];
0392 
0393     for (i = 0; i < fw_mon->num_frags; i++) {
0394         struct iwl_dram_data *frag = &fw_mon->frags[i];
0395 
0396         dma_free_coherent(trans->dev, frag->size, frag->block,
0397                   frag->physical);
0398 
0399         frag->physical = 0;
0400         frag->block = NULL;
0401         frag->size = 0;
0402     }
0403 
0404     kfree(fw_mon->frags);
0405     fw_mon->frags = NULL;
0406     fw_mon->num_frags = 0;
0407 }
0408 
0409 void iwl_dbg_tlv_free(struct iwl_trans *trans)
0410 {
0411     struct iwl_dbg_tlv_node *tlv_node, *tlv_node_tmp;
0412     int i;
0413 
0414     iwl_dbg_tlv_del_timers(trans);
0415 
0416     for (i = 0; i < ARRAY_SIZE(trans->dbg.active_regions); i++) {
0417         struct iwl_ucode_tlv **active_reg =
0418             &trans->dbg.active_regions[i];
0419 
0420         kfree(*active_reg);
0421         *active_reg = NULL;
0422     }
0423 
0424     list_for_each_entry_safe(tlv_node, tlv_node_tmp,
0425                  &trans->dbg.debug_info_tlv_list, list) {
0426         list_del(&tlv_node->list);
0427         kfree(tlv_node);
0428     }
0429 
0430     for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) {
0431         struct iwl_dbg_tlv_time_point_data *tp =
0432             &trans->dbg.time_point[i];
0433 
0434         list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->trig_list,
0435                      list) {
0436             list_del(&tlv_node->list);
0437             kfree(tlv_node);
0438         }
0439 
0440         list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->hcmd_list,
0441                      list) {
0442             list_del(&tlv_node->list);
0443             kfree(tlv_node);
0444         }
0445 
0446         list_for_each_entry_safe(tlv_node, tlv_node_tmp,
0447                      &tp->active_trig_list, list) {
0448             list_del(&tlv_node->list);
0449             kfree(tlv_node);
0450         }
0451 
0452         list_for_each_entry_safe(tlv_node, tlv_node_tmp,
0453                      &tp->config_list, list) {
0454             list_del(&tlv_node->list);
0455             kfree(tlv_node);
0456         }
0457 
0458     }
0459 
0460     for (i = 0; i < ARRAY_SIZE(trans->dbg.fw_mon_ini); i++)
0461         iwl_dbg_tlv_fragments_free(trans, i);
0462 }
0463 
0464 static int iwl_dbg_tlv_parse_bin(struct iwl_trans *trans, const u8 *data,
0465                  size_t len)
0466 {
0467     const struct iwl_ucode_tlv *tlv;
0468     u32 tlv_len;
0469 
0470     while (len >= sizeof(*tlv)) {
0471         len -= sizeof(*tlv);
0472         tlv = (const void *)data;
0473 
0474         tlv_len = le32_to_cpu(tlv->length);
0475 
0476         if (len < tlv_len) {
0477             IWL_ERR(trans, "invalid TLV len: %zd/%u\n",
0478                 len, tlv_len);
0479             return -EINVAL;
0480         }
0481         len -= ALIGN(tlv_len, 4);
0482         data += sizeof(*tlv) + ALIGN(tlv_len, 4);
0483 
0484         iwl_dbg_tlv_alloc(trans, tlv, true);
0485     }
0486 
0487     return 0;
0488 }
0489 
0490 void iwl_dbg_tlv_load_bin(struct device *dev, struct iwl_trans *trans)
0491 {
0492     const struct firmware *fw;
0493     const char *yoyo_bin = "iwl-debug-yoyo.bin";
0494     int res;
0495 
0496     if (!iwlwifi_mod_params.enable_ini ||
0497         trans->trans_cfg->device_family <= IWL_DEVICE_FAMILY_8000)
0498         return;
0499 
0500     res = firmware_request_nowarn(&fw, yoyo_bin, dev);
0501     IWL_DEBUG_FW(trans, "%s %s\n", res ? "didn't load" : "loaded", yoyo_bin);
0502 
0503     if (res)
0504         return;
0505 
0506     iwl_dbg_tlv_parse_bin(trans, fw->data, fw->size);
0507 
0508     release_firmware(fw);
0509 }
0510 
0511 void iwl_dbg_tlv_init(struct iwl_trans *trans)
0512 {
0513     int i;
0514 
0515     INIT_LIST_HEAD(&trans->dbg.debug_info_tlv_list);
0516     INIT_LIST_HEAD(&trans->dbg.periodic_trig_list);
0517 
0518     for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) {
0519         struct iwl_dbg_tlv_time_point_data *tp =
0520             &trans->dbg.time_point[i];
0521 
0522         INIT_LIST_HEAD(&tp->trig_list);
0523         INIT_LIST_HEAD(&tp->hcmd_list);
0524         INIT_LIST_HEAD(&tp->active_trig_list);
0525         INIT_LIST_HEAD(&tp->config_list);
0526     }
0527 }
0528 
0529 static int iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime *fwrt,
0530                       struct iwl_dram_data *frag, u32 pages)
0531 {
0532     void *block = NULL;
0533     dma_addr_t physical;
0534 
0535     if (!frag || frag->size || !pages)
0536         return -EIO;
0537 
0538     /*
0539      * We try to allocate as many pages as we can, starting with
0540      * the requested amount and going down until we can allocate
0541      * something.  Because of DIV_ROUND_UP(), pages will never go
0542      * down to 0 and stop the loop, so stop when pages reaches 1,
0543      * which is too small anyway.
0544      */
0545     while (pages > 1) {
0546         block = dma_alloc_coherent(fwrt->dev, pages * PAGE_SIZE,
0547                        &physical,
0548                        GFP_KERNEL | __GFP_NOWARN);
0549         if (block)
0550             break;
0551 
0552         IWL_WARN(fwrt, "WRT: Failed to allocate fragment size %lu\n",
0553              pages * PAGE_SIZE);
0554 
0555         pages = DIV_ROUND_UP(pages, 2);
0556     }
0557 
0558     if (!block)
0559         return -ENOMEM;
0560 
0561     frag->physical = physical;
0562     frag->block = block;
0563     frag->size = pages * PAGE_SIZE;
0564 
0565     return pages;
0566 }
0567 
0568 static int iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime *fwrt,
0569                        enum iwl_fw_ini_allocation_id alloc_id)
0570 {
0571     struct iwl_fw_mon *fw_mon;
0572     struct iwl_fw_ini_allocation_tlv *fw_mon_cfg;
0573     u32 num_frags, remain_pages, frag_pages;
0574     int i;
0575 
0576     if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID ||
0577         alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
0578         return -EIO;
0579 
0580     fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id];
0581     fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
0582 
0583     if (fw_mon->num_frags ||
0584         fw_mon_cfg->buf_location !=
0585         cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH))
0586         return 0;
0587 
0588     num_frags = le32_to_cpu(fw_mon_cfg->max_frags_num);
0589     if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) {
0590         if (alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1)
0591             return -EIO;
0592         num_frags = 1;
0593     }
0594 
0595     remain_pages = DIV_ROUND_UP(le32_to_cpu(fw_mon_cfg->req_size),
0596                     PAGE_SIZE);
0597     num_frags = min_t(u32, num_frags, BUF_ALLOC_MAX_NUM_FRAGS);
0598     num_frags = min_t(u32, num_frags, remain_pages);
0599     frag_pages = DIV_ROUND_UP(remain_pages, num_frags);
0600 
0601     fw_mon->frags = kcalloc(num_frags, sizeof(*fw_mon->frags), GFP_KERNEL);
0602     if (!fw_mon->frags)
0603         return -ENOMEM;
0604 
0605     for (i = 0; i < num_frags; i++) {
0606         int pages = min_t(u32, frag_pages, remain_pages);
0607 
0608         IWL_DEBUG_FW(fwrt,
0609                  "WRT: Allocating DRAM buffer (alloc_id=%u, fragment=%u, size=0x%lx)\n",
0610                  alloc_id, i, pages * PAGE_SIZE);
0611 
0612         pages = iwl_dbg_tlv_alloc_fragment(fwrt, &fw_mon->frags[i],
0613                            pages);
0614         if (pages < 0) {
0615             u32 alloc_size = le32_to_cpu(fw_mon_cfg->req_size) -
0616                 (remain_pages * PAGE_SIZE);
0617 
0618             if (alloc_size < le32_to_cpu(fw_mon_cfg->min_size)) {
0619                 iwl_dbg_tlv_fragments_free(fwrt->trans,
0620                                alloc_id);
0621                 return pages;
0622             }
0623             break;
0624         }
0625 
0626         remain_pages -= pages;
0627         fw_mon->num_frags++;
0628     }
0629 
0630     return 0;
0631 }
0632 
0633 static int iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime *fwrt,
0634                     enum iwl_fw_ini_allocation_id alloc_id)
0635 {
0636     struct iwl_fw_mon *fw_mon;
0637     u32 remain_frags, num_commands;
0638     int i, fw_mon_idx = 0;
0639 
0640     if (!fw_has_capa(&fwrt->fw->ucode_capa,
0641              IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP))
0642         return 0;
0643 
0644     if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID ||
0645         alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
0646         return -EIO;
0647 
0648     if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) !=
0649         IWL_FW_INI_LOCATION_DRAM_PATH)
0650         return 0;
0651 
0652     fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
0653 
0654     /* the first fragment of DBGC1 is given to the FW via register
0655      * or context info
0656      */
0657     if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1)
0658         fw_mon_idx++;
0659 
0660     remain_frags = fw_mon->num_frags - fw_mon_idx;
0661     if (!remain_frags)
0662         return 0;
0663 
0664     num_commands = DIV_ROUND_UP(remain_frags, BUF_ALLOC_MAX_NUM_FRAGS);
0665 
0666     IWL_DEBUG_FW(fwrt, "WRT: Applying DRAM destination (alloc_id=%u)\n",
0667              alloc_id);
0668 
0669     for (i = 0; i < num_commands; i++) {
0670         u32 num_frags = min_t(u32, remain_frags,
0671                       BUF_ALLOC_MAX_NUM_FRAGS);
0672         struct iwl_buf_alloc_cmd data = {
0673             .alloc_id = cpu_to_le32(alloc_id),
0674             .num_frags = cpu_to_le32(num_frags),
0675             .buf_location =
0676                 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH),
0677         };
0678         struct iwl_host_cmd hcmd = {
0679             .id = WIDE_ID(DEBUG_GROUP, BUFFER_ALLOCATION),
0680             .data[0] = &data,
0681             .len[0] = sizeof(data),
0682             .flags = CMD_SEND_IN_RFKILL,
0683         };
0684         int ret, j;
0685 
0686         for (j = 0; j < num_frags; j++) {
0687             struct iwl_buf_alloc_frag *frag = &data.frags[j];
0688             struct iwl_dram_data *fw_mon_frag =
0689                 &fw_mon->frags[fw_mon_idx++];
0690 
0691             frag->addr = cpu_to_le64(fw_mon_frag->physical);
0692             frag->size = cpu_to_le32(fw_mon_frag->size);
0693         }
0694         ret = iwl_trans_send_cmd(fwrt->trans, &hcmd);
0695         if (ret)
0696             return ret;
0697 
0698         remain_frags -= num_frags;
0699     }
0700 
0701     return 0;
0702 }
0703 
0704 static void iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime *fwrt)
0705 {
0706     int ret, i;
0707 
0708     if (fw_has_capa(&fwrt->fw->ucode_capa,
0709             IWL_UCODE_TLV_CAPA_DRAM_FRAG_SUPPORT))
0710         return;
0711 
0712     for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) {
0713         ret = iwl_dbg_tlv_apply_buffer(fwrt, i);
0714         if (ret)
0715             IWL_WARN(fwrt,
0716                  "WRT: Failed to apply DRAM buffer for allocation id %d, ret=%d\n",
0717                  i, ret);
0718     }
0719 }
0720 
0721 static int iwl_dbg_tlv_update_dram(struct iwl_fw_runtime *fwrt,
0722                    enum iwl_fw_ini_allocation_id alloc_id,
0723                    struct iwl_dram_info *dram_info)
0724 {
0725     struct iwl_fw_mon *fw_mon;
0726     u32 remain_frags, num_frags;
0727     int j, fw_mon_idx = 0;
0728     struct iwl_buf_alloc_cmd *data;
0729 
0730     if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) !=
0731             IWL_FW_INI_LOCATION_DRAM_PATH) {
0732         IWL_DEBUG_FW(fwrt, "DRAM_PATH is not supported alloc_id %u\n", alloc_id);
0733         return -1;
0734     }
0735 
0736     fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
0737 
0738     /* the first fragment of DBGC1 is given to the FW via register
0739      * or context info
0740      */
0741     if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1)
0742         fw_mon_idx++;
0743 
0744     remain_frags = fw_mon->num_frags - fw_mon_idx;
0745     if (!remain_frags)
0746         return -1;
0747 
0748     num_frags = min_t(u32, remain_frags, BUF_ALLOC_MAX_NUM_FRAGS);
0749     data = &dram_info->dram_frags[alloc_id - 1];
0750     data->alloc_id = cpu_to_le32(alloc_id);
0751     data->num_frags = cpu_to_le32(num_frags);
0752     data->buf_location = cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH);
0753 
0754     IWL_DEBUG_FW(fwrt, "WRT: DRAM buffer details alloc_id=%u, num_frags=%u\n",
0755              cpu_to_le32(alloc_id), cpu_to_le32(num_frags));
0756 
0757     for (j = 0; j < num_frags; j++) {
0758         struct iwl_buf_alloc_frag *frag = &data->frags[j];
0759         struct iwl_dram_data *fw_mon_frag = &fw_mon->frags[fw_mon_idx++];
0760 
0761         frag->addr = cpu_to_le64(fw_mon_frag->physical);
0762         frag->size = cpu_to_le32(fw_mon_frag->size);
0763         IWL_DEBUG_FW(fwrt, "WRT: DRAM fragment details\n");
0764         IWL_DEBUG_FW(fwrt, "frag=%u, addr=0x%016llx, size=0x%x)\n",
0765                  j, cpu_to_le64(fw_mon_frag->physical),
0766                  cpu_to_le32(fw_mon_frag->size));
0767     }
0768     return 0;
0769 }
0770 
0771 static void iwl_dbg_tlv_update_drams(struct iwl_fw_runtime *fwrt)
0772 {
0773     int ret, i;
0774     bool dram_alloc = false;
0775     struct iwl_dram_data *frags =
0776         &fwrt->trans->dbg.fw_mon_ini[IWL_FW_INI_ALLOCATION_ID_DBGC1].frags[0];
0777     struct iwl_dram_info *dram_info;
0778 
0779     if (!frags || !frags->block)
0780         return;
0781 
0782     dram_info = frags->block;
0783 
0784     if (!fw_has_capa(&fwrt->fw->ucode_capa,
0785              IWL_UCODE_TLV_CAPA_DRAM_FRAG_SUPPORT))
0786         return;
0787 
0788     dram_info->first_word = cpu_to_le32(DRAM_INFO_FIRST_MAGIC_WORD);
0789     dram_info->second_word = cpu_to_le32(DRAM_INFO_SECOND_MAGIC_WORD);
0790 
0791     for (i = IWL_FW_INI_ALLOCATION_ID_DBGC1;
0792          i <= IWL_FW_INI_ALLOCATION_ID_DBGC3; i++) {
0793         ret = iwl_dbg_tlv_update_dram(fwrt, i, dram_info);
0794         if (!ret)
0795             dram_alloc = true;
0796         else
0797             IWL_WARN(fwrt,
0798                  "WRT: Failed to set DRAM buffer for alloc id %d, ret=%d\n",
0799                  i, ret);
0800     }
0801 
0802     if (dram_alloc)
0803         IWL_DEBUG_FW(fwrt, "block data after  %08x\n",
0804                  dram_info->first_word);
0805     else
0806         memset(frags->block, 0, sizeof(*dram_info));
0807 }
0808 
0809 static void iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime *fwrt,
0810                    struct list_head *hcmd_list)
0811 {
0812     struct iwl_dbg_tlv_node *node;
0813 
0814     list_for_each_entry(node, hcmd_list, list) {
0815         struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)node->tlv.data;
0816         struct iwl_fw_ini_hcmd *hcmd_data = &hcmd->hcmd;
0817         u16 hcmd_len = le32_to_cpu(node->tlv.length) - sizeof(*hcmd);
0818         struct iwl_host_cmd cmd = {
0819             .id = WIDE_ID(hcmd_data->group, hcmd_data->id),
0820             .len = { hcmd_len, },
0821             .data = { hcmd_data->data, },
0822         };
0823 
0824         iwl_trans_send_cmd(fwrt->trans, &cmd);
0825     }
0826 }
0827 
0828 static void iwl_dbg_tlv_apply_config(struct iwl_fw_runtime *fwrt,
0829                      struct list_head *conf_list)
0830 {
0831     struct iwl_dbg_tlv_node *node;
0832 
0833     list_for_each_entry(node, conf_list, list) {
0834         struct iwl_fw_ini_conf_set_tlv *config_list = (void *)node->tlv.data;
0835         u32 count, address, value;
0836         u32 len = (le32_to_cpu(node->tlv.length) - sizeof(*config_list)) / 8;
0837         u32 type = le32_to_cpu(config_list->set_type);
0838         u32 offset = le32_to_cpu(config_list->addr_offset);
0839 
0840         switch (type) {
0841         case IWL_FW_INI_CONFIG_SET_TYPE_DEVICE_PERIPHERY_MAC: {
0842             if (!iwl_trans_grab_nic_access(fwrt->trans)) {
0843                 IWL_DEBUG_FW(fwrt, "WRT: failed to get nic access\n");
0844                 IWL_DEBUG_FW(fwrt, "WRT: skipping MAC PERIPHERY config\n");
0845                 continue;
0846             }
0847             IWL_DEBUG_FW(fwrt, "WRT:  MAC PERIPHERY config len: len %u\n", len);
0848             for (count = 0; count < len; count++) {
0849                 address = le32_to_cpu(config_list->addr_val[count].address);
0850                 value = le32_to_cpu(config_list->addr_val[count].value);
0851                 iwl_trans_write_prph(fwrt->trans, address + offset, value);
0852             }
0853             iwl_trans_release_nic_access(fwrt->trans);
0854         break;
0855         }
0856         case IWL_FW_INI_CONFIG_SET_TYPE_DEVICE_MEMORY: {
0857             for (count = 0; count < len; count++) {
0858                 address = le32_to_cpu(config_list->addr_val[count].address);
0859                 value = le32_to_cpu(config_list->addr_val[count].value);
0860                 iwl_trans_write_mem32(fwrt->trans, address + offset, value);
0861                 IWL_DEBUG_FW(fwrt, "WRT: DEV_MEM: count %u, add: %u val: %u\n",
0862                          count, address, value);
0863             }
0864         break;
0865         }
0866         case IWL_FW_INI_CONFIG_SET_TYPE_CSR: {
0867             for (count = 0; count < len; count++) {
0868                 address = le32_to_cpu(config_list->addr_val[count].address);
0869                 value = le32_to_cpu(config_list->addr_val[count].value);
0870                 iwl_write32(fwrt->trans, address + offset, value);
0871                 IWL_DEBUG_FW(fwrt, "WRT: CSR: count %u, add: %u val: %u\n",
0872                          count, address, value);
0873             }
0874         break;
0875         }
0876         case IWL_FW_INI_CONFIG_SET_TYPE_DBGC_DRAM_ADDR: {
0877             struct iwl_dbgc1_info dram_info = {};
0878             struct iwl_dram_data *frags = &fwrt->trans->dbg.fw_mon_ini[1].frags[0];
0879             __le64 dram_base_addr;
0880             __le32 dram_size;
0881             u64 dram_addr;
0882             u32 ret;
0883 
0884             if (!frags)
0885                 break;
0886 
0887             dram_base_addr = cpu_to_le64(frags->physical);
0888             dram_size = cpu_to_le32(frags->size);
0889             dram_addr = le64_to_cpu(dram_base_addr);
0890 
0891             IWL_DEBUG_FW(fwrt, "WRT: dram_base_addr 0x%016llx, dram_size 0x%x\n",
0892                      dram_base_addr, dram_size);
0893             IWL_DEBUG_FW(fwrt, "WRT: config_list->addr_offset: %u\n",
0894                      le32_to_cpu(config_list->addr_offset));
0895             for (count = 0; count < len; count++) {
0896                 address = le32_to_cpu(config_list->addr_val[count].address);
0897                 dram_info.dbgc1_add_lsb =
0898                     cpu_to_le32((dram_addr & 0x00000000FFFFFFFFULL) + 0x400);
0899                 dram_info.dbgc1_add_msb =
0900                     cpu_to_le32((dram_addr & 0xFFFFFFFF00000000ULL) >> 32);
0901                 dram_info.dbgc1_size = cpu_to_le32(le32_to_cpu(dram_size) - 0x400);
0902                 ret = iwl_trans_write_mem(fwrt->trans,
0903                               address + offset, &dram_info, 4);
0904                 if (ret) {
0905                     IWL_ERR(fwrt, "Failed to write dram_info to HW_SMEM\n");
0906                     break;
0907                 }
0908             }
0909             break;
0910         }
0911         case IWL_FW_INI_CONFIG_SET_TYPE_PERIPH_SCRATCH_HWM: {
0912             u32 debug_token_config =
0913                 le32_to_cpu(config_list->addr_val[0].value);
0914 
0915             IWL_DEBUG_FW(fwrt, "WRT: Setting HWM debug token config: %u\n",
0916                      debug_token_config);
0917             fwrt->trans->dbg.ucode_preset = debug_token_config;
0918             break;
0919         }
0920         default:
0921             break;
0922         }
0923     }
0924 }
0925 
0926 static void iwl_dbg_tlv_periodic_trig_handler(struct timer_list *t)
0927 {
0928     struct iwl_dbg_tlv_timer_node *timer_node =
0929         from_timer(timer_node, t, timer);
0930     struct iwl_fwrt_dump_data dump_data = {
0931         .trig = (void *)timer_node->tlv->data,
0932     };
0933     int ret;
0934 
0935     ret = iwl_fw_dbg_ini_collect(timer_node->fwrt, &dump_data, false);
0936     if (!ret || ret == -EBUSY) {
0937         u32 occur = le32_to_cpu(dump_data.trig->occurrences);
0938         u32 collect_interval = le32_to_cpu(dump_data.trig->data[0]);
0939 
0940         if (!occur)
0941             return;
0942 
0943         mod_timer(t, jiffies + msecs_to_jiffies(collect_interval));
0944     }
0945 }
0946 
0947 static void iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime *fwrt)
0948 {
0949     struct iwl_dbg_tlv_node *node;
0950     struct list_head *trig_list =
0951         &fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list;
0952 
0953     list_for_each_entry(node, trig_list, list) {
0954         struct iwl_fw_ini_trigger_tlv *trig = (void *)node->tlv.data;
0955         struct iwl_dbg_tlv_timer_node *timer_node;
0956         u32 occur = le32_to_cpu(trig->occurrences), collect_interval;
0957         u32 min_interval = 100;
0958 
0959         if (!occur)
0960             continue;
0961 
0962         /* make sure there is at least one dword of data for the
0963          * interval value
0964          */
0965         if (le32_to_cpu(node->tlv.length) <
0966             sizeof(*trig) + sizeof(__le32)) {
0967             IWL_ERR(fwrt,
0968                 "WRT: Invalid periodic trigger data was not given\n");
0969             continue;
0970         }
0971 
0972         if (le32_to_cpu(trig->data[0]) < min_interval) {
0973             IWL_WARN(fwrt,
0974                  "WRT: Override min interval from %u to %u msec\n",
0975                  le32_to_cpu(trig->data[0]), min_interval);
0976             trig->data[0] = cpu_to_le32(min_interval);
0977         }
0978 
0979         collect_interval = le32_to_cpu(trig->data[0]);
0980 
0981         timer_node = kzalloc(sizeof(*timer_node), GFP_KERNEL);
0982         if (!timer_node) {
0983             IWL_ERR(fwrt,
0984                 "WRT: Failed to allocate periodic trigger\n");
0985             continue;
0986         }
0987 
0988         timer_node->fwrt = fwrt;
0989         timer_node->tlv = &node->tlv;
0990         timer_setup(&timer_node->timer,
0991                 iwl_dbg_tlv_periodic_trig_handler, 0);
0992 
0993         list_add_tail(&timer_node->list,
0994                   &fwrt->trans->dbg.periodic_trig_list);
0995 
0996         IWL_DEBUG_FW(fwrt, "WRT: Enabling periodic trigger\n");
0997 
0998         mod_timer(&timer_node->timer,
0999               jiffies + msecs_to_jiffies(collect_interval));
1000     }
1001 }
1002 
1003 static bool is_trig_data_contained(const struct iwl_ucode_tlv *new,
1004                    const struct iwl_ucode_tlv *old)
1005 {
1006     const struct iwl_fw_ini_trigger_tlv *new_trig = (const void *)new->data;
1007     const struct iwl_fw_ini_trigger_tlv *old_trig = (const void *)old->data;
1008     const __le32 *new_data = new_trig->data, *old_data = old_trig->data;
1009     u32 new_dwords_num = iwl_tlv_array_len(new, new_trig, data);
1010     u32 old_dwords_num = iwl_tlv_array_len(old, old_trig, data);
1011     int i, j;
1012 
1013     for (i = 0; i < new_dwords_num; i++) {
1014         bool match = false;
1015 
1016         for (j = 0; j < old_dwords_num; j++) {
1017             if (new_data[i] == old_data[j]) {
1018                 match = true;
1019                 break;
1020             }
1021         }
1022         if (!match)
1023             return false;
1024     }
1025 
1026     return true;
1027 }
1028 
1029 static int iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime *fwrt,
1030                       struct iwl_ucode_tlv *trig_tlv,
1031                       struct iwl_dbg_tlv_node *node)
1032 {
1033     struct iwl_ucode_tlv *node_tlv = &node->tlv;
1034     struct iwl_fw_ini_trigger_tlv *node_trig = (void *)node_tlv->data;
1035     struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data;
1036     u32 policy = le32_to_cpu(trig->apply_policy);
1037     u32 size = le32_to_cpu(trig_tlv->length);
1038     u32 trig_data_len = size - sizeof(*trig);
1039     u32 offset = 0;
1040 
1041     if (!(policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_DATA)) {
1042         u32 data_len = le32_to_cpu(node_tlv->length) -
1043             sizeof(*node_trig);
1044 
1045         IWL_DEBUG_FW(fwrt,
1046                  "WRT: Appending trigger data (time point %u)\n",
1047                  le32_to_cpu(trig->time_point));
1048 
1049         offset += data_len;
1050         size += data_len;
1051     } else {
1052         IWL_DEBUG_FW(fwrt,
1053                  "WRT: Overriding trigger data (time point %u)\n",
1054                  le32_to_cpu(trig->time_point));
1055     }
1056 
1057     if (size != le32_to_cpu(node_tlv->length)) {
1058         struct list_head *prev = node->list.prev;
1059         struct iwl_dbg_tlv_node *tmp;
1060 
1061         list_del(&node->list);
1062 
1063         tmp = krealloc(node, sizeof(*node) + size, GFP_KERNEL);
1064         if (!tmp) {
1065             IWL_WARN(fwrt,
1066                  "WRT: No memory to override trigger (time point %u)\n",
1067                  le32_to_cpu(trig->time_point));
1068 
1069             list_add(&node->list, prev);
1070 
1071             return -ENOMEM;
1072         }
1073 
1074         list_add(&tmp->list, prev);
1075         node_tlv = &tmp->tlv;
1076         node_trig = (void *)node_tlv->data;
1077     }
1078 
1079     memcpy(node_trig->data + offset, trig->data, trig_data_len);
1080     node_tlv->length = cpu_to_le32(size);
1081 
1082     if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_CFG) {
1083         IWL_DEBUG_FW(fwrt,
1084                  "WRT: Overriding trigger configuration (time point %u)\n",
1085                  le32_to_cpu(trig->time_point));
1086 
1087         /* the first 11 dwords are configuration related */
1088         memcpy(node_trig, trig, sizeof(__le32) * 11);
1089     }
1090 
1091     if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_REGIONS) {
1092         IWL_DEBUG_FW(fwrt,
1093                  "WRT: Overriding trigger regions (time point %u)\n",
1094                  le32_to_cpu(trig->time_point));
1095 
1096         node_trig->regions_mask = trig->regions_mask;
1097     } else {
1098         IWL_DEBUG_FW(fwrt,
1099                  "WRT: Appending trigger regions (time point %u)\n",
1100                  le32_to_cpu(trig->time_point));
1101 
1102         node_trig->regions_mask |= trig->regions_mask;
1103     }
1104 
1105     return 0;
1106 }
1107 
1108 static int
1109 iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime *fwrt,
1110                    struct list_head *trig_list,
1111                    struct iwl_ucode_tlv *trig_tlv)
1112 {
1113     struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data;
1114     struct iwl_dbg_tlv_node *node, *match = NULL;
1115     u32 policy = le32_to_cpu(trig->apply_policy);
1116 
1117     list_for_each_entry(node, trig_list, list) {
1118         if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_TIME_POINT))
1119             break;
1120 
1121         if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_DATA) ||
1122             is_trig_data_contained(trig_tlv, &node->tlv)) {
1123             match = node;
1124             break;
1125         }
1126     }
1127 
1128     if (!match) {
1129         IWL_DEBUG_FW(fwrt, "WRT: Enabling trigger (time point %u)\n",
1130                  le32_to_cpu(trig->time_point));
1131         return iwl_dbg_tlv_add(trig_tlv, trig_list);
1132     }
1133 
1134     return iwl_dbg_tlv_override_trig_node(fwrt, trig_tlv, match);
1135 }
1136 
1137 static void
1138 iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime *fwrt,
1139                  struct iwl_dbg_tlv_time_point_data *tp)
1140 {
1141     struct iwl_dbg_tlv_node *node;
1142     struct list_head *trig_list = &tp->trig_list;
1143     struct list_head *active_trig_list = &tp->active_trig_list;
1144 
1145     list_for_each_entry(node, trig_list, list) {
1146         struct iwl_ucode_tlv *tlv = &node->tlv;
1147 
1148         iwl_dbg_tlv_add_active_trigger(fwrt, active_trig_list, tlv);
1149     }
1150 }
1151 
1152 static bool iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime *fwrt,
1153                      struct iwl_fwrt_dump_data *dump_data,
1154                      union iwl_dbg_tlv_tp_data *tp_data,
1155                      u32 trig_data)
1156 {
1157     struct iwl_rx_packet *pkt = tp_data->fw_pkt;
1158     struct iwl_cmd_header *wanted_hdr = (void *)&trig_data;
1159 
1160     if (pkt && (pkt->hdr.cmd == wanted_hdr->cmd &&
1161             pkt->hdr.group_id == wanted_hdr->group_id)) {
1162         struct iwl_rx_packet *fw_pkt =
1163             kmemdup(pkt,
1164                 sizeof(*pkt) + iwl_rx_packet_payload_len(pkt),
1165                 GFP_ATOMIC);
1166 
1167         if (!fw_pkt)
1168             return false;
1169 
1170         dump_data->fw_pkt = fw_pkt;
1171 
1172         return true;
1173     }
1174 
1175     return false;
1176 }
1177 
1178 static int
1179 iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime *fwrt, bool sync,
1180                struct list_head *active_trig_list,
1181                union iwl_dbg_tlv_tp_data *tp_data,
1182                bool (*data_check)(struct iwl_fw_runtime *fwrt,
1183                       struct iwl_fwrt_dump_data *dump_data,
1184                       union iwl_dbg_tlv_tp_data *tp_data,
1185                       u32 trig_data))
1186 {
1187     struct iwl_dbg_tlv_node *node;
1188 
1189     list_for_each_entry(node, active_trig_list, list) {
1190         struct iwl_fwrt_dump_data dump_data = {
1191             .trig = (void *)node->tlv.data,
1192         };
1193         u32 num_data = iwl_tlv_array_len(&node->tlv, dump_data.trig,
1194                          data);
1195         int ret, i;
1196         u32 tp = le32_to_cpu(dump_data.trig->time_point);
1197 
1198 
1199         if (!num_data) {
1200             ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync);
1201             if (ret)
1202                 return ret;
1203         }
1204 
1205         for (i = 0; i < num_data; i++) {
1206             if (!data_check ||
1207                 data_check(fwrt, &dump_data, tp_data,
1208                        le32_to_cpu(dump_data.trig->data[i]))) {
1209                 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync);
1210                 if (ret)
1211                     return ret;
1212 
1213                 break;
1214             }
1215         }
1216 
1217         fwrt->trans->dbg.restart_required = FALSE;
1218         IWL_DEBUG_INFO(fwrt, "WRT: tp %d, reset_fw %d\n",
1219                    tp, dump_data.trig->reset_fw);
1220         IWL_DEBUG_INFO(fwrt, "WRT: restart_required %d, last_tp_resetfw %d\n",
1221                    fwrt->trans->dbg.restart_required,
1222                    fwrt->trans->dbg.last_tp_resetfw);
1223 
1224         if (fwrt->trans->trans_cfg->device_family ==
1225             IWL_DEVICE_FAMILY_9000) {
1226             fwrt->trans->dbg.restart_required = TRUE;
1227         } else if (tp == IWL_FW_INI_TIME_POINT_FW_ASSERT &&
1228                fwrt->trans->dbg.last_tp_resetfw ==
1229                IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) {
1230             fwrt->trans->dbg.restart_required = FALSE;
1231             fwrt->trans->dbg.last_tp_resetfw = 0xFF;
1232             IWL_DEBUG_FW(fwrt, "WRT: FW_ASSERT due to reset_fw_mode-no restart\n");
1233         } else if (le32_to_cpu(dump_data.trig->reset_fw) ==
1234                IWL_FW_INI_RESET_FW_MODE_STOP_AND_RELOAD_FW) {
1235             IWL_DEBUG_INFO(fwrt, "WRT: stop and reload firmware\n");
1236             fwrt->trans->dbg.restart_required = TRUE;
1237         } else if (le32_to_cpu(dump_data.trig->reset_fw) ==
1238                IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) {
1239             IWL_DEBUG_INFO(fwrt, "WRT: stop only and no reload firmware\n");
1240             fwrt->trans->dbg.restart_required = FALSE;
1241             fwrt->trans->dbg.last_tp_resetfw =
1242                 le32_to_cpu(dump_data.trig->reset_fw);
1243         } else if (le32_to_cpu(dump_data.trig->reset_fw) ==
1244                IWL_FW_INI_RESET_FW_MODE_NOTHING) {
1245             IWL_DEBUG_INFO(fwrt,
1246                        "WRT: nothing need to be done after debug collection\n");
1247         } else {
1248             IWL_ERR(fwrt, "WRT: wrong resetfw %d\n",
1249                 le32_to_cpu(dump_data.trig->reset_fw));
1250         }
1251     }
1252     return 0;
1253 }
1254 
1255 static void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt)
1256 {
1257     enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest;
1258     int ret, i;
1259     u32 failed_alloc = 0;
1260 
1261     if (*ini_dest != IWL_FW_INI_LOCATION_INVALID)
1262         return;
1263 
1264     IWL_DEBUG_FW(fwrt,
1265              "WRT: Generating active triggers list, domain 0x%x\n",
1266              fwrt->trans->dbg.domains_bitmap);
1267 
1268     for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) {
1269         struct iwl_dbg_tlv_time_point_data *tp =
1270             &fwrt->trans->dbg.time_point[i];
1271 
1272         iwl_dbg_tlv_gen_active_trig_list(fwrt, tp);
1273     }
1274 
1275     *ini_dest = IWL_FW_INI_LOCATION_INVALID;
1276     for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) {
1277         struct iwl_fw_ini_allocation_tlv *fw_mon_cfg =
1278             &fwrt->trans->dbg.fw_mon_cfg[i];
1279         u32 dest = le32_to_cpu(fw_mon_cfg->buf_location);
1280 
1281         if (dest == IWL_FW_INI_LOCATION_INVALID) {
1282             failed_alloc |= BIT(i);
1283             continue;
1284         }
1285 
1286         if (*ini_dest == IWL_FW_INI_LOCATION_INVALID)
1287             *ini_dest = dest;
1288 
1289         if (dest != *ini_dest)
1290             continue;
1291 
1292         ret = iwl_dbg_tlv_alloc_fragments(fwrt, i);
1293 
1294         if (ret) {
1295             IWL_WARN(fwrt,
1296                  "WRT: Failed to allocate DRAM buffer for allocation id %d, ret=%d\n",
1297                  i, ret);
1298             failed_alloc |= BIT(i);
1299         }
1300     }
1301 
1302     if (!failed_alloc)
1303         return;
1304 
1305     for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions) && failed_alloc; i++) {
1306         struct iwl_fw_ini_region_tlv *reg;
1307         struct iwl_ucode_tlv **active_reg =
1308             &fwrt->trans->dbg.active_regions[i];
1309         u32 reg_type;
1310 
1311         if (!*active_reg) {
1312             fwrt->trans->dbg.unsupported_region_msk |= BIT(i);
1313             continue;
1314         }
1315 
1316         reg = (void *)(*active_reg)->data;
1317         reg_type = reg->type;
1318 
1319         if (reg_type != IWL_FW_INI_REGION_DRAM_BUFFER ||
1320             !(BIT(le32_to_cpu(reg->dram_alloc_id)) & failed_alloc))
1321             continue;
1322 
1323         IWL_DEBUG_FW(fwrt,
1324                  "WRT: removing allocation id %d from region id %d\n",
1325                  le32_to_cpu(reg->dram_alloc_id), i);
1326 
1327         failed_alloc &= ~le32_to_cpu(reg->dram_alloc_id);
1328         fwrt->trans->dbg.unsupported_region_msk |= BIT(i);
1329 
1330         kfree(*active_reg);
1331         *active_reg = NULL;
1332     }
1333 }
1334 
1335 void _iwl_dbg_tlv_time_point(struct iwl_fw_runtime *fwrt,
1336                  enum iwl_fw_ini_time_point tp_id,
1337                  union iwl_dbg_tlv_tp_data *tp_data,
1338                  bool sync)
1339 {
1340     struct list_head *hcmd_list, *trig_list, *conf_list;
1341 
1342     if (!iwl_trans_dbg_ini_valid(fwrt->trans) ||
1343         tp_id == IWL_FW_INI_TIME_POINT_INVALID ||
1344         tp_id >= IWL_FW_INI_TIME_POINT_NUM)
1345         return;
1346 
1347     hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list;
1348     trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list;
1349     conf_list = &fwrt->trans->dbg.time_point[tp_id].config_list;
1350 
1351     switch (tp_id) {
1352     case IWL_FW_INI_TIME_POINT_EARLY:
1353         iwl_dbg_tlv_init_cfg(fwrt);
1354         iwl_dbg_tlv_apply_config(fwrt, conf_list);
1355         iwl_dbg_tlv_update_drams(fwrt);
1356         iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL);
1357         break;
1358     case IWL_FW_INI_TIME_POINT_AFTER_ALIVE:
1359         iwl_dbg_tlv_apply_buffers(fwrt);
1360         iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1361         iwl_dbg_tlv_apply_config(fwrt, conf_list);
1362         iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL);
1363         break;
1364     case IWL_FW_INI_TIME_POINT_PERIODIC:
1365         iwl_dbg_tlv_set_periodic_trigs(fwrt);
1366         iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1367         break;
1368     case IWL_FW_INI_TIME_POINT_FW_RSP_OR_NOTIF:
1369     case IWL_FW_INI_TIME_POINT_MISSED_BEACONS:
1370     case IWL_FW_INI_TIME_POINT_FW_DHC_NOTIFICATION:
1371         iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1372         iwl_dbg_tlv_apply_config(fwrt, conf_list);
1373         iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data,
1374                        iwl_dbg_tlv_check_fw_pkt);
1375         break;
1376     default:
1377         iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1378         iwl_dbg_tlv_apply_config(fwrt, conf_list);
1379         iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL);
1380         break;
1381     }
1382 }
1383 IWL_EXPORT_SYMBOL(_iwl_dbg_tlv_time_point);
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