intel/iwlwifi/iwl-context-info.h

0001 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
0002 /*
0003  * Copyright (C) 2017 Intel Deutschland GmbH
0004  * Copyright (C) 2018-2020 Intel Corporation
0005  */
0006 #ifndef __iwl_context_info_file_h__
0007 #define __iwl_context_info_file_h__
0008
0009 /* maximmum number of DRAM map entries supported by FW */
0010 #define IWL_MAX_DRAM_ENTRY  64
0011 #define CSR_CTXT_INFO_BA    0x40
0012
0013 /**
0014  * enum iwl_context_info_flags - Context information control flags
0015  * @IWL_CTXT_INFO_AUTO_FUNC_INIT: If set, FW will not wait before interrupting
0016  *  the init done for driver command that configures several system modes
0017  * @IWL_CTXT_INFO_EARLY_DEBUG: enable early debug
0018  * @IWL_CTXT_INFO_ENABLE_CDMP: enable core dump
0019  * @IWL_CTXT_INFO_RB_CB_SIZE: mask of the RBD Cyclic Buffer Size
0020  *  exponent, the actual size is 2**value, valid sizes are 8-2048.
0021  *  The value is four bits long. Maximum valid exponent is 12
0022  * @IWL_CTXT_INFO_TFD_FORMAT_LONG: use long TFD Format (the
0023  *  default is short format - not supported by the driver)
0024  * @IWL_CTXT_INFO_RB_SIZE: RB size mask
0025  *  (values are IWL_CTXT_INFO_RB_SIZE_*K)
0026  * @IWL_CTXT_INFO_RB_SIZE_1K: Value for 1K RB size
0027  * @IWL_CTXT_INFO_RB_SIZE_2K: Value for 2K RB size
0028  * @IWL_CTXT_INFO_RB_SIZE_4K: Value for 4K RB size
0029  * @IWL_CTXT_INFO_RB_SIZE_8K: Value for 8K RB size
0030  * @IWL_CTXT_INFO_RB_SIZE_12K: Value for 12K RB size
0031  * @IWL_CTXT_INFO_RB_SIZE_16K: Value for 16K RB size
0032  * @IWL_CTXT_INFO_RB_SIZE_20K: Value for 20K RB size
0033  * @IWL_CTXT_INFO_RB_SIZE_24K: Value for 24K RB size
0034  * @IWL_CTXT_INFO_RB_SIZE_28K: Value for 28K RB size
0035  * @IWL_CTXT_INFO_RB_SIZE_32K: Value for 32K RB size
0036  */
0037 enum iwl_context_info_flags {
0038     IWL_CTXT_INFO_AUTO_FUNC_INIT    = 0x0001,
0039     IWL_CTXT_INFO_EARLY_DEBUG   = 0x0002,
0040     IWL_CTXT_INFO_ENABLE_CDMP   = 0x0004,
0041     IWL_CTXT_INFO_RB_CB_SIZE    = 0x00f0,
0042     IWL_CTXT_INFO_TFD_FORMAT_LONG   = 0x0100,
0043     IWL_CTXT_INFO_RB_SIZE       = 0x1e00,
0044     IWL_CTXT_INFO_RB_SIZE_1K    = 0x1,
0045     IWL_CTXT_INFO_RB_SIZE_2K    = 0x2,
0046     IWL_CTXT_INFO_RB_SIZE_4K    = 0x4,
0047     IWL_CTXT_INFO_RB_SIZE_8K    = 0x8,
0048     IWL_CTXT_INFO_RB_SIZE_12K   = 0x9,
0049     IWL_CTXT_INFO_RB_SIZE_16K   = 0xa,
0050     IWL_CTXT_INFO_RB_SIZE_20K   = 0xb,
0051     IWL_CTXT_INFO_RB_SIZE_24K   = 0xc,
0052     IWL_CTXT_INFO_RB_SIZE_28K   = 0xd,
0053     IWL_CTXT_INFO_RB_SIZE_32K   = 0xe,
0054 };
0055
0056 /*
0057  * struct iwl_context_info_version - version structure
0058  * @mac_id: SKU and revision id
0059  * @version: context information version id
0060  * @size: the size of the context information in DWs
0061  */
0062 struct iwl_context_info_version {
0063     __le16 mac_id;
0064     __le16 version;
0065     __le16 size;
0066     __le16 reserved;
0067 } __packed;
0068
0069 /*
0070  * struct iwl_context_info_control - version structure
0071  * @control_flags: context information flags see &enum iwl_context_info_flags
0072  */
0073 struct iwl_context_info_control {
0074     __le32 control_flags;
0075     __le32 reserved;
0076 } __packed;
0077
0078 /*
0079  * struct iwl_context_info_dram - images DRAM map
0080  * each entry in the map represents a DRAM chunk of up to 32 KB
0081  * @umac_img: UMAC image DRAM map
0082  * @lmac_img: LMAC image DRAM map
0083  * @virtual_img: paged image DRAM map
0084  */
0085 struct iwl_context_info_dram {
0086     __le64 umac_img[IWL_MAX_DRAM_ENTRY];
0087     __le64 lmac_img[IWL_MAX_DRAM_ENTRY];
0088     __le64 virtual_img[IWL_MAX_DRAM_ENTRY];
0089 } __packed;
0090
0091 /*
0092  * struct iwl_context_info_rbd_cfg - RBDs configuration
0093  * @free_rbd_addr: default queue free RB CB base address
0094  * @used_rbd_addr: default queue used RB CB base address
0095  * @status_wr_ptr: default queue used RB status write pointer
0096  */
0097 struct iwl_context_info_rbd_cfg {
0098     __le64 free_rbd_addr;
0099     __le64 used_rbd_addr;
0100     __le64 status_wr_ptr;
0101 } __packed;
0102
0103 /*
0104  * struct iwl_context_info_hcmd_cfg  - command queue configuration
0105  * @cmd_queue_addr: address of command queue
0106  * @cmd_queue_size: number of entries
0107  */
0108 struct iwl_context_info_hcmd_cfg {
0109     __le64 cmd_queue_addr;
0110     u8 cmd_queue_size;
0111     u8 reserved[7];
0112 } __packed;
0113
0114 /*
0115  * struct iwl_context_info_dump_cfg - Core Dump configuration
0116  * @core_dump_addr: core dump (debug DRAM address) start address
0117  * @core_dump_size: size, in DWs
0118  */
0119 struct iwl_context_info_dump_cfg {
0120     __le64 core_dump_addr;
0121     __le32 core_dump_size;
0122     __le32 reserved;
0123 } __packed;
0124
0125 /*
0126  * struct iwl_context_info_pnvm_cfg - platform NVM data configuration
0127  * @platform_nvm_addr: Platform NVM data start address
0128  * @platform_nvm_size: size in DWs
0129  */
0130 struct iwl_context_info_pnvm_cfg {
0131     __le64 platform_nvm_addr;
0132     __le32 platform_nvm_size;
0133     __le32 reserved;
0134 } __packed;
0135
0136 /*
0137  * struct iwl_context_info_early_dbg_cfg - early debug configuration for
0138  *  dumping DRAM addresses
0139  * @early_debug_addr: early debug start address
0140  * @early_debug_size: size in DWs
0141  */
0142 struct iwl_context_info_early_dbg_cfg {
0143     __le64 early_debug_addr;
0144     __le32 early_debug_size;
0145     __le32 reserved;
0146 } __packed;
0147
0148 /*
0149  * struct iwl_context_info - device INIT configuration
0150  * @version: version information of context info and HW
0151  * @control: control flags of FH configurations
0152  * @rbd_cfg: default RX queue configuration
0153  * @hcmd_cfg: command queue configuration
0154  * @dump_cfg: core dump data
0155  * @edbg_cfg: early debug configuration
0156  * @pnvm_cfg: platform nvm configuration
0157  * @dram: firmware image addresses in DRAM
0158  */
0159 struct iwl_context_info {
0160     struct iwl_context_info_version version;
0161     struct iwl_context_info_control control;
0162     __le64 reserved0;
0163     struct iwl_context_info_rbd_cfg rbd_cfg;
0164     struct iwl_context_info_hcmd_cfg hcmd_cfg;
0165     __le32 reserved1[4];
0166     struct iwl_context_info_dump_cfg dump_cfg;
0167     struct iwl_context_info_early_dbg_cfg edbg_cfg;
0168     struct iwl_context_info_pnvm_cfg pnvm_cfg;
0169     __le32 reserved2[16];
0170     struct iwl_context_info_dram dram;
0171     __le32 reserved3[16];
0172 } __packed;
0173
0174 int iwl_pcie_ctxt_info_init(struct iwl_trans *trans, const struct fw_img *fw);
0175 void iwl_pcie_ctxt_info_free(struct iwl_trans *trans);
0176 void iwl_pcie_ctxt_info_free_paging(struct iwl_trans *trans);
0177 int iwl_pcie_init_fw_sec(struct iwl_trans *trans,
0178              const struct fw_img *fw,
0179              struct iwl_context_info_dram *ctxt_dram);
0180 int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans,
0181                  const void *data, u32 len,
0182                  struct iwl_dram_data *dram);
0183
0184 #endif /* __iwl_context_info_file_h__ */