intel/iwlwifi/iwl-context-info-gen3.h

0001 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
0002 /*
0003  * Copyright (C) 2018, 2020-2022 Intel Corporation
0004  */
0005 #ifndef __iwl_context_info_file_gen3_h__
0006 #define __iwl_context_info_file_gen3_h__
0007
0008 #include "iwl-context-info.h"
0009
0010 #define CSR_CTXT_INFO_BOOT_CTRL         0x0
0011 #define CSR_CTXT_INFO_ADDR              0x118
0012 #define CSR_IML_DATA_ADDR               0x120
0013 #define CSR_IML_SIZE_ADDR               0x128
0014 #define CSR_IML_RESP_ADDR               0x12c
0015
0016 /* Set bit for enabling automatic function boot */
0017 #define CSR_AUTO_FUNC_BOOT_ENA          BIT(1)
0018 /* Set bit for initiating function boot */
0019 #define CSR_AUTO_FUNC_INIT              BIT(7)
0020
0021 /**
0022  * enum iwl_prph_scratch_mtr_format - tfd size configuration
0023  * @IWL_PRPH_MTR_FORMAT_16B: 16 bit tfd
0024  * @IWL_PRPH_MTR_FORMAT_32B: 32 bit tfd
0025  * @IWL_PRPH_MTR_FORMAT_64B: 64 bit tfd
0026  * @IWL_PRPH_MTR_FORMAT_256B: 256 bit tfd
0027  */
0028 enum iwl_prph_scratch_mtr_format {
0029     IWL_PRPH_MTR_FORMAT_16B = 0x0,
0030     IWL_PRPH_MTR_FORMAT_32B = 0x40000,
0031     IWL_PRPH_MTR_FORMAT_64B = 0x80000,
0032     IWL_PRPH_MTR_FORMAT_256B = 0xC0000,
0033 };
0034
0035 /**
0036  * enum iwl_prph_scratch_flags - PRPH scratch control flags
0037  * @IWL_PRPH_SCRATCH_IMR_DEBUG_EN: IMR support for debug
0038  * @IWL_PRPH_SCRATCH_EARLY_DEBUG_EN: enable early debug conf
0039  * @IWL_PRPH_SCRATCH_EDBG_DEST_DRAM: use DRAM, with size allocated
0040  *  in hwm config.
0041  * @IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL: use buffer on SRAM
0042  * @IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER: use st arbiter, mainly for
0043  *  multicomm.
0044  * @IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF: route debug data to SoC HW
0045  * @IWL_PRPH_SCTATCH_RB_SIZE_4K: Use 4K RB size (the default is 2K)
0046  * @IWL_PRPH_SCRATCH_MTR_MODE: format used for completion - 0: for
0047  *  completion descriptor, 1 for responses (legacy)
0048  * @IWL_PRPH_SCRATCH_MTR_FORMAT: a mask for the size of the tfd.
0049  *  There are 4 optional values: 0: 16 bit, 1: 32 bit, 2: 64 bit,
0050  *  3: 256 bit.
0051  * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK: RB size full information, ignored
0052  *  by older firmware versions, so set IWL_PRPH_SCRATCH_RB_SIZE_4K
0053  *  appropriately; use the below values for this.
0054  * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K: 8kB RB size
0055  * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K: 12kB RB size
0056  * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K: 16kB RB size
0057  */
0058 enum iwl_prph_scratch_flags {
0059     IWL_PRPH_SCRATCH_IMR_DEBUG_EN       = BIT(1),
0060     IWL_PRPH_SCRATCH_EARLY_DEBUG_EN     = BIT(4),
0061     IWL_PRPH_SCRATCH_EDBG_DEST_DRAM     = BIT(8),
0062     IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL = BIT(9),
0063     IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER   = BIT(10),
0064     IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF  = BIT(11),
0065     IWL_PRPH_SCRATCH_RB_SIZE_4K     = BIT(16),
0066     IWL_PRPH_SCRATCH_MTR_MODE       = BIT(17),
0067     IWL_PRPH_SCRATCH_MTR_FORMAT     = BIT(18) | BIT(19),
0068     IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK   = 0xf << 20,
0069     IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K     = 8 << 20,
0070     IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K    = 9 << 20,
0071     IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K    = 10 << 20,
0072 };
0073
0074 /*
0075  * struct iwl_prph_scratch_version - version structure
0076  * @mac_id: SKU and revision id
0077  * @version: prph scratch information version id
0078  * @size: the size of the context information in DWs
0079  * @reserved: reserved
0080  */
0081 struct iwl_prph_scratch_version {
0082     __le16 mac_id;
0083     __le16 version;
0084     __le16 size;
0085     __le16 reserved;
0086 } __packed; /* PERIPH_SCRATCH_VERSION_S */
0087
0088 /*
0089  * struct iwl_prph_scratch_control - control structure
0090  * @control_flags: context information flags see &enum iwl_prph_scratch_flags
0091  * @reserved: reserved
0092  */
0093 struct iwl_prph_scratch_control {
0094     __le32 control_flags;
0095     __le32 reserved;
0096 } __packed; /* PERIPH_SCRATCH_CONTROL_S */
0097
0098 /*
0099  * struct iwl_prph_scratch_pnvm_cfg - ror config
0100  * @pnvm_base_addr: PNVM start address
0101  * @pnvm_size: PNVM size in DWs
0102  * @reserved: reserved
0103  */
0104 struct iwl_prph_scratch_pnvm_cfg {
0105     __le64 pnvm_base_addr;
0106     __le32 pnvm_size;
0107     __le32 reserved;
0108 } __packed; /* PERIPH_SCRATCH_PNVM_CFG_S */
0109
0110 /*
0111  * struct iwl_prph_scratch_hwm_cfg - hwm config
0112  * @hwm_base_addr: hwm start address
0113  * @hwm_size: hwm size in DWs
0114  * @debug_token_config: debug preset
0115  */
0116 struct iwl_prph_scratch_hwm_cfg {
0117     __le64 hwm_base_addr;
0118     __le32 hwm_size;
0119     __le32 debug_token_config;
0120 } __packed; /* PERIPH_SCRATCH_HWM_CFG_S */
0121
0122 /*
0123  * struct iwl_prph_scratch_rbd_cfg - RBDs configuration
0124  * @free_rbd_addr: default queue free RB CB base address
0125  * @reserved: reserved
0126  */
0127 struct iwl_prph_scratch_rbd_cfg {
0128     __le64 free_rbd_addr;
0129     __le32 reserved;
0130 } __packed; /* PERIPH_SCRATCH_RBD_CFG_S */
0131
0132 /*
0133  * struct iwl_prph_scratch_uefi_cfg - prph scratch reduce power table
0134  * @base_addr: reduce power table address
0135  * @size: table size in dwords
0136  */
0137 struct iwl_prph_scratch_uefi_cfg {
0138     __le64 base_addr;
0139     __le32 size;
0140     __le32 reserved;
0141 } __packed; /* PERIPH_SCRATCH_UEFI_CFG_S */
0142
0143 /*
0144  * struct iwl_prph_scratch_ctrl_cfg - prph scratch ctrl and config
0145  * @version: version information of context info and HW
0146  * @control: control flags of FH configurations
0147  * @pnvm_cfg: ror configuration
0148  * @hwm_cfg: hwm configuration
0149  * @rbd_cfg: default RX queue configuration
0150  */
0151 struct iwl_prph_scratch_ctrl_cfg {
0152     struct iwl_prph_scratch_version version;
0153     struct iwl_prph_scratch_control control;
0154     struct iwl_prph_scratch_pnvm_cfg pnvm_cfg;
0155     struct iwl_prph_scratch_hwm_cfg hwm_cfg;
0156     struct iwl_prph_scratch_rbd_cfg rbd_cfg;
0157     struct iwl_prph_scratch_uefi_cfg reduce_power_cfg;
0158 } __packed; /* PERIPH_SCRATCH_CTRL_CFG_S */
0159
0160 /*
0161  * struct iwl_prph_scratch - peripheral scratch mapping
0162  * @ctrl_cfg: control and configuration of prph scratch
0163  * @dram: firmware images addresses in DRAM
0164  * @reserved: reserved
0165  */
0166 struct iwl_prph_scratch {
0167     struct iwl_prph_scratch_ctrl_cfg ctrl_cfg;
0168     __le32 reserved[12];
0169     struct iwl_context_info_dram dram;
0170 } __packed; /* PERIPH_SCRATCH_S */
0171
0172 /*
0173  * struct iwl_prph_info - peripheral information
0174  * @boot_stage_mirror: reflects the value in the Boot Stage CSR register
0175  * @ipc_status_mirror: reflects the value in the IPC Status CSR register
0176  * @sleep_notif: indicates the peripheral sleep status
0177  * @reserved: reserved
0178  */
0179 struct iwl_prph_info {
0180     __le32 boot_stage_mirror;
0181     __le32 ipc_status_mirror;
0182     __le32 sleep_notif;
0183     __le32 reserved;
0184 } __packed; /* PERIPH_INFO_S */
0185
0186 /*
0187  * struct iwl_context_info_gen3 - device INIT configuration
0188  * @version: version of the context information
0189  * @size: size of context information in DWs
0190  * @config: context in which the peripheral would execute - a subset of
0191  *  capability csr register published by the peripheral
0192  * @prph_info_base_addr: the peripheral information structure start address
0193  * @cr_head_idx_arr_base_addr: the completion ring head index array
0194  *  start address
0195  * @tr_tail_idx_arr_base_addr: the transfer ring tail index array
0196  *  start address
0197  * @cr_tail_idx_arr_base_addr: the completion ring tail index array
0198  *  start address
0199  * @tr_head_idx_arr_base_addr: the transfer ring head index array
0200  *  start address
0201  * @cr_idx_arr_size: number of entries in the completion ring index array
0202  * @tr_idx_arr_size: number of entries in the transfer ring index array
0203  * @mtr_base_addr: the message transfer ring start address
0204  * @mcr_base_addr: the message completion ring start address
0205  * @mtr_size: number of entries which the message transfer ring can hold
0206  * @mcr_size: number of entries which the message completion ring can hold
0207  * @mtr_doorbell_vec: the doorbell vector associated with the message
0208  *  transfer ring
0209  * @mcr_doorbell_vec: the doorbell vector associated with the message
0210  *  completion ring
0211  * @mtr_msi_vec: the MSI which shall be generated by the peripheral after
0212  *  completing a transfer descriptor in the message transfer ring
0213  * @mcr_msi_vec: the MSI which shall be generated by the peripheral after
0214  *  completing a completion descriptor in the message completion ring
0215  * @mtr_opt_header_size: the size of the optional header in the transfer
0216  *  descriptor associated with the message transfer ring in DWs
0217  * @mtr_opt_footer_size: the size of the optional footer in the transfer
0218  *  descriptor associated with the message transfer ring in DWs
0219  * @mcr_opt_header_size: the size of the optional header in the completion
0220  *  descriptor associated with the message completion ring in DWs
0221  * @mcr_opt_footer_size: the size of the optional footer in the completion
0222  *  descriptor associated with the message completion ring in DWs
0223  * @msg_rings_ctrl_flags: message rings control flags
0224  * @prph_info_msi_vec: the MSI which shall be generated by the peripheral
0225  *  after updating the Peripheral Information structure
0226  * @prph_scratch_base_addr: the peripheral scratch structure start address
0227  * @prph_scratch_size: the size of the peripheral scratch structure in DWs
0228  * @reserved: reserved
0229  */
0230 struct iwl_context_info_gen3 {
0231     __le16 version;
0232     __le16 size;
0233     __le32 config;
0234     __le64 prph_info_base_addr;
0235     __le64 cr_head_idx_arr_base_addr;
0236     __le64 tr_tail_idx_arr_base_addr;
0237     __le64 cr_tail_idx_arr_base_addr;
0238     __le64 tr_head_idx_arr_base_addr;
0239     __le16 cr_idx_arr_size;
0240     __le16 tr_idx_arr_size;
0241     __le64 mtr_base_addr;
0242     __le64 mcr_base_addr;
0243     __le16 mtr_size;
0244     __le16 mcr_size;
0245     __le16 mtr_doorbell_vec;
0246     __le16 mcr_doorbell_vec;
0247     __le16 mtr_msi_vec;
0248     __le16 mcr_msi_vec;
0249     u8 mtr_opt_header_size;
0250     u8 mtr_opt_footer_size;
0251     u8 mcr_opt_header_size;
0252     u8 mcr_opt_footer_size;
0253     __le16 msg_rings_ctrl_flags;
0254     __le16 prph_info_msi_vec;
0255     __le64 prph_scratch_base_addr;
0256     __le32 prph_scratch_size;
0257     __le32 reserved;
0258 } __packed; /* IPC_CONTEXT_INFO_S */
0259
0260 int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
0261                  const struct fw_img *fw);
0262 void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans, bool alive);
0263
0264 int iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans,
0265                       const void *data, u32 len);
0266 int iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans *trans,
0267                           const void *data, u32 len);
0268
0269 #endif /* __iwl_context_info_file_gen3_h__ */