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0007 #ifndef __iwl_fw_file_h__
0008 #define __iwl_fw_file_h__
0009
0010 #include <linux/netdevice.h>
0011 #include <linux/nl80211.h>
0012
0013
0014 struct iwl_ucode_header {
0015 __le32 ver;
0016 union {
0017 struct {
0018 __le32 inst_size;
0019 __le32 data_size;
0020 __le32 init_size;
0021 __le32 init_data_size;
0022 __le32 boot_size;
0023 u8 data[0];
0024 } v1;
0025 struct {
0026 __le32 build;
0027 __le32 inst_size;
0028 __le32 data_size;
0029 __le32 init_size;
0030 __le32 init_data_size;
0031 __le32 boot_size;
0032 u8 data[0];
0033 } v2;
0034 } u;
0035 };
0036
0037 #define IWL_UCODE_TLV_DEBUG_BASE 0x1000005
0038 #define IWL_UCODE_TLV_CONST_BASE 0x100
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0045
0046
0047 enum iwl_ucode_tlv_type {
0048 IWL_UCODE_TLV_INVALID = 0,
0049 IWL_UCODE_TLV_INST = 1,
0050 IWL_UCODE_TLV_DATA = 2,
0051 IWL_UCODE_TLV_INIT = 3,
0052 IWL_UCODE_TLV_INIT_DATA = 4,
0053 IWL_UCODE_TLV_BOOT = 5,
0054 IWL_UCODE_TLV_PROBE_MAX_LEN = 6,
0055 IWL_UCODE_TLV_PAN = 7,
0056 IWL_UCODE_TLV_MEM_DESC = 7,
0057 IWL_UCODE_TLV_RUNT_EVTLOG_PTR = 8,
0058 IWL_UCODE_TLV_RUNT_EVTLOG_SIZE = 9,
0059 IWL_UCODE_TLV_RUNT_ERRLOG_PTR = 10,
0060 IWL_UCODE_TLV_INIT_EVTLOG_PTR = 11,
0061 IWL_UCODE_TLV_INIT_EVTLOG_SIZE = 12,
0062 IWL_UCODE_TLV_INIT_ERRLOG_PTR = 13,
0063 IWL_UCODE_TLV_ENHANCE_SENS_TBL = 14,
0064 IWL_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
0065 IWL_UCODE_TLV_WOWLAN_INST = 16,
0066 IWL_UCODE_TLV_WOWLAN_DATA = 17,
0067 IWL_UCODE_TLV_FLAGS = 18,
0068 IWL_UCODE_TLV_SEC_RT = 19,
0069 IWL_UCODE_TLV_SEC_INIT = 20,
0070 IWL_UCODE_TLV_SEC_WOWLAN = 21,
0071 IWL_UCODE_TLV_DEF_CALIB = 22,
0072 IWL_UCODE_TLV_PHY_SKU = 23,
0073 IWL_UCODE_TLV_SECURE_SEC_RT = 24,
0074 IWL_UCODE_TLV_SECURE_SEC_INIT = 25,
0075 IWL_UCODE_TLV_SECURE_SEC_WOWLAN = 26,
0076 IWL_UCODE_TLV_NUM_OF_CPU = 27,
0077 IWL_UCODE_TLV_CSCHEME = 28,
0078 IWL_UCODE_TLV_API_CHANGES_SET = 29,
0079 IWL_UCODE_TLV_ENABLED_CAPABILITIES = 30,
0080 IWL_UCODE_TLV_N_SCAN_CHANNELS = 31,
0081 IWL_UCODE_TLV_PAGING = 32,
0082 IWL_UCODE_TLV_SEC_RT_USNIFFER = 34,
0083
0084 IWL_UCODE_TLV_FW_VERSION = 36,
0085 IWL_UCODE_TLV_FW_DBG_DEST = 38,
0086 IWL_UCODE_TLV_FW_DBG_CONF = 39,
0087 IWL_UCODE_TLV_FW_DBG_TRIGGER = 40,
0088 IWL_UCODE_TLV_CMD_VERSIONS = 48,
0089 IWL_UCODE_TLV_FW_GSCAN_CAPA = 50,
0090 IWL_UCODE_TLV_FW_MEM_SEG = 51,
0091 IWL_UCODE_TLV_IML = 52,
0092 IWL_UCODE_TLV_UMAC_DEBUG_ADDRS = 54,
0093 IWL_UCODE_TLV_LMAC_DEBUG_ADDRS = 55,
0094 IWL_UCODE_TLV_FW_RECOVERY_INFO = 57,
0095 IWL_UCODE_TLV_HW_TYPE = 58,
0096 IWL_UCODE_TLV_FW_FSEQ_VERSION = 60,
0097 IWL_UCODE_TLV_PHY_INTEGRATION_VERSION = 61,
0098
0099 IWL_UCODE_TLV_PNVM_VERSION = 62,
0100 IWL_UCODE_TLV_PNVM_SKU = 64,
0101
0102 IWL_UCODE_TLV_SEC_TABLE_ADDR = 66,
0103 IWL_UCODE_TLV_D3_KEK_KCK_ADDR = 67,
0104
0105 IWL_UCODE_TLV_FW_NUM_STATIONS = IWL_UCODE_TLV_CONST_BASE + 0,
0106
0107 IWL_UCODE_TLV_TYPE_DEBUG_INFO = IWL_UCODE_TLV_DEBUG_BASE + 0,
0108 IWL_UCODE_TLV_TYPE_BUFFER_ALLOCATION = IWL_UCODE_TLV_DEBUG_BASE + 1,
0109 IWL_UCODE_TLV_TYPE_HCMD = IWL_UCODE_TLV_DEBUG_BASE + 2,
0110 IWL_UCODE_TLV_TYPE_REGIONS = IWL_UCODE_TLV_DEBUG_BASE + 3,
0111 IWL_UCODE_TLV_TYPE_TRIGGERS = IWL_UCODE_TLV_DEBUG_BASE + 4,
0112 IWL_UCODE_TLV_TYPE_CONF_SET = IWL_UCODE_TLV_DEBUG_BASE + 5,
0113 IWL_UCODE_TLV_DEBUG_MAX = IWL_UCODE_TLV_TYPE_TRIGGERS,
0114
0115
0116 IWL_UCODE_TLV_FW_DBG_DUMP_LST = 0x1000,
0117 };
0118
0119 struct iwl_ucode_tlv {
0120 __le32 type;
0121 __le32 length;
0122 u8 data[];
0123 };
0124
0125 #define IWL_TLV_UCODE_MAGIC 0x0a4c5749
0126 #define FW_VER_HUMAN_READABLE_SZ 64
0127
0128 struct iwl_tlv_ucode_header {
0129
0130
0131
0132
0133
0134
0135 __le32 zero;
0136 __le32 magic;
0137 u8 human_readable[FW_VER_HUMAN_READABLE_SZ];
0138
0139 __le32 ver;
0140 __le32 build;
0141 __le64 ignore;
0142
0143
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0146
0147
0148 u8 data[];
0149 };
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0155
0156 struct iwl_ucode_api {
0157 __le32 api_index;
0158 __le32 api_flags;
0159 } __packed;
0160
0161 struct iwl_ucode_capa {
0162 __le32 api_index;
0163 __le32 api_capa;
0164 } __packed;
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0186 enum iwl_ucode_tlv_flag {
0187 IWL_UCODE_TLV_FLAGS_PAN = BIT(0),
0188 IWL_UCODE_TLV_FLAGS_NEWSCAN = BIT(1),
0189 IWL_UCODE_TLV_FLAGS_MFP = BIT(2),
0190 IWL_UCODE_TLV_FLAGS_SHORT_BL = BIT(7),
0191 IWL_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = BIT(10),
0192 IWL_UCODE_TLV_FLAGS_NO_BASIC_SSID = BIT(12),
0193 IWL_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = BIT(15),
0194 IWL_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = BIT(16),
0195 IWL_UCODE_TLV_FLAGS_UAPSD_SUPPORT = BIT(24),
0196 IWL_UCODE_TLV_FLAGS_EBS_SUPPORT = BIT(25),
0197 IWL_UCODE_TLV_FLAGS_P2P_PS_UAPSD = BIT(26),
0198 };
0199
0200 typedef unsigned int __bitwise iwl_ucode_tlv_api_t;
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0247 enum iwl_ucode_tlv_api {
0248
0249 IWL_UCODE_TLV_API_FRAGMENTED_SCAN = (__force iwl_ucode_tlv_api_t)8,
0250 IWL_UCODE_TLV_API_WIFI_MCC_UPDATE = (__force iwl_ucode_tlv_api_t)9,
0251 IWL_UCODE_TLV_API_LQ_SS_PARAMS = (__force iwl_ucode_tlv_api_t)18,
0252 IWL_UCODE_TLV_API_NEW_VERSION = (__force iwl_ucode_tlv_api_t)20,
0253 IWL_UCODE_TLV_API_SCAN_TSF_REPORT = (__force iwl_ucode_tlv_api_t)28,
0254 IWL_UCODE_TLV_API_TKIP_MIC_KEYS = (__force iwl_ucode_tlv_api_t)29,
0255 IWL_UCODE_TLV_API_STA_TYPE = (__force iwl_ucode_tlv_api_t)30,
0256 IWL_UCODE_TLV_API_NAN2_VER2 = (__force iwl_ucode_tlv_api_t)31,
0257
0258 IWL_UCODE_TLV_API_ADAPTIVE_DWELL = (__force iwl_ucode_tlv_api_t)32,
0259 IWL_UCODE_TLV_API_OCE = (__force iwl_ucode_tlv_api_t)33,
0260 IWL_UCODE_TLV_API_NEW_BEACON_TEMPLATE = (__force iwl_ucode_tlv_api_t)34,
0261 IWL_UCODE_TLV_API_NEW_RX_STATS = (__force iwl_ucode_tlv_api_t)35,
0262 IWL_UCODE_TLV_API_WOWLAN_KEY_MATERIAL = (__force iwl_ucode_tlv_api_t)36,
0263 IWL_UCODE_TLV_API_QUOTA_LOW_LATENCY = (__force iwl_ucode_tlv_api_t)38,
0264 IWL_UCODE_TLV_API_DEPRECATE_TTAK = (__force iwl_ucode_tlv_api_t)41,
0265 IWL_UCODE_TLV_API_ADAPTIVE_DWELL_V2 = (__force iwl_ucode_tlv_api_t)42,
0266 IWL_UCODE_TLV_API_FRAG_EBS = (__force iwl_ucode_tlv_api_t)44,
0267 IWL_UCODE_TLV_API_REDUCE_TX_POWER = (__force iwl_ucode_tlv_api_t)45,
0268 IWL_UCODE_TLV_API_SHORT_BEACON_NOTIF = (__force iwl_ucode_tlv_api_t)46,
0269 IWL_UCODE_TLV_API_BEACON_FILTER_V4 = (__force iwl_ucode_tlv_api_t)47,
0270 IWL_UCODE_TLV_API_REGULATORY_NVM_INFO = (__force iwl_ucode_tlv_api_t)48,
0271 IWL_UCODE_TLV_API_FTM_NEW_RANGE_REQ = (__force iwl_ucode_tlv_api_t)49,
0272 IWL_UCODE_TLV_API_SCAN_OFFLOAD_CHANS = (__force iwl_ucode_tlv_api_t)50,
0273 IWL_UCODE_TLV_API_MBSSID_HE = (__force iwl_ucode_tlv_api_t)52,
0274 IWL_UCODE_TLV_API_WOWLAN_TCP_SYN_WAKE = (__force iwl_ucode_tlv_api_t)53,
0275 IWL_UCODE_TLV_API_FTM_RTT_ACCURACY = (__force iwl_ucode_tlv_api_t)54,
0276 IWL_UCODE_TLV_API_SAR_TABLE_VER = (__force iwl_ucode_tlv_api_t)55,
0277 IWL_UCODE_TLV_API_REDUCED_SCAN_CONFIG = (__force iwl_ucode_tlv_api_t)56,
0278 IWL_UCODE_TLV_API_ADWELL_HB_DEF_N_AP = (__force iwl_ucode_tlv_api_t)57,
0279 IWL_UCODE_TLV_API_SCAN_EXT_CHAN_VER = (__force iwl_ucode_tlv_api_t)58,
0280 IWL_UCODE_TLV_API_BAND_IN_RX_DATA = (__force iwl_ucode_tlv_api_t)59,
0281
0282
0283 #ifdef __CHECKER__
0284
0285 #define NUM_IWL_UCODE_TLV_API 128
0286 #else
0287 NUM_IWL_UCODE_TLV_API
0288 #endif
0289 };
0290
0291 typedef unsigned int __bitwise iwl_ucode_tlv_capa_t;
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0375 enum iwl_ucode_tlv_capa {
0376
0377 IWL_UCODE_TLV_CAPA_D0I3_SUPPORT = (__force iwl_ucode_tlv_capa_t)0,
0378 IWL_UCODE_TLV_CAPA_LAR_SUPPORT = (__force iwl_ucode_tlv_capa_t)1,
0379 IWL_UCODE_TLV_CAPA_UMAC_SCAN = (__force iwl_ucode_tlv_capa_t)2,
0380 IWL_UCODE_TLV_CAPA_BEAMFORMER = (__force iwl_ucode_tlv_capa_t)3,
0381 IWL_UCODE_TLV_CAPA_TDLS_SUPPORT = (__force iwl_ucode_tlv_capa_t)6,
0382 IWL_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = (__force iwl_ucode_tlv_capa_t)8,
0383 IWL_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = (__force iwl_ucode_tlv_capa_t)9,
0384 IWL_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = (__force iwl_ucode_tlv_capa_t)10,
0385 IWL_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = (__force iwl_ucode_tlv_capa_t)11,
0386 IWL_UCODE_TLV_CAPA_DQA_SUPPORT = (__force iwl_ucode_tlv_capa_t)12,
0387 IWL_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = (__force iwl_ucode_tlv_capa_t)13,
0388 IWL_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = (__force iwl_ucode_tlv_capa_t)17,
0389 IWL_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = (__force iwl_ucode_tlv_capa_t)18,
0390 IWL_UCODE_TLV_CAPA_CSUM_SUPPORT = (__force iwl_ucode_tlv_capa_t)21,
0391 IWL_UCODE_TLV_CAPA_RADIO_BEACON_STATS = (__force iwl_ucode_tlv_capa_t)22,
0392 IWL_UCODE_TLV_CAPA_P2P_SCM_UAPSD = (__force iwl_ucode_tlv_capa_t)26,
0393 IWL_UCODE_TLV_CAPA_BT_COEX_PLCR = (__force iwl_ucode_tlv_capa_t)28,
0394 IWL_UCODE_TLV_CAPA_LAR_MULTI_MCC = (__force iwl_ucode_tlv_capa_t)29,
0395 IWL_UCODE_TLV_CAPA_BT_COEX_RRC = (__force iwl_ucode_tlv_capa_t)30,
0396 IWL_UCODE_TLV_CAPA_GSCAN_SUPPORT = (__force iwl_ucode_tlv_capa_t)31,
0397
0398
0399 IWL_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT = (__force iwl_ucode_tlv_capa_t)37,
0400 IWL_UCODE_TLV_CAPA_STA_PM_NOTIF = (__force iwl_ucode_tlv_capa_t)38,
0401 IWL_UCODE_TLV_CAPA_BINDING_CDB_SUPPORT = (__force iwl_ucode_tlv_capa_t)39,
0402 IWL_UCODE_TLV_CAPA_CDB_SUPPORT = (__force iwl_ucode_tlv_capa_t)40,
0403 IWL_UCODE_TLV_CAPA_D0I3_END_FIRST = (__force iwl_ucode_tlv_capa_t)41,
0404 IWL_UCODE_TLV_CAPA_TLC_OFFLOAD = (__force iwl_ucode_tlv_capa_t)43,
0405 IWL_UCODE_TLV_CAPA_DYNAMIC_QUOTA = (__force iwl_ucode_tlv_capa_t)44,
0406 IWL_UCODE_TLV_CAPA_COEX_SCHEMA_2 = (__force iwl_ucode_tlv_capa_t)45,
0407 IWL_UCODE_TLV_CAPA_CHANNEL_SWITCH_CMD = (__force iwl_ucode_tlv_capa_t)46,
0408 IWL_UCODE_TLV_CAPA_FTM_CALIBRATED = (__force iwl_ucode_tlv_capa_t)47,
0409 IWL_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS = (__force iwl_ucode_tlv_capa_t)48,
0410 IWL_UCODE_TLV_CAPA_CS_MODIFY = (__force iwl_ucode_tlv_capa_t)49,
0411 IWL_UCODE_TLV_CAPA_SET_LTR_GEN2 = (__force iwl_ucode_tlv_capa_t)50,
0412 IWL_UCODE_TLV_CAPA_SET_PPAG = (__force iwl_ucode_tlv_capa_t)52,
0413 IWL_UCODE_TLV_CAPA_TAS_CFG = (__force iwl_ucode_tlv_capa_t)53,
0414 IWL_UCODE_TLV_CAPA_SESSION_PROT_CMD = (__force iwl_ucode_tlv_capa_t)54,
0415 IWL_UCODE_TLV_CAPA_PROTECTED_TWT = (__force iwl_ucode_tlv_capa_t)56,
0416 IWL_UCODE_TLV_CAPA_FW_RESET_HANDSHAKE = (__force iwl_ucode_tlv_capa_t)57,
0417 IWL_UCODE_TLV_CAPA_PASSIVE_6GHZ_SCAN = (__force iwl_ucode_tlv_capa_t)58,
0418 IWL_UCODE_TLV_CAPA_HIDDEN_6GHZ_SCAN = (__force iwl_ucode_tlv_capa_t)59,
0419 IWL_UCODE_TLV_CAPA_BROADCAST_TWT = (__force iwl_ucode_tlv_capa_t)60,
0420 IWL_UCODE_TLV_CAPA_COEX_HIGH_PRIO = (__force iwl_ucode_tlv_capa_t)61,
0421 IWL_UCODE_TLV_CAPA_RFIM_SUPPORT = (__force iwl_ucode_tlv_capa_t)62,
0422 IWL_UCODE_TLV_CAPA_BAID_ML_SUPPORT = (__force iwl_ucode_tlv_capa_t)63,
0423
0424
0425 IWL_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = (__force iwl_ucode_tlv_capa_t)64,
0426 IWL_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = (__force iwl_ucode_tlv_capa_t)65,
0427 IWL_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = (__force iwl_ucode_tlv_capa_t)67,
0428 IWL_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = (__force iwl_ucode_tlv_capa_t)68,
0429 IWL_UCODE_TLV_CAPA_CSA_AND_TBTT_OFFLOAD = (__force iwl_ucode_tlv_capa_t)70,
0430 IWL_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = (__force iwl_ucode_tlv_capa_t)71,
0431 IWL_UCODE_TLV_CAPA_BEACON_STORING = (__force iwl_ucode_tlv_capa_t)72,
0432 IWL_UCODE_TLV_CAPA_LAR_SUPPORT_V3 = (__force iwl_ucode_tlv_capa_t)73,
0433 IWL_UCODE_TLV_CAPA_CT_KILL_BY_FW = (__force iwl_ucode_tlv_capa_t)74,
0434 IWL_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = (__force iwl_ucode_tlv_capa_t)75,
0435 IWL_UCODE_TLV_CAPA_CTDP_SUPPORT = (__force iwl_ucode_tlv_capa_t)76,
0436 IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED = (__force iwl_ucode_tlv_capa_t)77,
0437 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = (__force iwl_ucode_tlv_capa_t)80,
0438 IWL_UCODE_TLV_CAPA_LQM_SUPPORT = (__force iwl_ucode_tlv_capa_t)81,
0439 IWL_UCODE_TLV_CAPA_TX_POWER_ACK = (__force iwl_ucode_tlv_capa_t)84,
0440 IWL_UCODE_TLV_CAPA_D3_DEBUG = (__force iwl_ucode_tlv_capa_t)87,
0441 IWL_UCODE_TLV_CAPA_LED_CMD_SUPPORT = (__force iwl_ucode_tlv_capa_t)88,
0442 IWL_UCODE_TLV_CAPA_MCC_UPDATE_11AX_SUPPORT = (__force iwl_ucode_tlv_capa_t)89,
0443 IWL_UCODE_TLV_CAPA_CSI_REPORTING = (__force iwl_ucode_tlv_capa_t)90,
0444 IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP = (__force iwl_ucode_tlv_capa_t)92,
0445 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP = (__force iwl_ucode_tlv_capa_t)93,
0446
0447
0448 IWL_UCODE_TLV_CAPA_MLME_OFFLOAD = (__force iwl_ucode_tlv_capa_t)96,
0449
0450
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0453 IWL_UCODE_TLV_CAPA_PSC_CHAN_SUPPORT = (__force iwl_ucode_tlv_capa_t)98,
0454
0455 IWL_UCODE_TLV_CAPA_BIGTK_SUPPORT = (__force iwl_ucode_tlv_capa_t)100,
0456 IWL_UCODE_TLV_CAPA_DRAM_FRAG_SUPPORT = (__force iwl_ucode_tlv_capa_t)104,
0457 IWL_UCODE_TLV_CAPA_DUMP_COMPLETE_SUPPORT = (__force iwl_ucode_tlv_capa_t)105,
0458
0459 #ifdef __CHECKER__
0460
0461 #define NUM_IWL_UCODE_TLV_CAPA 128
0462 #else
0463 NUM_IWL_UCODE_TLV_CAPA
0464 #endif
0465 };
0466
0467
0468 #define IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18
0469 #define IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19
0470 #define IWL_MAX_PHY_CALIBRATE_TBL_SIZE 253
0471
0472
0473 #define IWL_DEFAULT_MAX_PROBE_LENGTH 200
0474
0475
0476
0477
0478
0479 #define CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC
0480 #define PAGING_SEPARATOR_SECTION 0xAAAABBBB
0481
0482
0483 #define IWL_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24)
0484 #define IWL_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16)
0485 #define IWL_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8)
0486 #define IWL_UCODE_SERIAL(ver) ((ver) & 0x000000FF)
0487
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0495
0496 struct iwl_tlv_calib_ctrl {
0497 __le32 flow_trigger;
0498 __le32 event_trigger;
0499 } __packed;
0500
0501 enum iwl_fw_phy_cfg {
0502 FW_PHY_CFG_RADIO_TYPE_POS = 0,
0503 FW_PHY_CFG_RADIO_TYPE = 0x3 << FW_PHY_CFG_RADIO_TYPE_POS,
0504 FW_PHY_CFG_RADIO_STEP_POS = 2,
0505 FW_PHY_CFG_RADIO_STEP = 0x3 << FW_PHY_CFG_RADIO_STEP_POS,
0506 FW_PHY_CFG_RADIO_DASH_POS = 4,
0507 FW_PHY_CFG_RADIO_DASH = 0x3 << FW_PHY_CFG_RADIO_DASH_POS,
0508 FW_PHY_CFG_TX_CHAIN_POS = 16,
0509 FW_PHY_CFG_TX_CHAIN = 0xf << FW_PHY_CFG_TX_CHAIN_POS,
0510 FW_PHY_CFG_RX_CHAIN_POS = 20,
0511 FW_PHY_CFG_RX_CHAIN = 0xf << FW_PHY_CFG_RX_CHAIN_POS,
0512 FW_PHY_CFG_CHAIN_SAD_POS = 23,
0513 FW_PHY_CFG_CHAIN_SAD_ENABLED = 0x1 << FW_PHY_CFG_CHAIN_SAD_POS,
0514 FW_PHY_CFG_CHAIN_SAD_ANT_A = 0x2 << FW_PHY_CFG_CHAIN_SAD_POS,
0515 FW_PHY_CFG_CHAIN_SAD_ANT_B = 0x4 << FW_PHY_CFG_CHAIN_SAD_POS,
0516 FW_PHY_CFG_SHARED_CLK = BIT(31),
0517 };
0518
0519 enum iwl_fw_dbg_reg_operator {
0520 CSR_ASSIGN,
0521 CSR_SETBIT,
0522 CSR_CLEARBIT,
0523
0524 PRPH_ASSIGN,
0525 PRPH_SETBIT,
0526 PRPH_CLEARBIT,
0527
0528 INDIRECT_ASSIGN,
0529 INDIRECT_SETBIT,
0530 INDIRECT_CLEARBIT,
0531
0532 PRPH_BLOCKBIT,
0533 };
0534
0535
0536
0537
0538
0539
0540
0541
0542 struct iwl_fw_dbg_reg_op {
0543 u8 op;
0544 u8 reserved[3];
0545 __le32 addr;
0546 __le32 val;
0547 } __packed;
0548
0549
0550
0551
0552
0553
0554
0555
0556
0557 enum iwl_fw_dbg_monitor_mode {
0558 SMEM_MODE = 0,
0559 EXTERNAL_MODE = 1,
0560 MARBH_MODE = 2,
0561 MIPI_MODE = 3,
0562 };
0563
0564
0565
0566
0567
0568
0569
0570
0571
0572
0573 struct iwl_fw_dbg_mem_seg_tlv {
0574 __le32 data_type;
0575 __le32 ofs;
0576 __le32 len;
0577 } __packed;
0578
0579
0580
0581
0582
0583
0584
0585
0586
0587
0588
0589
0590
0591
0592
0593
0594
0595 struct iwl_fw_dbg_dest_tlv_v1 {
0596 u8 version;
0597 u8 monitor_mode;
0598 u8 size_power;
0599 u8 reserved;
0600 __le32 base_reg;
0601 __le32 end_reg;
0602 __le32 write_ptr_reg;
0603 __le32 wrap_count;
0604 u8 base_shift;
0605 u8 end_shift;
0606 struct iwl_fw_dbg_reg_op reg_ops[];
0607 } __packed;
0608
0609
0610 #define IWL_LDBG_M2S_BUF_SIZE_MSK 0x0fff0000
0611
0612 #define IWL_LDBG_M2S_BUF_BA_MSK 0x00000fff
0613
0614 #define IWL_M2S_UNIT_SIZE 0x100
0615
0616 struct iwl_fw_dbg_dest_tlv {
0617 u8 version;
0618 u8 monitor_mode;
0619 u8 size_power;
0620 u8 reserved;
0621 __le32 cfg_reg;
0622 __le32 write_ptr_reg;
0623 __le32 wrap_count;
0624 u8 base_shift;
0625 u8 size_shift;
0626 struct iwl_fw_dbg_reg_op reg_ops[];
0627 } __packed;
0628
0629 struct iwl_fw_dbg_conf_hcmd {
0630 u8 id;
0631 u8 reserved;
0632 __le16 len;
0633 u8 data[];
0634 } __packed;
0635
0636
0637
0638
0639
0640
0641
0642
0643
0644 enum iwl_fw_dbg_trigger_mode {
0645 IWL_FW_DBG_TRIGGER_START = BIT(0),
0646 IWL_FW_DBG_TRIGGER_STOP = BIT(1),
0647 IWL_FW_DBG_TRIGGER_MONITOR_ONLY = BIT(2),
0648 };
0649
0650
0651
0652
0653
0654 enum iwl_fw_dbg_trigger_flags {
0655 IWL_FW_DBG_FORCE_RESTART = BIT(0),
0656 };
0657
0658
0659
0660
0661
0662
0663
0664
0665
0666
0667
0668 enum iwl_fw_dbg_trigger_vif_type {
0669 IWL_FW_DBG_CONF_VIF_ANY = NL80211_IFTYPE_UNSPECIFIED,
0670 IWL_FW_DBG_CONF_VIF_IBSS = NL80211_IFTYPE_ADHOC,
0671 IWL_FW_DBG_CONF_VIF_STATION = NL80211_IFTYPE_STATION,
0672 IWL_FW_DBG_CONF_VIF_AP = NL80211_IFTYPE_AP,
0673 IWL_FW_DBG_CONF_VIF_P2P_CLIENT = NL80211_IFTYPE_P2P_CLIENT,
0674 IWL_FW_DBG_CONF_VIF_P2P_GO = NL80211_IFTYPE_P2P_GO,
0675 IWL_FW_DBG_CONF_VIF_P2P_DEVICE = NL80211_IFTYPE_P2P_DEVICE,
0676 };
0677
0678
0679
0680
0681
0682
0683
0684
0685
0686
0687
0688
0689
0690
0691
0692
0693
0694
0695
0696 struct iwl_fw_dbg_trigger_tlv {
0697 __le32 id;
0698 __le32 vif_type;
0699 __le32 stop_conf_ids;
0700 __le32 stop_delay;
0701 u8 mode;
0702 u8 start_conf_id;
0703 __le16 occurrences;
0704 __le16 trig_dis_ms;
0705 u8 flags;
0706 u8 reserved[5];
0707
0708 u8 data[];
0709 } __packed;
0710
0711 #define FW_DBG_START_FROM_ALIVE 0
0712 #define FW_DBG_CONF_MAX 32
0713 #define FW_DBG_INVALID 0xff
0714
0715
0716
0717
0718
0719
0720
0721
0722
0723
0724 struct iwl_fw_dbg_trigger_missed_bcon {
0725 __le32 stop_consec_missed_bcon;
0726 __le32 stop_consec_missed_bcon_since_rx;
0727 __le32 reserved2[2];
0728 __le32 start_consec_missed_bcon;
0729 __le32 start_consec_missed_bcon_since_rx;
0730 __le32 reserved1[2];
0731 } __packed;
0732
0733
0734
0735
0736
0737 struct iwl_fw_dbg_trigger_cmd {
0738 struct cmd {
0739 u8 cmd_id;
0740 u8 group_id;
0741 } __packed cmds[16];
0742 } __packed;
0743
0744
0745
0746
0747
0748
0749
0750
0751 struct iwl_fw_dbg_trigger_stats {
0752 __le32 stop_offset;
0753 __le32 stop_threshold;
0754 __le32 start_offset;
0755 __le32 start_threshold;
0756 } __packed;
0757
0758
0759
0760
0761
0762 struct iwl_fw_dbg_trigger_low_rssi {
0763 __le32 rssi;
0764 } __packed;
0765
0766
0767
0768
0769
0770
0771
0772
0773
0774
0775
0776
0777
0778
0779
0780
0781
0782
0783 struct iwl_fw_dbg_trigger_mlme {
0784 u8 stop_auth_denied;
0785 u8 stop_auth_timeout;
0786 u8 stop_rx_deauth;
0787 u8 stop_tx_deauth;
0788
0789 u8 stop_assoc_denied;
0790 u8 stop_assoc_timeout;
0791 u8 stop_connection_loss;
0792 u8 reserved;
0793
0794 u8 start_auth_denied;
0795 u8 start_auth_timeout;
0796 u8 start_rx_deauth;
0797 u8 start_tx_deauth;
0798
0799 u8 start_assoc_denied;
0800 u8 start_assoc_timeout;
0801 u8 start_connection_loss;
0802 u8 reserved2;
0803 } __packed;
0804
0805
0806
0807
0808
0809
0810
0811
0812
0813
0814
0815
0816 struct iwl_fw_dbg_trigger_txq_timer {
0817 __le32 command_queue;
0818 __le32 bss;
0819 __le32 softap;
0820 __le32 p2p_go;
0821 __le32 p2p_client;
0822 __le32 p2p_device;
0823 __le32 ibss;
0824 __le32 tdls;
0825 __le32 reserved[4];
0826 } __packed;
0827
0828
0829
0830
0831
0832
0833
0834
0835
0836 struct iwl_fw_dbg_trigger_time_event {
0837 struct {
0838 __le32 id;
0839 __le32 action_bitmap;
0840 __le32 status_bitmap;
0841 } __packed time_events[16];
0842 } __packed;
0843
0844
0845
0846
0847
0848
0849
0850
0851
0852
0853
0854
0855
0856
0857
0858
0859
0860
0861 struct iwl_fw_dbg_trigger_ba {
0862 __le16 rx_ba_start;
0863 __le16 rx_ba_stop;
0864 __le16 tx_ba_start;
0865 __le16 tx_ba_stop;
0866 __le16 rx_bar;
0867 __le16 tx_bar;
0868 __le16 frame_timeout;
0869 } __packed;
0870
0871
0872
0873
0874
0875
0876
0877 struct iwl_fw_dbg_trigger_tdls {
0878 u8 action_bitmap;
0879 u8 peer_mode;
0880 u8 peer[ETH_ALEN];
0881 u8 reserved[4];
0882 } __packed;
0883
0884
0885
0886
0887
0888
0889 struct iwl_fw_dbg_trigger_tx_status {
0890 struct tx_status {
0891 u8 status;
0892 u8 reserved[3];
0893 } __packed statuses[16];
0894 __le32 reserved[2];
0895 } __packed;
0896
0897
0898
0899
0900
0901
0902
0903
0904
0905
0906
0907
0908 struct iwl_fw_dbg_conf_tlv {
0909 u8 id;
0910 u8 usniffer;
0911 u8 reserved;
0912 u8 num_of_hcmds;
0913 struct iwl_fw_dbg_conf_hcmd hcmd;
0914 } __packed;
0915
0916 #define IWL_FW_CMD_VER_UNKNOWN 99
0917
0918
0919
0920
0921
0922
0923
0924
0925 struct iwl_fw_cmd_version {
0926 u8 cmd;
0927 u8 group;
0928 u8 cmd_ver;
0929 u8 notif_ver;
0930 } __packed;
0931
0932 struct iwl_fw_tcm_error_addr {
0933 __le32 addr;
0934 };
0935
0936 struct iwl_fw_dump_exclude {
0937 __le32 addr, size;
0938 };
0939
0940 static inline size_t _iwl_tlv_array_len(const struct iwl_ucode_tlv *tlv,
0941 size_t fixed_size, size_t var_size)
0942 {
0943 size_t var_len = le32_to_cpu(tlv->length) - fixed_size;
0944
0945 if (WARN_ON(var_len % var_size))
0946 return 0;
0947
0948 return var_len / var_size;
0949 }
0950
0951 #define iwl_tlv_array_len(_tlv_ptr, _struct_ptr, _memb) \
0952 _iwl_tlv_array_len((_tlv_ptr), sizeof(*(_struct_ptr)), \
0953 sizeof(_struct_ptr->_memb[0]))
0954
0955 #endif