fw/api/sf.h

0001 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
0002 /*
0003  * Copyright (C) 2012-2014 Intel Corporation
0004  * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
0005  * Copyright (C) 2016-2017 Intel Deutschland GmbH
0006  */
0007 #ifndef __iwl_fw_api_sf_h__
0008 #define __iwl_fw_api_sf_h__
0009
0010 /* Smart Fifo state */
0011 enum iwl_sf_state {
0012     SF_LONG_DELAY_ON = 0, /* should never be called by driver */
0013     SF_FULL_ON,
0014     SF_UNINIT,
0015     SF_INIT_OFF,
0016     SF_HW_NUM_STATES
0017 };
0018
0019 /* Smart Fifo possible scenario */
0020 enum iwl_sf_scenario {
0021     SF_SCENARIO_SINGLE_UNICAST,
0022     SF_SCENARIO_AGG_UNICAST,
0023     SF_SCENARIO_MULTICAST,
0024     SF_SCENARIO_BA_RESP,
0025     SF_SCENARIO_TX_RESP,
0026     SF_NUM_SCENARIO
0027 };
0028
0029 #define SF_TRANSIENT_STATES_NUMBER 2    /* SF_LONG_DELAY_ON and SF_FULL_ON */
0030 #define SF_NUM_TIMEOUT_TYPES 2      /* Aging timer and Idle timer */
0031
0032 /* smart FIFO default values */
0033 #define SF_W_MARK_SISO 6144
0034 #define SF_W_MARK_MIMO2 8192
0035 #define SF_W_MARK_MIMO3 6144
0036 #define SF_W_MARK_LEGACY 4096
0037 #define SF_W_MARK_SCAN 4096
0038
0039 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */
0040 #define SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160    /* 150 uSec  */
0041 #define SF_SINGLE_UNICAST_AGING_TIMER_DEF 400   /* 0.4 mSec */
0042 #define SF_AGG_UNICAST_IDLE_TIMER_DEF 160       /* 150 uSec */
0043 #define SF_AGG_UNICAST_AGING_TIMER_DEF 400      /* 0.4 mSec */
0044 #define SF_MCAST_IDLE_TIMER_DEF 160     /* 150 mSec */
0045 #define SF_MCAST_AGING_TIMER_DEF 400        /* 0.4 mSec */
0046 #define SF_BA_IDLE_TIMER_DEF 160            /* 150 uSec */
0047 #define SF_BA_AGING_TIMER_DEF 400           /* 0.4 mSec */
0048 #define SF_TX_RE_IDLE_TIMER_DEF 160         /* 150 uSec */
0049 #define SF_TX_RE_AGING_TIMER_DEF 400        /* 0.4 mSec */
0050
0051 /* SF Scenarios timers for BSS MAC configuration (aligned to 32 uSec) */
0052 #define SF_SINGLE_UNICAST_IDLE_TIMER 320    /* 300 uSec  */
0053 #define SF_SINGLE_UNICAST_AGING_TIMER 2016  /* 2 mSec */
0054 #define SF_AGG_UNICAST_IDLE_TIMER 320       /* 300 uSec */
0055 #define SF_AGG_UNICAST_AGING_TIMER 2016     /* 2 mSec */
0056 #define SF_MCAST_IDLE_TIMER 2016        /* 2 mSec */
0057 #define SF_MCAST_AGING_TIMER 10016      /* 10 mSec */
0058 #define SF_BA_IDLE_TIMER 320            /* 300 uSec */
0059 #define SF_BA_AGING_TIMER 2016          /* 2 mSec */
0060 #define SF_TX_RE_IDLE_TIMER 320         /* 300 uSec */
0061 #define SF_TX_RE_AGING_TIMER 2016       /* 2 mSec */
0062
0063 #define SF_LONG_DELAY_AGING_TIMER 1000000   /* 1 Sec */
0064
0065 #define SF_CFG_DUMMY_NOTIF_OFF  BIT(16)
0066
0067 /**
0068  * struct iwl_sf_cfg_cmd - Smart Fifo configuration command.
0069  * @state: smart fifo state, types listed in &enum iwl_sf_state.
0070  * @watermark: Minimum allowed available free space in RXF for transient state.
0071  * @long_delay_timeouts: aging and idle timer values for each scenario
0072  * in long delay state.
0073  * @full_on_timeouts: timer values for each scenario in full on state.
0074  */
0075 struct iwl_sf_cfg_cmd {
0076     __le32 state;
0077     __le32 watermark[SF_TRANSIENT_STATES_NUMBER];
0078     __le32 long_delay_timeouts[SF_NUM_SCENARIO][SF_NUM_TIMEOUT_TYPES];
0079     __le32 full_on_timeouts[SF_NUM_SCENARIO][SF_NUM_TIMEOUT_TYPES];
0080 } __packed; /* SF_CFG_API_S_VER_2 */
0081
0082 #endif /* __iwl_fw_api_sf_h__ */