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0001 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
0002 /*
0003  * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
0004  * Copyright (C) 2017 Intel Deutschland GmbH
0005  */
0006 #ifndef __iwl_fw_api_rs_h__
0007 #define __iwl_fw_api_rs_h__
0008 
0009 #include "mac.h"
0010 
0011 /**
0012  * enum iwl_tlc_mng_cfg_flags_enum - options for TLC config flags
0013  * @IWL_TLC_MNG_CFG_FLAGS_STBC_MSK: enable STBC. For HE this enables STBC for
0014  *                  bandwidths <= 80MHz
0015  * @IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK: enable LDPC
0016  * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
0017  *                        bandwidth
0018  * @IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK: enable HE Dual Carrier Modulation
0019  *                      for BPSK (MCS 0) with 1 spatial
0020  *                      stream
0021  * @IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK: enable HE Dual Carrier Modulation
0022  *                      for BPSK (MCS 0) with 2 spatial
0023  *                      streams
0024  */
0025 enum iwl_tlc_mng_cfg_flags {
0026     IWL_TLC_MNG_CFG_FLAGS_STBC_MSK          = BIT(0),
0027     IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK          = BIT(1),
0028     IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK    = BIT(2),
0029     IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK      = BIT(3),
0030     IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK      = BIT(4),
0031 };
0032 
0033 /**
0034  * enum iwl_tlc_mng_cfg_cw - channel width options
0035  * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
0036  * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
0037  * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
0038  * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
0039  * @IWL_TLC_MNG_CH_WIDTH_LAST: maximum value
0040  */
0041 enum iwl_tlc_mng_cfg_cw {
0042     IWL_TLC_MNG_CH_WIDTH_20MHZ,
0043     IWL_TLC_MNG_CH_WIDTH_40MHZ,
0044     IWL_TLC_MNG_CH_WIDTH_80MHZ,
0045     IWL_TLC_MNG_CH_WIDTH_160MHZ,
0046     IWL_TLC_MNG_CH_WIDTH_LAST = IWL_TLC_MNG_CH_WIDTH_160MHZ,
0047 };
0048 
0049 /**
0050  * enum iwl_tlc_mng_cfg_chains - possible chains
0051  * @IWL_TLC_MNG_CHAIN_A_MSK: chain A
0052  * @IWL_TLC_MNG_CHAIN_B_MSK: chain B
0053  */
0054 enum iwl_tlc_mng_cfg_chains {
0055     IWL_TLC_MNG_CHAIN_A_MSK = BIT(0),
0056     IWL_TLC_MNG_CHAIN_B_MSK = BIT(1),
0057 };
0058 
0059 /**
0060  * enum iwl_tlc_mng_cfg_mode - supported modes
0061  * @IWL_TLC_MNG_MODE_CCK: enable CCK
0062  * @IWL_TLC_MNG_MODE_OFDM_NON_HT: enable OFDM (non HT)
0063  * @IWL_TLC_MNG_MODE_NON_HT: enable non HT
0064  * @IWL_TLC_MNG_MODE_HT: enable HT
0065  * @IWL_TLC_MNG_MODE_VHT: enable VHT
0066  * @IWL_TLC_MNG_MODE_HE: enable HE
0067  * @IWL_TLC_MNG_MODE_INVALID: invalid value
0068  * @IWL_TLC_MNG_MODE_NUM: a count of possible modes
0069  */
0070 enum iwl_tlc_mng_cfg_mode {
0071     IWL_TLC_MNG_MODE_CCK = 0,
0072     IWL_TLC_MNG_MODE_OFDM_NON_HT = IWL_TLC_MNG_MODE_CCK,
0073     IWL_TLC_MNG_MODE_NON_HT = IWL_TLC_MNG_MODE_CCK,
0074     IWL_TLC_MNG_MODE_HT,
0075     IWL_TLC_MNG_MODE_VHT,
0076     IWL_TLC_MNG_MODE_HE,
0077     IWL_TLC_MNG_MODE_INVALID,
0078     IWL_TLC_MNG_MODE_NUM = IWL_TLC_MNG_MODE_INVALID,
0079 };
0080 
0081 /**
0082  * enum iwl_tlc_mng_ht_rates - HT/VHT/HE rates
0083  * @IWL_TLC_MNG_HT_RATE_MCS0: index of MCS0
0084  * @IWL_TLC_MNG_HT_RATE_MCS1: index of MCS1
0085  * @IWL_TLC_MNG_HT_RATE_MCS2: index of MCS2
0086  * @IWL_TLC_MNG_HT_RATE_MCS3: index of MCS3
0087  * @IWL_TLC_MNG_HT_RATE_MCS4: index of MCS4
0088  * @IWL_TLC_MNG_HT_RATE_MCS5: index of MCS5
0089  * @IWL_TLC_MNG_HT_RATE_MCS6: index of MCS6
0090  * @IWL_TLC_MNG_HT_RATE_MCS7: index of MCS7
0091  * @IWL_TLC_MNG_HT_RATE_MCS8: index of MCS8
0092  * @IWL_TLC_MNG_HT_RATE_MCS9: index of MCS9
0093  * @IWL_TLC_MNG_HT_RATE_MCS10: index of MCS10
0094  * @IWL_TLC_MNG_HT_RATE_MCS11: index of MCS11
0095  * @IWL_TLC_MNG_HT_RATE_MAX: maximal rate for HT/VHT
0096  */
0097 enum iwl_tlc_mng_ht_rates {
0098     IWL_TLC_MNG_HT_RATE_MCS0 = 0,
0099     IWL_TLC_MNG_HT_RATE_MCS1,
0100     IWL_TLC_MNG_HT_RATE_MCS2,
0101     IWL_TLC_MNG_HT_RATE_MCS3,
0102     IWL_TLC_MNG_HT_RATE_MCS4,
0103     IWL_TLC_MNG_HT_RATE_MCS5,
0104     IWL_TLC_MNG_HT_RATE_MCS6,
0105     IWL_TLC_MNG_HT_RATE_MCS7,
0106     IWL_TLC_MNG_HT_RATE_MCS8,
0107     IWL_TLC_MNG_HT_RATE_MCS9,
0108     IWL_TLC_MNG_HT_RATE_MCS10,
0109     IWL_TLC_MNG_HT_RATE_MCS11,
0110     IWL_TLC_MNG_HT_RATE_MAX = IWL_TLC_MNG_HT_RATE_MCS11,
0111 };
0112 
0113 enum IWL_TLC_MNG_NSS {
0114     IWL_TLC_NSS_1,
0115     IWL_TLC_NSS_2,
0116     IWL_TLC_NSS_MAX
0117 };
0118 
0119 /**
0120  * enum IWL_TLC_MCS_PER_BW - mcs index per BW
0121  * @IWL_TLC_MCS_PER_BW_80: mcs for bw - 20Hhz, 40Hhz, 80Hhz
0122  * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz
0123  * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz
0124  * @IWL_TLC_MCS_PER_BW_NUM_V3: number of entries up to version 3
0125  * @IWL_TLC_MCS_PER_BW_NUM_V4: number of entries from version 4
0126  */
0127 enum IWL_TLC_MCS_PER_BW {
0128     IWL_TLC_MCS_PER_BW_80,
0129     IWL_TLC_MCS_PER_BW_160,
0130     IWL_TLC_MCS_PER_BW_320,
0131     IWL_TLC_MCS_PER_BW_NUM_V3 = IWL_TLC_MCS_PER_BW_160 + 1,
0132     IWL_TLC_MCS_PER_BW_NUM_V4 = IWL_TLC_MCS_PER_BW_320 + 1,
0133 };
0134 
0135 /**
0136  * struct iwl_tlc_config_cmd_v3 - TLC configuration
0137  * @sta_id: station id
0138  * @reserved1: reserved
0139  * @max_ch_width: max supported channel width from @enum iwl_tlc_mng_cfg_cw
0140  * @mode: &enum iwl_tlc_mng_cfg_mode
0141  * @chains: bitmask of &enum iwl_tlc_mng_cfg_chains
0142  * @amsdu: TX amsdu is supported
0143  * @flags: bitmask of &enum iwl_tlc_mng_cfg_flags
0144  * @non_ht_rates: bitmap of supported legacy rates
0145  * @ht_rates: bitmap of &enum iwl_tlc_mng_ht_rates, per &enum IWL_TLC_MCS_PER_BW
0146  *        <nss, channel-width> pair (0 - 80mhz width and below, 1 - 160mhz).
0147  * @max_mpdu_len: max MPDU length, in bytes
0148  * @sgi_ch_width_supp: bitmap of SGI support per channel width
0149  *             use BIT(@enum iwl_tlc_mng_cfg_cw)
0150  * @reserved2: reserved
0151  * @max_tx_op: max TXOP in uSecs for all AC (BK, BE, VO, VI),
0152  *         set zero for no limit.
0153  */
0154 struct iwl_tlc_config_cmd_v3 {
0155     u8 sta_id;
0156     u8 reserved1[3];
0157     u8 max_ch_width;
0158     u8 mode;
0159     u8 chains;
0160     u8 amsdu;
0161     __le16 flags;
0162     __le16 non_ht_rates;
0163     __le16 ht_rates[IWL_TLC_NSS_MAX][IWL_TLC_MCS_PER_BW_NUM_V3];
0164     __le16 max_mpdu_len;
0165     u8 sgi_ch_width_supp;
0166     u8 reserved2;
0167     __le32 max_tx_op;
0168 } __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_3 */
0169 
0170 /**
0171  * struct iwl_tlc_config_cmd_v4 - TLC configuration
0172  * @sta_id: station id
0173  * @reserved1: reserved
0174  * @max_ch_width: max supported channel width from &enum iwl_tlc_mng_cfg_cw
0175  * @mode: &enum iwl_tlc_mng_cfg_mode
0176  * @chains: bitmask of &enum iwl_tlc_mng_cfg_chains
0177  * @sgi_ch_width_supp: bitmap of SGI support per channel width
0178  *             use BIT(&enum iwl_tlc_mng_cfg_cw)
0179  * @flags: bitmask of &enum iwl_tlc_mng_cfg_flags
0180  * @non_ht_rates: bitmap of supported legacy rates
0181  * @ht_rates: bitmap of &enum iwl_tlc_mng_ht_rates, per <nss, channel-width>
0182  *        pair (0 - 80mhz width and below, 1 - 160mhz, 2 - 320mhz).
0183  * @max_mpdu_len: max MPDU length, in bytes
0184  * @max_tx_op: max TXOP in uSecs for all AC (BK, BE, VO, VI),
0185  *         set zero for no limit.
0186  */
0187 struct iwl_tlc_config_cmd_v4 {
0188     u8 sta_id;
0189     u8 reserved1[3];
0190     u8 max_ch_width;
0191     u8 mode;
0192     u8 chains;
0193     u8 sgi_ch_width_supp;
0194     __le16 flags;
0195     __le16 non_ht_rates;
0196     __le16 ht_rates[IWL_TLC_NSS_MAX][IWL_TLC_MCS_PER_BW_NUM_V4];
0197     __le16 max_mpdu_len;
0198     __le16 max_tx_op;
0199 } __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_4 */
0200 
0201 /**
0202  * enum iwl_tlc_update_flags - updated fields
0203  * @IWL_TLC_NOTIF_FLAG_RATE: last initial rate update
0204  * @IWL_TLC_NOTIF_FLAG_AMSDU: umsdu parameters update
0205  */
0206 enum iwl_tlc_update_flags {
0207     IWL_TLC_NOTIF_FLAG_RATE  = BIT(0),
0208     IWL_TLC_NOTIF_FLAG_AMSDU = BIT(1),
0209 };
0210 
0211 /**
0212  * struct iwl_tlc_update_notif - TLC notification from FW
0213  * @sta_id: station id
0214  * @reserved: reserved
0215  * @flags: bitmap of notifications reported
0216  * @rate: current initial rate
0217  * @amsdu_size: Max AMSDU size, in bytes
0218  * @amsdu_enabled: bitmap for per-TID AMSDU enablement
0219  */
0220 struct iwl_tlc_update_notif {
0221     u8 sta_id;
0222     u8 reserved[3];
0223     __le32 flags;
0224     __le32 rate;
0225     __le32 amsdu_size;
0226     __le32 amsdu_enabled;
0227 } __packed; /* TLC_MNG_UPDATE_NTFY_API_S_VER_2 */
0228 
0229 
0230 #define IWL_MAX_MCS_DISPLAY_SIZE        12
0231 
0232 struct iwl_rate_mcs_info {
0233     char    mbps[IWL_MAX_MCS_DISPLAY_SIZE];
0234     char    mcs[IWL_MAX_MCS_DISPLAY_SIZE];
0235 };
0236 
0237 /*
0238  * These serve as indexes into
0239  * struct iwl_rate_info fw_rate_idx_to_plcp[IWL_RATE_COUNT];
0240  * TODO: avoid overlap between legacy and HT rates
0241  */
0242 enum {
0243     IWL_RATE_1M_INDEX = 0,
0244     IWL_FIRST_CCK_RATE = IWL_RATE_1M_INDEX,
0245     IWL_RATE_2M_INDEX,
0246     IWL_RATE_5M_INDEX,
0247     IWL_RATE_11M_INDEX,
0248     IWL_LAST_CCK_RATE = IWL_RATE_11M_INDEX,
0249     IWL_RATE_6M_INDEX,
0250     IWL_FIRST_OFDM_RATE = IWL_RATE_6M_INDEX,
0251     IWL_RATE_MCS_0_INDEX = IWL_RATE_6M_INDEX,
0252     IWL_FIRST_HT_RATE = IWL_RATE_MCS_0_INDEX,
0253     IWL_FIRST_VHT_RATE = IWL_RATE_MCS_0_INDEX,
0254     IWL_RATE_9M_INDEX,
0255     IWL_RATE_12M_INDEX,
0256     IWL_RATE_MCS_1_INDEX = IWL_RATE_12M_INDEX,
0257     IWL_RATE_18M_INDEX,
0258     IWL_RATE_MCS_2_INDEX = IWL_RATE_18M_INDEX,
0259     IWL_RATE_24M_INDEX,
0260     IWL_RATE_MCS_3_INDEX = IWL_RATE_24M_INDEX,
0261     IWL_RATE_36M_INDEX,
0262     IWL_RATE_MCS_4_INDEX = IWL_RATE_36M_INDEX,
0263     IWL_RATE_48M_INDEX,
0264     IWL_RATE_MCS_5_INDEX = IWL_RATE_48M_INDEX,
0265     IWL_RATE_54M_INDEX,
0266     IWL_RATE_MCS_6_INDEX = IWL_RATE_54M_INDEX,
0267     IWL_LAST_NON_HT_RATE = IWL_RATE_54M_INDEX,
0268     IWL_RATE_60M_INDEX,
0269     IWL_RATE_MCS_7_INDEX = IWL_RATE_60M_INDEX,
0270     IWL_LAST_HT_RATE = IWL_RATE_MCS_7_INDEX,
0271     IWL_RATE_MCS_8_INDEX,
0272     IWL_RATE_MCS_9_INDEX,
0273     IWL_LAST_VHT_RATE = IWL_RATE_MCS_9_INDEX,
0274     IWL_RATE_MCS_10_INDEX,
0275     IWL_RATE_MCS_11_INDEX,
0276     IWL_LAST_HE_RATE = IWL_RATE_MCS_11_INDEX,
0277     IWL_RATE_COUNT_LEGACY = IWL_LAST_NON_HT_RATE + 1,
0278     IWL_RATE_COUNT = IWL_LAST_HE_RATE + 1,
0279     IWL_RATE_INVM_INDEX = IWL_RATE_COUNT,
0280     IWL_RATE_INVALID = IWL_RATE_COUNT,
0281 };
0282 
0283 #define IWL_RATE_BIT_MSK(r) BIT(IWL_RATE_##r##M_INDEX)
0284 
0285 /* fw API values for legacy bit rates, both OFDM and CCK */
0286 enum {
0287     IWL_RATE_6M_PLCP  = 13,
0288     IWL_RATE_9M_PLCP  = 15,
0289     IWL_RATE_12M_PLCP = 5,
0290     IWL_RATE_18M_PLCP = 7,
0291     IWL_RATE_24M_PLCP = 9,
0292     IWL_RATE_36M_PLCP = 11,
0293     IWL_RATE_48M_PLCP = 1,
0294     IWL_RATE_54M_PLCP = 3,
0295     IWL_RATE_1M_PLCP  = 10,
0296     IWL_RATE_2M_PLCP  = 20,
0297     IWL_RATE_5M_PLCP  = 55,
0298     IWL_RATE_11M_PLCP = 110,
0299     IWL_RATE_INVM_PLCP = -1,
0300 };
0301 
0302 /*
0303  * rate_n_flags bit fields version 1
0304  *
0305  * The 32-bit value has different layouts in the low 8 bites depending on the
0306  * format. There are three formats, HT, VHT and legacy (11abg, with subformats
0307  * for CCK and OFDM).
0308  *
0309  * High-throughput (HT) rate format
0310  *  bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM)
0311  * Very High-throughput (VHT) rate format
0312  *  bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM)
0313  * Legacy OFDM rate format for bits 7:0
0314  *  bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM)
0315  * Legacy CCK rate format for bits 7:0:
0316  *  bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK)
0317  */
0318 
0319 /* Bit 8: (1) HT format, (0) legacy or VHT format */
0320 #define RATE_MCS_HT_POS 8
0321 #define RATE_MCS_HT_MSK_V1 BIT(RATE_MCS_HT_POS)
0322 
0323 /* Bit 9: (1) CCK, (0) OFDM.  HT (bit 8) must be "0" for this bit to be valid */
0324 #define RATE_MCS_CCK_POS_V1 9
0325 #define RATE_MCS_CCK_MSK_V1 BIT(RATE_MCS_CCK_POS_V1)
0326 
0327 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */
0328 #define RATE_MCS_VHT_POS_V1 26
0329 #define RATE_MCS_VHT_MSK_V1 BIT(RATE_MCS_VHT_POS_V1)
0330 
0331 
0332 /*
0333  * High-throughput (HT) rate format for bits 7:0
0334  *
0335  *  2-0:  MCS rate base
0336  *        0)   6 Mbps
0337  *        1)  12 Mbps
0338  *        2)  18 Mbps
0339  *        3)  24 Mbps
0340  *        4)  36 Mbps
0341  *        5)  48 Mbps
0342  *        6)  54 Mbps
0343  *        7)  60 Mbps
0344  *  4-3:  0)  Single stream (SISO)
0345  *        1)  Dual stream (MIMO)
0346  *        2)  Triple stream (MIMO)
0347  *    5:  Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data
0348  *  (bits 7-6 are zero)
0349  *
0350  * Together the low 5 bits work out to the MCS index because we don't
0351  * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two
0352  * streams and 16-23 have three streams. We could also support MCS 32
0353  * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.)
0354  */
0355 #define RATE_HT_MCS_RATE_CODE_MSK_V1    0x7
0356 #define RATE_HT_MCS_NSS_POS_V1          3
0357 #define RATE_HT_MCS_NSS_MSK_V1          (3 << RATE_HT_MCS_NSS_POS_V1)
0358 #define RATE_HT_MCS_MIMO2_MSK       BIT(RATE_HT_MCS_NSS_POS_V1)
0359 
0360 /* Bit 10: (1) Use Green Field preamble */
0361 #define RATE_HT_MCS_GF_POS      10
0362 #define RATE_HT_MCS_GF_MSK      (1 << RATE_HT_MCS_GF_POS)
0363 
0364 #define RATE_HT_MCS_INDEX_MSK_V1    0x3f
0365 
0366 /*
0367  * Very High-throughput (VHT) rate format for bits 7:0
0368  *
0369  *  3-0:  VHT MCS (0-9)
0370  *  5-4:  number of streams - 1:
0371  *        0)  Single stream (SISO)
0372  *        1)  Dual stream (MIMO)
0373  *        2)  Triple stream (MIMO)
0374  */
0375 
0376 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */
0377 #define RATE_VHT_MCS_RATE_CODE_MSK  0xf
0378 #define RATE_VHT_MCS_NSS_POS        4
0379 #define RATE_VHT_MCS_NSS_MSK        (3 << RATE_VHT_MCS_NSS_POS)
0380 #define RATE_VHT_MCS_MIMO2_MSK      BIT(RATE_VHT_MCS_NSS_POS)
0381 
0382 /*
0383  * Legacy OFDM rate format for bits 7:0
0384  *
0385  *  3-0:  0xD)   6 Mbps
0386  *        0xF)   9 Mbps
0387  *        0x5)  12 Mbps
0388  *        0x7)  18 Mbps
0389  *        0x9)  24 Mbps
0390  *        0xB)  36 Mbps
0391  *        0x1)  48 Mbps
0392  *        0x3)  54 Mbps
0393  * (bits 7-4 are 0)
0394  *
0395  * Legacy CCK rate format for bits 7:0:
0396  * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK):
0397  *
0398  *  6-0:   10)  1 Mbps
0399  *         20)  2 Mbps
0400  *         55)  5.5 Mbps
0401  *        110)  11 Mbps
0402  * (bit 7 is 0)
0403  */
0404 #define RATE_LEGACY_RATE_MSK_V1 0xff
0405 
0406 /* Bit 10 - OFDM HE */
0407 #define RATE_MCS_HE_POS_V1  10
0408 #define RATE_MCS_HE_MSK_V1  BIT(RATE_MCS_HE_POS_V1)
0409 
0410 /*
0411  * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz
0412  * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT
0413  */
0414 #define RATE_MCS_CHAN_WIDTH_POS     11
0415 #define RATE_MCS_CHAN_WIDTH_MSK_V1  (3 << RATE_MCS_CHAN_WIDTH_POS)
0416 
0417 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */
0418 #define RATE_MCS_SGI_POS_V1     13
0419 #define RATE_MCS_SGI_MSK_V1     BIT(RATE_MCS_SGI_POS_V1)
0420 
0421 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */
0422 #define RATE_MCS_ANT_POS        14
0423 #define RATE_MCS_ANT_A_MSK      (1 << RATE_MCS_ANT_POS)
0424 #define RATE_MCS_ANT_B_MSK      (2 << RATE_MCS_ANT_POS)
0425 #define RATE_MCS_ANT_AB_MSK     (RATE_MCS_ANT_A_MSK | \
0426                      RATE_MCS_ANT_B_MSK)
0427 #define RATE_MCS_ANT_MSK        RATE_MCS_ANT_AB_MSK
0428 
0429 /* Bit 17: (0) SS, (1) SS*2 */
0430 #define RATE_MCS_STBC_POS       17
0431 #define RATE_MCS_STBC_MSK       BIT(RATE_MCS_STBC_POS)
0432 
0433 /* Bit 18: OFDM-HE dual carrier mode */
0434 #define RATE_HE_DUAL_CARRIER_MODE   18
0435 #define RATE_HE_DUAL_CARRIER_MODE_MSK   BIT(RATE_HE_DUAL_CARRIER_MODE)
0436 
0437 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */
0438 #define RATE_MCS_BF_POS         19
0439 #define RATE_MCS_BF_MSK         (1 << RATE_MCS_BF_POS)
0440 
0441 /*
0442  * Bit 20-21: HE LTF type and guard interval
0443  * HE (ext) SU:
0444  *  0           1xLTF+0.8us
0445  *  1           2xLTF+0.8us
0446  *  2           2xLTF+1.6us
0447  *  3 & SGI (bit 13) clear  4xLTF+3.2us
0448  *  3 & SGI (bit 13) set    4xLTF+0.8us
0449  * HE MU:
0450  *  0           4xLTF+0.8us
0451  *  1           2xLTF+0.8us
0452  *  2           2xLTF+1.6us
0453  *  3           4xLTF+3.2us
0454  * HE TRIG:
0455  *  0           1xLTF+1.6us
0456  *  1           2xLTF+1.6us
0457  *  2           4xLTF+3.2us
0458  *  3           (does not occur)
0459  */
0460 #define RATE_MCS_HE_GI_LTF_POS      20
0461 #define RATE_MCS_HE_GI_LTF_MSK_V1       (3 << RATE_MCS_HE_GI_LTF_POS)
0462 
0463 /* Bit 22-23: HE type. (0) SU, (1) SU_EXT, (2) MU, (3) trigger based */
0464 #define RATE_MCS_HE_TYPE_POS_V1     22
0465 #define RATE_MCS_HE_TYPE_SU_V1      (0 << RATE_MCS_HE_TYPE_POS_V1)
0466 #define RATE_MCS_HE_TYPE_EXT_SU_V1      BIT(RATE_MCS_HE_TYPE_POS_V1)
0467 #define RATE_MCS_HE_TYPE_MU_V1      (2 << RATE_MCS_HE_TYPE_POS_V1)
0468 #define RATE_MCS_HE_TYPE_TRIG_V1    (3 << RATE_MCS_HE_TYPE_POS_V1)
0469 #define RATE_MCS_HE_TYPE_MSK_V1     (3 << RATE_MCS_HE_TYPE_POS_V1)
0470 
0471 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */
0472 #define RATE_MCS_DUP_POS_V1     24
0473 #define RATE_MCS_DUP_MSK_V1     (3 << RATE_MCS_DUP_POS_V1)
0474 
0475 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */
0476 #define RATE_MCS_LDPC_POS_V1        27
0477 #define RATE_MCS_LDPC_MSK_V1        BIT(RATE_MCS_LDPC_POS_V1)
0478 
0479 /* Bit 28: (1) 106-tone RX (8 MHz RU), (0) normal bandwidth */
0480 #define RATE_MCS_HE_106T_POS_V1     28
0481 #define RATE_MCS_HE_106T_MSK_V1     BIT(RATE_MCS_HE_106T_POS_V1)
0482 
0483 /* Bit 30-31: (1) RTS, (2) CTS */
0484 #define RATE_MCS_RTS_REQUIRED_POS  (30)
0485 #define RATE_MCS_RTS_REQUIRED_MSK  (0x1 << RATE_MCS_RTS_REQUIRED_POS)
0486 
0487 #define RATE_MCS_CTS_REQUIRED_POS  (31)
0488 #define RATE_MCS_CTS_REQUIRED_MSK  (0x1 << RATE_MCS_CTS_REQUIRED_POS)
0489 
0490 /* rate_n_flags bit field version 2
0491  *
0492  * The 32-bit value has different layouts in the low 8 bits depending on the
0493  * format. There are three formats, HT, VHT and legacy (11abg, with subformats
0494  * for CCK and OFDM).
0495  *
0496  */
0497 
0498 /* Bits 10-8: rate format
0499  * (0) Legacy CCK (1) Legacy OFDM (2) High-throughput (HT)
0500  * (3) Very High-throughput (VHT) (4) High-efficiency (HE)
0501  * (5) Extremely High-throughput (EHT)
0502  */
0503 #define RATE_MCS_MOD_TYPE_POS       8
0504 #define RATE_MCS_MOD_TYPE_MSK       (0x7 << RATE_MCS_MOD_TYPE_POS)
0505 #define RATE_MCS_CCK_MSK        (0 << RATE_MCS_MOD_TYPE_POS)
0506 #define RATE_MCS_LEGACY_OFDM_MSK    (1 << RATE_MCS_MOD_TYPE_POS)
0507 #define RATE_MCS_HT_MSK         (2 << RATE_MCS_MOD_TYPE_POS)
0508 #define RATE_MCS_VHT_MSK        (3 << RATE_MCS_MOD_TYPE_POS)
0509 #define RATE_MCS_HE_MSK         (4 << RATE_MCS_MOD_TYPE_POS)
0510 #define RATE_MCS_EHT_MSK        (5 << RATE_MCS_MOD_TYPE_POS)
0511 
0512 /*
0513  * Legacy CCK rate format for bits 0:3:
0514  *
0515  * (0) 0xa - 1 Mbps
0516  * (1) 0x14 - 2 Mbps
0517  * (2) 0x37 - 5.5 Mbps
0518  * (3) 0x6e - 11 nbps
0519  *
0520  * Legacy OFDM rate format for bis 3:0:
0521  *
0522  * (0) 6 Mbps
0523  * (1) 9 Mbps
0524  * (2) 12 Mbps
0525  * (3) 18 Mbps
0526  * (4) 24 Mbps
0527  * (5) 36 Mbps
0528  * (6) 48 Mbps
0529  * (7) 54 Mbps
0530  *
0531  */
0532 #define RATE_LEGACY_RATE_MSK        0x7
0533 
0534 /*
0535  * HT, VHT, HE, EHT rate format for bits 3:0
0536  * 3-0: MCS
0537  *
0538  */
0539 #define RATE_HT_MCS_CODE_MSK        0x7
0540 #define RATE_MCS_NSS_POS        4
0541 #define RATE_MCS_NSS_MSK        (1 << RATE_MCS_NSS_POS)
0542 #define RATE_MCS_CODE_MSK       0xf
0543 #define RATE_HT_MCS_INDEX(r)        ((((r) & RATE_MCS_NSS_MSK) >> 1) | \
0544                      ((r) & RATE_HT_MCS_CODE_MSK))
0545 
0546 /* Bits 7-5: reserved */
0547 
0548 /*
0549  * Bits 13-11: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz, (4) 320MHz
0550  */
0551 #define RATE_MCS_CHAN_WIDTH_MSK         (0x7 << RATE_MCS_CHAN_WIDTH_POS)
0552 #define RATE_MCS_CHAN_WIDTH_20          (0 << RATE_MCS_CHAN_WIDTH_POS)
0553 #define RATE_MCS_CHAN_WIDTH_40          (1 << RATE_MCS_CHAN_WIDTH_POS)
0554 #define RATE_MCS_CHAN_WIDTH_80          (2 << RATE_MCS_CHAN_WIDTH_POS)
0555 #define RATE_MCS_CHAN_WIDTH_160         (3 << RATE_MCS_CHAN_WIDTH_POS)
0556 #define RATE_MCS_CHAN_WIDTH_320         (4 << RATE_MCS_CHAN_WIDTH_POS)
0557 
0558 /* Bit 15-14: Antenna selection:
0559  * Bit 14: Ant A active
0560  * Bit 15: Ant B active
0561  *
0562  * All relevant definitions are same as in v1
0563  */
0564 
0565 /* Bit 16 (1) LDPC enables, (0) LDPC disabled */
0566 #define RATE_MCS_LDPC_POS   16
0567 #define RATE_MCS_LDPC_MSK   (1 << RATE_MCS_LDPC_POS)
0568 
0569 /* Bit 17: (0) SS, (1) SS*2 (same as v1) */
0570 
0571 /* Bit 18: OFDM-HE dual carrier mode (same as v1) */
0572 
0573 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on (same as v1) */
0574 
0575 /*
0576  * Bit 22-20: HE LTF type and guard interval
0577  * CCK:
0578  *  0           long preamble
0579  *  1           short preamble
0580  * HT/VHT:
0581  *  0           0.8us
0582  *  1           0.4us
0583  * HE (ext) SU:
0584  *  0           1xLTF+0.8us
0585  *  1           2xLTF+0.8us
0586  *  2           2xLTF+1.6us
0587  *  3           4xLTF+3.2us
0588  *  4           4xLTF+0.8us
0589  * HE MU:
0590  *  0           4xLTF+0.8us
0591  *  1           2xLTF+0.8us
0592  *  2           2xLTF+1.6us
0593  *  3           4xLTF+3.2us
0594  * HE TRIG:
0595  *  0           1xLTF+1.6us
0596  *  1           2xLTF+1.6us
0597  *  2           4xLTF+3.2us
0598  * */
0599 #define RATE_MCS_HE_GI_LTF_MSK      (0x7 << RATE_MCS_HE_GI_LTF_POS)
0600 #define RATE_MCS_SGI_POS        RATE_MCS_HE_GI_LTF_POS
0601 #define RATE_MCS_SGI_MSK        (1 << RATE_MCS_SGI_POS)
0602 #define RATE_MCS_HE_SU_4_LTF        3
0603 #define RATE_MCS_HE_SU_4_LTF_08_GI  4
0604 
0605 /* Bit 24-23: HE type. (0) SU, (1) SU_EXT, (2) MU, (3) trigger based */
0606 #define RATE_MCS_HE_TYPE_POS        23
0607 #define RATE_MCS_HE_TYPE_SU     (0 << RATE_MCS_HE_TYPE_POS)
0608 #define RATE_MCS_HE_TYPE_EXT_SU     (1 << RATE_MCS_HE_TYPE_POS)
0609 #define RATE_MCS_HE_TYPE_MU     (2 << RATE_MCS_HE_TYPE_POS)
0610 #define RATE_MCS_HE_TYPE_TRIG       (3 << RATE_MCS_HE_TYPE_POS)
0611 #define RATE_MCS_HE_TYPE_MSK        (3 << RATE_MCS_HE_TYPE_POS)
0612 
0613 /* Bit 25: duplicate channel enabled
0614  *
0615  * if this bit is set, duplicate is according to BW (bits 11-13):
0616  *
0617  * CCK:  2x 20MHz
0618  * OFDM Legacy: N x 20Mhz, (N = BW \ 2 , either 2, 4, 8, 16)
0619  * EHT: 2 x BW/2, (80 - 2x40, 160 - 2x80, 320 - 2x160)
0620  * */
0621 #define RATE_MCS_DUP_POS        25
0622 #define RATE_MCS_DUP_MSK        (1 << RATE_MCS_DUP_POS)
0623 
0624 /* Bit 26: (1) 106-tone RX (8 MHz RU), (0) normal bandwidth */
0625 #define RATE_MCS_HE_106T_POS        26
0626 #define RATE_MCS_HE_106T_MSK        (1 << RATE_MCS_HE_106T_POS)
0627 
0628 /* Bit 27: EHT extra LTF:
0629  * instead of 1 LTF for SISO use 2 LTFs,
0630  * instead of 2 LTFs for NSTS=2 use 4 LTFs*/
0631 #define RATE_MCS_EHT_EXTRA_LTF_POS  27
0632 #define RATE_MCS_EHT_EXTRA_LTF_MSK  (1 << RATE_MCS_EHT_EXTRA_LTF_POS)
0633 
0634 /* Bit 31-28: reserved */
0635 
0636 /* Link Quality definitions */
0637 
0638 /* # entries in rate scale table to support Tx retries */
0639 #define  LQ_MAX_RETRY_NUM 16
0640 
0641 /* Link quality command flags bit fields */
0642 
0643 /* Bit 0: (0) Don't use RTS (1) Use RTS */
0644 #define LQ_FLAG_USE_RTS_POS             0
0645 #define LQ_FLAG_USE_RTS_MSK         (1 << LQ_FLAG_USE_RTS_POS)
0646 
0647 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */
0648 #define LQ_FLAG_COLOR_POS               1
0649 #define LQ_FLAG_COLOR_MSK               (7 << LQ_FLAG_COLOR_POS)
0650 #define LQ_FLAG_COLOR_GET(_f)       (((_f) & LQ_FLAG_COLOR_MSK) >>\
0651                      LQ_FLAG_COLOR_POS)
0652 #define LQ_FLAGS_COLOR_INC(_c)      ((((_c) + 1) << LQ_FLAG_COLOR_POS) &\
0653                      LQ_FLAG_COLOR_MSK)
0654 #define LQ_FLAG_COLOR_SET(_f, _c)   ((_c) | ((_f) & ~LQ_FLAG_COLOR_MSK))
0655 
0656 /* Bit 4-5: Tx RTS BW Signalling
0657  * (0) No RTS BW signalling
0658  * (1) Static BW signalling
0659  * (2) Dynamic BW signalling
0660  */
0661 #define LQ_FLAG_RTS_BW_SIG_POS          4
0662 #define LQ_FLAG_RTS_BW_SIG_NONE         (0 << LQ_FLAG_RTS_BW_SIG_POS)
0663 #define LQ_FLAG_RTS_BW_SIG_STATIC       (1 << LQ_FLAG_RTS_BW_SIG_POS)
0664 #define LQ_FLAG_RTS_BW_SIG_DYNAMIC      (2 << LQ_FLAG_RTS_BW_SIG_POS)
0665 
0666 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection
0667  * Dyanmic BW selection allows Tx with narrower BW then requested in rates
0668  */
0669 #define LQ_FLAG_DYNAMIC_BW_POS          6
0670 #define LQ_FLAG_DYNAMIC_BW_MSK          (1 << LQ_FLAG_DYNAMIC_BW_POS)
0671 
0672 /* Single Stream Tx Parameters (lq_cmd->ss_params)
0673  * Flags to control a smart FW decision about whether BFER/STBC/SISO will be
0674  * used for single stream Tx.
0675  */
0676 
0677 /* Bit 0-1: Max STBC streams allowed. Can be 0-3.
0678  * (0) - No STBC allowed
0679  * (1) - 2x1 STBC allowed (HT/VHT)
0680  * (2) - 4x2 STBC allowed (HT/VHT)
0681  * (3) - 3x2 STBC allowed (HT only)
0682  * All our chips are at most 2 antennas so only (1) is valid for now.
0683  */
0684 #define LQ_SS_STBC_ALLOWED_POS          0
0685 #define LQ_SS_STBC_ALLOWED_MSK      (3 << LQ_SS_STBC_ALLOWED_MSK)
0686 
0687 /* 2x1 STBC is allowed */
0688 #define LQ_SS_STBC_1SS_ALLOWED      (1 << LQ_SS_STBC_ALLOWED_POS)
0689 
0690 /* Bit 2: Beamformer (VHT only) is allowed */
0691 #define LQ_SS_BFER_ALLOWED_POS      2
0692 #define LQ_SS_BFER_ALLOWED      (1 << LQ_SS_BFER_ALLOWED_POS)
0693 
0694 /* Bit 3: Force BFER or STBC for testing
0695  * If this is set:
0696  * If BFER is allowed then force the ucode to choose BFER else
0697  * If STBC is allowed then force the ucode to choose STBC over SISO
0698  */
0699 #define LQ_SS_FORCE_POS         3
0700 #define LQ_SS_FORCE         (1 << LQ_SS_FORCE_POS)
0701 
0702 /* Bit 31: ss_params field is valid. Used for FW backward compatibility
0703  * with other drivers which don't support the ss_params API yet
0704  */
0705 #define LQ_SS_PARAMS_VALID_POS      31
0706 #define LQ_SS_PARAMS_VALID      (1 << LQ_SS_PARAMS_VALID_POS)
0707 
0708 /**
0709  * struct iwl_lq_cmd - link quality command
0710  * @sta_id: station to update
0711  * @reduced_tpc: reduced transmit power control value
0712  * @control: not used
0713  * @flags: combination of LQ_FLAG_*
0714  * @mimo_delim: the first SISO index in rs_table, which separates MIMO
0715  *  and SISO rates
0716  * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD).
0717  *  Should be ANT_[ABC]
0718  * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC]
0719  * @initial_rate_index: first index from rs_table per AC category
0720  * @agg_time_limit: aggregation max time threshold in usec/100, meaning
0721  *  value of 100 is one usec. Range is 100 to 8000
0722  * @agg_disable_start_th: try-count threshold for starting aggregation.
0723  *  If a frame has higher try-count, it should not be selected for
0724  *  starting an aggregation sequence.
0725  * @agg_frame_cnt_limit: max frame count in an aggregation.
0726  *  0: no limit
0727  *  1: no aggregation (one frame per aggregation)
0728  *  2 - 0x3f: maximal number of frames (up to 3f == 63)
0729  * @reserved2: reserved
0730  * @rs_table: array of rates for each TX try, each is rate_n_flags,
0731  *  meaning it is a combination of RATE_MCS_* and IWL_RATE_*_PLCP
0732  * @ss_params: single stream features. declare whether STBC or BFER are allowed.
0733  */
0734 struct iwl_lq_cmd {
0735     u8 sta_id;
0736     u8 reduced_tpc;
0737     __le16 control;
0738     /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */
0739     u8 flags;
0740     u8 mimo_delim;
0741     u8 single_stream_ant_msk;
0742     u8 dual_stream_ant_msk;
0743     u8 initial_rate_index[AC_NUM];
0744     /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */
0745     __le16 agg_time_limit;
0746     u8 agg_disable_start_th;
0747     u8 agg_frame_cnt_limit;
0748     __le32 reserved2;
0749     __le32 rs_table[LQ_MAX_RETRY_NUM];
0750     __le32 ss_params;
0751 }; /* LINK_QUALITY_CMD_API_S_VER_1 */
0752 
0753 u8 iwl_fw_rate_idx_to_plcp(int idx);
0754 u32 iwl_new_rate_from_v1(u32 rate_v1);
0755 const struct iwl_rate_mcs_info *iwl_rate_mcs(int idx);
0756 const char *iwl_rs_pretty_ant(u8 ant);
0757 const char *iwl_rs_pretty_bw(int bw);
0758 int rs_pretty_print_rate(char *buf, int bufsz, const u32 rate);
0759 bool iwl_he_is_sgi(u32 rate_n_flags);
0760 
0761 #endif /* __iwl_fw_api_rs_h__ */
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