fw/api/phy-ctxt.h

0001 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
0002 /*
0003  * Copyright (C) 2012-2014, 2018, 2020-2021 Intel Corporation
0004  * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
0005  * Copyright (C) 2016-2017 Intel Deutschland GmbH
0006  */
0007 #ifndef __iwl_fw_api_phy_ctxt_h__
0008 #define __iwl_fw_api_phy_ctxt_h__
0009
0010 /* Supported bands */
0011 #define PHY_BAND_5  (0)
0012 #define PHY_BAND_24 (1)
0013 #define PHY_BAND_6 (2)
0014
0015 /* Supported channel width, vary if there is VHT support */
0016 #define PHY_VHT_CHANNEL_MODE20  (0x0)
0017 #define PHY_VHT_CHANNEL_MODE40  (0x1)
0018 #define PHY_VHT_CHANNEL_MODE80  (0x2)
0019 #define PHY_VHT_CHANNEL_MODE160 (0x3)
0020
0021 /*
0022  * Control channel position:
0023  * For legacy set bit means upper channel, otherwise lower.
0024  * For VHT - bit-2 marks if the control is lower/upper relative to center-freq
0025  *   bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
0026  *                                   center_freq
0027  *                                        |
0028  * 40Mhz                          |_______|_______|
0029  * 80Mhz                  |_______|_______|_______|_______|
0030  * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______|
0031  * code      011     010     001     000  |  100     101     110    111
0032  */
0033 #define PHY_VHT_CTRL_POS_1_BELOW  (0x0)
0034 #define PHY_VHT_CTRL_POS_2_BELOW  (0x1)
0035 #define PHY_VHT_CTRL_POS_3_BELOW  (0x2)
0036 #define PHY_VHT_CTRL_POS_4_BELOW  (0x3)
0037 #define PHY_VHT_CTRL_POS_1_ABOVE  (0x4)
0038 #define PHY_VHT_CTRL_POS_2_ABOVE  (0x5)
0039 #define PHY_VHT_CTRL_POS_3_ABOVE  (0x6)
0040 #define PHY_VHT_CTRL_POS_4_ABOVE  (0x7)
0041
0042 /*
0043  * struct iwl_fw_channel_info_v1 - channel information
0044  *
0045  * @band: PHY_BAND_*
0046  * @channel: channel number
0047  * @width: PHY_[VHT|LEGACY]_CHANNEL_*
0048  * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
0049  */
0050 struct iwl_fw_channel_info_v1 {
0051     u8 band;
0052     u8 channel;
0053     u8 width;
0054     u8 ctrl_pos;
0055 } __packed; /* CHANNEL_CONFIG_API_S_VER_1 */
0056
0057 /*
0058  * struct iwl_fw_channel_info - channel information
0059  *
0060  * @channel: channel number
0061  * @band: PHY_BAND_*
0062  * @width: PHY_[VHT|LEGACY]_CHANNEL_*
0063  * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
0064  * @reserved: for future use and alignment
0065  */
0066 struct iwl_fw_channel_info {
0067     __le32 channel;
0068     u8 band;
0069     u8 width;
0070     u8 ctrl_pos;
0071     u8 reserved;
0072 } __packed; /*CHANNEL_CONFIG_API_S_VER_2 */
0073
0074 #define PHY_RX_CHAIN_DRIVER_FORCE_POS   (0)
0075 #define PHY_RX_CHAIN_DRIVER_FORCE_MSK \
0076     (0x1 << PHY_RX_CHAIN_DRIVER_FORCE_POS)
0077 #define PHY_RX_CHAIN_VALID_POS      (1)
0078 #define PHY_RX_CHAIN_VALID_MSK \
0079     (0x7 << PHY_RX_CHAIN_VALID_POS)
0080 #define PHY_RX_CHAIN_FORCE_SEL_POS  (4)
0081 #define PHY_RX_CHAIN_FORCE_SEL_MSK \
0082     (0x7 << PHY_RX_CHAIN_FORCE_SEL_POS)
0083 #define PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
0084 #define PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \
0085     (0x7 << PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)
0086 #define PHY_RX_CHAIN_CNT_POS        (10)
0087 #define PHY_RX_CHAIN_CNT_MSK \
0088     (0x3 << PHY_RX_CHAIN_CNT_POS)
0089 #define PHY_RX_CHAIN_MIMO_CNT_POS   (12)
0090 #define PHY_RX_CHAIN_MIMO_CNT_MSK \
0091     (0x3 << PHY_RX_CHAIN_MIMO_CNT_POS)
0092 #define PHY_RX_CHAIN_MIMO_FORCE_POS (14)
0093 #define PHY_RX_CHAIN_MIMO_FORCE_MSK \
0094     (0x1 << PHY_RX_CHAIN_MIMO_FORCE_POS)
0095
0096 /* TODO: fix the value, make it depend on firmware at runtime? */
0097 #define NUM_PHY_CTX 3
0098
0099 /* TODO: complete missing documentation */
0100 /**
0101  * struct iwl_phy_context_cmd_tail - tail of iwl_phy_ctx_cmd for alignment with
0102  *  various channel structures.
0103  *
0104  * @txchain_info: ???
0105  * @rxchain_info: ???
0106  * @acquisition_data: ???
0107  * @dsp_cfg_flags: set to 0
0108  */
0109 struct iwl_phy_context_cmd_tail {
0110     __le32 txchain_info;
0111     __le32 rxchain_info;
0112     __le32 acquisition_data;
0113     __le32 dsp_cfg_flags;
0114 } __packed;
0115
0116 /**
0117  * struct iwl_phy_context_cmd - config of the PHY context
0118  * ( PHY_CONTEXT_CMD = 0x8 )
0119  * @id_and_color: ID and color of the relevant Binding
0120  * @action: action to perform, one of FW_CTXT_ACTION_*
0121  * @apply_time: 0 means immediate apply and context switch.
0122  *  other value means apply new params after X usecs
0123  * @tx_param_color: ???
0124  * @ci: channel info
0125  * @tail: command tail
0126  */
0127 struct iwl_phy_context_cmd_v1 {
0128     /* COMMON_INDEX_HDR_API_S_VER_1 */
0129     __le32 id_and_color;
0130     __le32 action;
0131     /* PHY_CONTEXT_DATA_API_S_VER_3 */
0132     __le32 apply_time;
0133     __le32 tx_param_color;
0134     struct iwl_fw_channel_info ci;
0135     struct iwl_phy_context_cmd_tail tail;
0136 } __packed; /* PHY_CONTEXT_CMD_API_VER_1 */
0137
0138 /**
0139  * struct iwl_phy_context_cmd - config of the PHY context
0140  * ( PHY_CONTEXT_CMD = 0x8 )
0141  * @id_and_color: ID and color of the relevant Binding
0142  * @action: action to perform, one of FW_CTXT_ACTION_*
0143  * @lmac_id: the lmac id the phy context belongs to
0144  * @ci: channel info
0145  * @rxchain_info: ???
0146  * @dsp_cfg_flags: set to 0
0147  * @reserved: reserved to align to 64 bit
0148  */
0149 struct iwl_phy_context_cmd {
0150     /* COMMON_INDEX_HDR_API_S_VER_1 */
0151     __le32 id_and_color;
0152     __le32 action;
0153     /* PHY_CONTEXT_DATA_API_S_VER_3, PHY_CONTEXT_DATA_API_S_VER_4 */
0154     struct iwl_fw_channel_info ci;
0155     __le32 lmac_id;
0156     __le32 rxchain_info; /* reserved in _VER_4 */
0157     __le32 dsp_cfg_flags;
0158     __le32 reserved;
0159 } __packed; /* PHY_CONTEXT_CMD_API_VER_3, PHY_CONTEXT_CMD_API_VER_4 */
0160
0161 #endif /* __iwl_fw_api_phy_ctxt_h__ */