fw/api/debug.h

0001 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
0002 /*
0003  * Copyright (C) 2005-2014, 2018-2022 Intel Corporation
0004  * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
0005  * Copyright (C) 2016-2017 Intel Deutschland GmbH
0006  */
0007 #ifndef __iwl_fw_api_debug_h__
0008 #define __iwl_fw_api_debug_h__
0009
0010 /**
0011  * enum iwl_debug_cmds - debug commands
0012  */
0013 enum iwl_debug_cmds {
0014     /**
0015      * @LMAC_RD_WR:
0016      * LMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and
0017      * &struct iwl_dbg_mem_access_rsp
0018      */
0019     LMAC_RD_WR = 0x0,
0020     /**
0021      * @UMAC_RD_WR:
0022      * UMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and
0023      * &struct iwl_dbg_mem_access_rsp
0024      */
0025     UMAC_RD_WR = 0x1,
0026     /**
0027      * @HOST_EVENT_CFG:
0028      * updates the enabled event severities
0029      * &struct iwl_dbg_host_event_cfg_cmd
0030      */
0031     HOST_EVENT_CFG = 0x3,
0032     /**
0033      * @DBGC_SUSPEND_RESUME:
0034      * DBGC suspend/resume commad. Uses a single dword as data:
0035      * 0 - resume DBGC recording
0036      * 1 - suspend DBGC recording
0037      */
0038     DBGC_SUSPEND_RESUME = 0x7,
0039     /**
0040      * @BUFFER_ALLOCATION:
0041      * passes DRAM buffers to a DBGC
0042      * &struct iwl_buf_alloc_cmd
0043      */
0044     BUFFER_ALLOCATION = 0x8,
0045     /**
0046      * @FW_DUMP_COMPLETE_CMD:
0047      * sends command to fw once dump collection completed
0048      * &struct iwl_dbg_dump_complete_cmd
0049      */
0050     FW_DUMP_COMPLETE_CMD = 0xB,
0051     /**
0052      * @MFU_ASSERT_DUMP_NTF:
0053      * &struct iwl_mfu_assert_dump_notif
0054      */
0055     MFU_ASSERT_DUMP_NTF = 0xFE,
0056 };
0057
0058 /* Error response/notification */
0059 enum {
0060     FW_ERR_UNKNOWN_CMD = 0x0,
0061     FW_ERR_INVALID_CMD_PARAM = 0x1,
0062     FW_ERR_SERVICE = 0x2,
0063     FW_ERR_ARC_MEMORY = 0x3,
0064     FW_ERR_ARC_CODE = 0x4,
0065     FW_ERR_WATCH_DOG = 0x5,
0066     FW_ERR_WEP_GRP_KEY_INDX = 0x10,
0067     FW_ERR_WEP_KEY_SIZE = 0x11,
0068     FW_ERR_OBSOLETE_FUNC = 0x12,
0069     FW_ERR_UNEXPECTED = 0xFE,
0070     FW_ERR_FATAL = 0xFF
0071 };
0072
0073 /** enum iwl_dbg_suspend_resume_cmds - dbgc suspend resume operations
0074  * dbgc suspend resume command operations
0075  * @DBGC_RESUME_CMD: resume dbgc recording
0076  * @DBGC_SUSPEND_CMD: stop dbgc recording
0077  */
0078 enum iwl_dbg_suspend_resume_cmds {
0079     DBGC_RESUME_CMD,
0080     DBGC_SUSPEND_CMD,
0081 };
0082
0083 /**
0084  * struct iwl_error_resp - FW error indication
0085  * ( REPLY_ERROR = 0x2 )
0086  * @error_type: one of FW_ERR_*
0087  * @cmd_id: the command ID for which the error occurred
0088  * @reserved1: reserved
0089  * @bad_cmd_seq_num: sequence number of the erroneous command
0090  * @error_service: which service created the error, applicable only if
0091  *     error_type = 2, otherwise 0
0092  * @timestamp: TSF in usecs.
0093  */
0094 struct iwl_error_resp {
0095     __le32 error_type;
0096     u8 cmd_id;
0097     u8 reserved1;
0098     __le16 bad_cmd_seq_num;
0099     __le32 error_service;
0100     __le64 timestamp;
0101 } __packed;
0102
0103 #define TX_FIFO_MAX_NUM_9000        8
0104 #define TX_FIFO_MAX_NUM         15
0105 #define RX_FIFO_MAX_NUM         2
0106 #define TX_FIFO_INTERNAL_MAX_NUM    6
0107
0108 /**
0109  * struct iwl_shared_mem_cfg_v2 - Shared memory configuration information
0110  *
0111  * @shared_mem_addr: shared memory addr (pre 8000 HW set to 0x0 as MARBH is not
0112  *  accessible)
0113  * @shared_mem_size: shared memory size
0114  * @sample_buff_addr: internal sample (mon/adc) buff addr (pre 8000 HW set to
0115  *  0x0 as accessible only via DBGM RDAT)
0116  * @sample_buff_size: internal sample buff size
0117  * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB), (pre
0118  *  8000 HW set to 0x0 as not accessible)
0119  * @txfifo_size: size of TXF0 ... TXF7
0120  * @rxfifo_size: RXF1, RXF2 sizes. If there is no RXF2, it'll have a value of 0
0121  * @page_buff_addr: used by UMAC and performance debug (page miss analysis),
0122  *  when paging is not supported this should be 0
0123  * @page_buff_size: size of %page_buff_addr
0124  * @rxfifo_addr: Start address of rxFifo
0125  * @internal_txfifo_addr: start address of internalFifo
0126  * @internal_txfifo_size: internal fifos' size
0127  *
0128  * NOTE: on firmware that don't have IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG
0129  *   set, the last 3 members don't exist.
0130  */
0131 struct iwl_shared_mem_cfg_v2 {
0132     __le32 shared_mem_addr;
0133     __le32 shared_mem_size;
0134     __le32 sample_buff_addr;
0135     __le32 sample_buff_size;
0136     __le32 txfifo_addr;
0137     __le32 txfifo_size[TX_FIFO_MAX_NUM_9000];
0138     __le32 rxfifo_size[RX_FIFO_MAX_NUM];
0139     __le32 page_buff_addr;
0140     __le32 page_buff_size;
0141     __le32 rxfifo_addr;
0142     __le32 internal_txfifo_addr;
0143     __le32 internal_txfifo_size[TX_FIFO_INTERNAL_MAX_NUM];
0144 } __packed; /* SHARED_MEM_ALLOC_API_S_VER_2 */
0145
0146 /**
0147  * struct iwl_shared_mem_lmac_cfg - LMAC shared memory configuration
0148  *
0149  * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB)
0150  * @txfifo_size: size of TX FIFOs
0151  * @rxfifo1_addr: RXF1 addr
0152  * @rxfifo1_size: RXF1 size
0153  */
0154 struct iwl_shared_mem_lmac_cfg {
0155     __le32 txfifo_addr;
0156     __le32 txfifo_size[TX_FIFO_MAX_NUM];
0157     __le32 rxfifo1_addr;
0158     __le32 rxfifo1_size;
0159
0160 } __packed; /* SHARED_MEM_ALLOC_LMAC_API_S_VER_1 */
0161
0162 /**
0163  * struct iwl_shared_mem_cfg - Shared memory configuration information
0164  *
0165  * @shared_mem_addr: shared memory address
0166  * @shared_mem_size: shared memory size
0167  * @sample_buff_addr: internal sample (mon/adc) buff addr
0168  * @sample_buff_size: internal sample buff size
0169  * @rxfifo2_addr: start addr of RXF2
0170  * @rxfifo2_size: size of RXF2
0171  * @page_buff_addr: used by UMAC and performance debug (page miss analysis),
0172  *  when paging is not supported this should be 0
0173  * @page_buff_size: size of %page_buff_addr
0174  * @lmac_num: number of LMACs (1 or 2)
0175  * @lmac_smem: per - LMAC smem data
0176  * @rxfifo2_control_addr: start addr of RXF2C
0177  * @rxfifo2_control_size: size of RXF2C
0178  */
0179 struct iwl_shared_mem_cfg {
0180     __le32 shared_mem_addr;
0181     __le32 shared_mem_size;
0182     __le32 sample_buff_addr;
0183     __le32 sample_buff_size;
0184     __le32 rxfifo2_addr;
0185     __le32 rxfifo2_size;
0186     __le32 page_buff_addr;
0187     __le32 page_buff_size;
0188     __le32 lmac_num;
0189     struct iwl_shared_mem_lmac_cfg lmac_smem[3];
0190     __le32 rxfifo2_control_addr;
0191     __le32 rxfifo2_control_size;
0192 } __packed; /* SHARED_MEM_ALLOC_API_S_VER_4 */
0193
0194 /**
0195  * struct iwl_mfuart_load_notif_v1 - mfuart image version & status
0196  * ( MFUART_LOAD_NOTIFICATION = 0xb1 )
0197  * @installed_ver: installed image version
0198  * @external_ver: external image version
0199  * @status: MFUART loading status
0200  * @duration: MFUART loading time
0201 */
0202 struct iwl_mfuart_load_notif_v1 {
0203     __le32 installed_ver;
0204     __le32 external_ver;
0205     __le32 status;
0206     __le32 duration;
0207 } __packed; /* MFU_LOADER_NTFY_API_S_VER_1 */
0208
0209 /**
0210  * struct iwl_mfuart_load_notif - mfuart image version & status
0211  * ( MFUART_LOAD_NOTIFICATION = 0xb1 )
0212  * @installed_ver: installed image version
0213  * @external_ver: external image version
0214  * @status: MFUART loading status
0215  * @duration: MFUART loading time
0216  * @image_size: MFUART image size in bytes
0217 */
0218 struct iwl_mfuart_load_notif {
0219     __le32 installed_ver;
0220     __le32 external_ver;
0221     __le32 status;
0222     __le32 duration;
0223     /* image size valid only in v2 of the command */
0224     __le32 image_size;
0225 } __packed; /* MFU_LOADER_NTFY_API_S_VER_2 */
0226
0227 /**
0228  * struct iwl_mfu_assert_dump_notif - mfuart dump logs
0229  * ( MFU_ASSERT_DUMP_NTF = 0xfe )
0230  * @assert_id: mfuart assert id that cause the notif
0231  * @curr_reset_num: number of asserts since uptime
0232  * @index_num: current chunk id
0233  * @parts_num: total number of chunks
0234  * @data_size: number of data bytes sent
0235  * @data: data buffer
0236  */
0237 struct iwl_mfu_assert_dump_notif {
0238     __le32   assert_id;
0239     __le32   curr_reset_num;
0240     __le16   index_num;
0241     __le16   parts_num;
0242     __le32   data_size;
0243     __le32   data[];
0244 } __packed; /* MFU_DUMP_ASSERT_API_S_VER_1 */
0245
0246 /**
0247  * enum iwl_mvm_marker_id - marker ids
0248  *
0249  * The ids for different type of markers to insert into the usniffer logs
0250  *
0251  * @MARKER_ID_TX_FRAME_LATENCY: TX latency marker
0252  * @MARKER_ID_SYNC_CLOCK: sync FW time and systime
0253  */
0254 enum iwl_mvm_marker_id {
0255     MARKER_ID_TX_FRAME_LATENCY = 1,
0256     MARKER_ID_SYNC_CLOCK = 2,
0257 }; /* MARKER_ID_API_E_VER_2 */
0258
0259 /**
0260  * struct iwl_mvm_marker - mark info into the usniffer logs
0261  *
0262  * (MARKER_CMD = 0xcb)
0263  *
0264  * Mark the UTC time stamp into the usniffer logs together with additional
0265  * metadata, so the usniffer output can be parsed.
0266  * In the command response the ucode will return the GP2 time.
0267  *
0268  * @dw_len: The amount of dwords following this byte including this byte.
0269  * @marker_id: A unique marker id (iwl_mvm_marker_id).
0270  * @reserved: reserved.
0271  * @timestamp: in milliseconds since 1970-01-01 00:00:00 UTC
0272  * @metadata: additional meta data that will be written to the unsiffer log
0273  */
0274 struct iwl_mvm_marker {
0275     u8 dw_len;
0276     u8 marker_id;
0277     __le16 reserved;
0278     __le64 timestamp;
0279     __le32 metadata[];
0280 } __packed; /* MARKER_API_S_VER_1 */
0281
0282 /**
0283  * struct iwl_mvm_marker_rsp - Response to marker cmd
0284  *
0285  * @gp2: The gp2 clock value in the FW
0286  */
0287 struct iwl_mvm_marker_rsp {
0288     __le32 gp2;
0289 } __packed;
0290
0291 /* Operation types for the debug mem access */
0292 enum {
0293     DEBUG_MEM_OP_READ = 0,
0294     DEBUG_MEM_OP_WRITE = 1,
0295     DEBUG_MEM_OP_WRITE_BYTES = 2,
0296 };
0297
0298 #define DEBUG_MEM_MAX_SIZE_DWORDS 32
0299
0300 /**
0301  * struct iwl_dbg_mem_access_cmd - Request the device to read/write memory
0302  * @op: DEBUG_MEM_OP_*
0303  * @addr: address to read/write from/to
0304  * @len: in dwords, to read/write
0305  * @data: for write opeations, contains the source buffer
0306  */
0307 struct iwl_dbg_mem_access_cmd {
0308     __le32 op;
0309     __le32 addr;
0310     __le32 len;
0311     __le32 data[];
0312 } __packed; /* DEBUG_(U|L)MAC_RD_WR_CMD_API_S_VER_1 */
0313
0314 /* Status responses for the debug mem access */
0315 enum {
0316     DEBUG_MEM_STATUS_SUCCESS = 0x0,
0317     DEBUG_MEM_STATUS_FAILED = 0x1,
0318     DEBUG_MEM_STATUS_LOCKED = 0x2,
0319     DEBUG_MEM_STATUS_HIDDEN = 0x3,
0320     DEBUG_MEM_STATUS_LENGTH = 0x4,
0321 };
0322
0323 /**
0324  * struct iwl_dbg_mem_access_rsp - Response to debug mem commands
0325  * @status: DEBUG_MEM_STATUS_*
0326  * @len: read dwords (0 for write operations)
0327  * @data: contains the read DWs
0328  */
0329 struct iwl_dbg_mem_access_rsp {
0330     __le32 status;
0331     __le32 len;
0332     __le32 data[];
0333 } __packed; /* DEBUG_(U|L)MAC_RD_WR_RSP_API_S_VER_1 */
0334
0335 /**
0336  * struct iwl_dbg_suspend_resume_cmd - dbgc suspend resume command
0337  * @operation: suspend or resume operation, uses
0338  *  &enum iwl_dbg_suspend_resume_cmds
0339  */
0340 struct iwl_dbg_suspend_resume_cmd {
0341     __le32 operation;
0342 } __packed;
0343
0344 #define BUF_ALLOC_MAX_NUM_FRAGS 16
0345
0346 /**
0347  * struct iwl_buf_alloc_frag - a DBGC fragment
0348  * @addr: base address of the fragment
0349  * @size: size of the fragment
0350  */
0351 struct iwl_buf_alloc_frag {
0352     __le64 addr;
0353     __le32 size;
0354 } __packed; /* FRAGMENT_STRUCTURE_API_S_VER_1 */
0355
0356 /**
0357  * struct iwl_buf_alloc_cmd - buffer allocation command
0358  * @alloc_id: &enum iwl_fw_ini_allocation_id
0359  * @buf_location: &enum iwl_fw_ini_buffer_location
0360  * @num_frags: number of fragments
0361  * @frags: fragments array
0362  */
0363 struct iwl_buf_alloc_cmd {
0364     __le32 alloc_id;
0365     __le32 buf_location;
0366     __le32 num_frags;
0367     struct iwl_buf_alloc_frag frags[BUF_ALLOC_MAX_NUM_FRAGS];
0368 } __packed; /* BUFFER_ALLOCATION_CMD_API_S_VER_2 */
0369
0370 #define DRAM_INFO_FIRST_MAGIC_WORD 0x76543210
0371 #define DRAM_INFO_SECOND_MAGIC_WORD 0x89ABCDEF
0372
0373 /**
0374  * struct iwL_dram_info - DRAM fragments allocation struct
0375  *
0376  * Driver will fill in the first 1K(+) of the pointed DRAM fragment
0377  *
0378  * @first_word: magic word value
0379  * @second_word: magic word value
0380  * @framfrags: DRAM fragmentaion detail
0381 */
0382 struct iwl_dram_info {
0383     __le32 first_word;
0384     __le32 second_word;
0385     struct iwl_buf_alloc_cmd dram_frags[IWL_FW_INI_ALLOCATION_NUM - 1];
0386 } __packed; /* INIT_DRAM_FRAGS_ALLOCATIONS_S_VER_1 */
0387
0388 /**
0389  * struct iwl_dbgc1_info - DBGC1 address and size
0390  *
0391  * Driver will fill the dbcg1 address and size at address based on config TLV.
0392  *
0393  * @first_word: all 0 set as identifier
0394  * @dbgc1_add_lsb: LSB bits of DBGC1 physical address
0395  * @dbgc1_add_msb: MSB bits of DBGC1 physical address
0396  * @dbgc1_size: DBGC1 size
0397 */
0398 struct iwl_dbgc1_info {
0399     __le32 first_word;
0400     __le32 dbgc1_add_lsb;
0401     __le32 dbgc1_add_msb;
0402     __le32 dbgc1_size;
0403 } __packed; /* INIT_DRAM_FRAGS_ALLOCATIONS_S_VER_1 */
0404
0405 /**
0406  * struct iwl_dbg_host_event_cfg_cmd
0407  * @enabled_severities: enabled severities
0408  */
0409 struct iwl_dbg_host_event_cfg_cmd {
0410     __le32 enabled_severities;
0411 } __packed; /* DEBUG_HOST_EVENT_CFG_CMD_API_S_VER_1 */
0412
0413 /**
0414  * struct iwl_dbg_dump_complete_cmd - dump complete cmd
0415  *
0416  * @tp: timepoint whose dump has completed
0417  * @tp_data: timepoint data
0418  */
0419 struct iwl_dbg_dump_complete_cmd {
0420     __le32 tp;
0421     __le32 tp_data;
0422 } __packed; /* FW_DUMP_COMPLETE_CMD_API_S_VER_1 */
0423
0424 #endif /* __iwl_fw_api_debug_h__ */