Back to home page

OSCL-LXR

 
 

    


0001 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
0002 /*
0003  * Copyright (C) 2015-2017 Intel Deutschland GmbH
0004  * Copyright (C) 2018-2022 Intel Corporation
0005  */
0006 #include <linux/module.h>
0007 #include <linux/stringify.h>
0008 #include "iwl-config.h"
0009 #include "iwl-prph.h"
0010 #include "fw/api/txq.h"
0011 
0012 /* Highest firmware API version supported */
0013 #define IWL_22000_UCODE_API_MAX 72
0014 
0015 /* Lowest firmware API version supported */
0016 #define IWL_22000_UCODE_API_MIN 39
0017 
0018 /* NVM versions */
0019 #define IWL_22000_NVM_VERSION       0x0a1d
0020 
0021 /* Memory offsets and lengths */
0022 #define IWL_22000_DCCM_OFFSET       0x800000 /* LMAC1 */
0023 #define IWL_22000_DCCM_LEN      0x10000 /* LMAC1 */
0024 #define IWL_22000_DCCM2_OFFSET      0x880000
0025 #define IWL_22000_DCCM2_LEN     0x8000
0026 #define IWL_22000_SMEM_OFFSET       0x400000
0027 #define IWL_22000_SMEM_LEN      0xD0000
0028 
0029 #define IWL_QU_B_HR_B_FW_PRE        "iwlwifi-Qu-b0-hr-b0-"
0030 #define IWL_QNJ_B_HR_B_FW_PRE       "iwlwifi-QuQnj-b0-hr-b0-"
0031 #define IWL_QU_C_HR_B_FW_PRE        "iwlwifi-Qu-c0-hr-b0-"
0032 #define IWL_QU_B_JF_B_FW_PRE        "iwlwifi-Qu-b0-jf-b0-"
0033 #define IWL_QU_C_JF_B_FW_PRE        "iwlwifi-Qu-c0-jf-b0-"
0034 #define IWL_QUZ_A_HR_B_FW_PRE       "iwlwifi-QuZ-a0-hr-b0-"
0035 #define IWL_QUZ_A_JF_B_FW_PRE       "iwlwifi-QuZ-a0-jf-b0-"
0036 #define IWL_QNJ_B_JF_B_FW_PRE       "iwlwifi-QuQnj-b0-jf-b0-"
0037 #define IWL_CC_A_FW_PRE         "iwlwifi-cc-a0-"
0038 #define IWL_SO_A_JF_B_FW_PRE        "iwlwifi-so-a0-jf-b0-"
0039 #define IWL_SO_A_HR_B_FW_PRE        "iwlwifi-so-a0-hr-b0-"
0040 #define IWL_SO_A_GF_A_FW_PRE        "iwlwifi-so-a0-gf-a0-"
0041 #define IWL_TY_A_GF_A_FW_PRE        "iwlwifi-ty-a0-gf-a0-"
0042 #define IWL_SO_A_GF4_A_FW_PRE       "iwlwifi-so-a0-gf4-a0-"
0043 #define IWL_SO_A_MR_A_FW_PRE        "iwlwifi-so-a0-mr-a0-"
0044 #define IWL_SNJ_A_GF4_A_FW_PRE      "iwlwifi-SoSnj-a0-gf4-a0-"
0045 #define IWL_SNJ_A_GF_A_FW_PRE       "iwlwifi-SoSnj-a0-gf-a0-"
0046 #define IWL_SNJ_A_HR_B_FW_PRE       "iwlwifi-SoSnj-a0-hr-b0-"
0047 #define IWL_SNJ_A_JF_B_FW_PRE       "iwlwifi-SoSnj-a0-jf-b0-"
0048 #define IWL_MA_A_HR_B_FW_PRE        "iwlwifi-ma-a0-hr-b0-"
0049 #define IWL_MA_A_GF_A_FW_PRE        "iwlwifi-ma-a0-gf-a0-"
0050 #define IWL_MA_A_GF4_A_FW_PRE       "iwlwifi-ma-a0-gf4-a0-"
0051 #define IWL_MA_A_MR_A_FW_PRE        "iwlwifi-ma-a0-mr-a0-"
0052 #define IWL_MA_A_FM_A_FW_PRE        "iwlwifi-ma-a0-fm-a0-"
0053 #define IWL_SNJ_A_MR_A_FW_PRE       "iwlwifi-SoSnj-a0-mr-a0-"
0054 #define IWL_BZ_A_HR_B_FW_PRE        "iwlwifi-bz-a0-hr-b0-"
0055 #define IWL_BZ_A_GF_A_FW_PRE        "iwlwifi-bz-a0-gf-a0-"
0056 #define IWL_BZ_A_GF4_A_FW_PRE       "iwlwifi-bz-a0-gf4-a0-"
0057 #define IWL_BZ_A_MR_A_FW_PRE        "iwlwifi-bz-a0-mr-a0-"
0058 #define IWL_BZ_A_FM_A_FW_PRE        "iwlwifi-bz-a0-fm-a0-"
0059 #define IWL_GL_A_FM_A_FW_PRE        "iwlwifi-gl-a0-fm-a0-"
0060 #define IWL_BZ_Z_GF_A_FW_PRE        "iwlwifi-bz-z0-gf-a0-"
0061 #define IWL_BNJ_A_FM_A_FW_PRE       "iwlwifi-BzBnj-a0-fm-a0-"
0062 #define IWL_BNJ_A_FM4_A_FW_PRE      "iwlwifi-BzBnj-a0-fm4-a0-"
0063 #define IWL_BNJ_A_GF_A_FW_PRE       "iwlwifi-BzBnj-a0-gf-a0-"
0064 #define IWL_BNJ_A_GF4_A_FW_PRE      "iwlwifi-BzBnj-a0-gf4-a0-"
0065 #define IWL_BNJ_A_HR_B_FW_PRE       "iwlwifi-BzBnj-a0-hr-b0-"
0066 
0067 
0068 #define IWL_QU_B_HR_B_MODULE_FIRMWARE(api) \
0069     IWL_QU_B_HR_B_FW_PRE __stringify(api) ".ucode"
0070 #define IWL_QNJ_B_HR_B_MODULE_FIRMWARE(api) \
0071     IWL_QNJ_B_HR_B_FW_PRE __stringify(api) ".ucode"
0072 #define IWL_QUZ_A_HR_B_MODULE_FIRMWARE(api) \
0073     IWL_QUZ_A_HR_B_FW_PRE __stringify(api) ".ucode"
0074 #define IWL_QUZ_A_JF_B_MODULE_FIRMWARE(api) \
0075     IWL_QUZ_A_JF_B_FW_PRE __stringify(api) ".ucode"
0076 #define IWL_QU_C_HR_B_MODULE_FIRMWARE(api) \
0077     IWL_QU_C_HR_B_FW_PRE __stringify(api) ".ucode"
0078 #define IWL_QU_B_JF_B_MODULE_FIRMWARE(api) \
0079     IWL_QU_B_JF_B_FW_PRE __stringify(api) ".ucode"
0080 #define IWL_QNJ_B_JF_B_MODULE_FIRMWARE(api)     \
0081     IWL_QNJ_B_JF_B_FW_PRE __stringify(api) ".ucode"
0082 #define IWL_CC_A_MODULE_FIRMWARE(api)           \
0083     IWL_CC_A_FW_PRE __stringify(api) ".ucode"
0084 #define IWL_SO_A_JF_B_MODULE_FIRMWARE(api) \
0085     IWL_SO_A_JF_B_FW_PRE __stringify(api) ".ucode"
0086 #define IWL_SO_A_HR_B_MODULE_FIRMWARE(api) \
0087     IWL_SO_A_HR_B_FW_PRE __stringify(api) ".ucode"
0088 #define IWL_SO_A_GF_A_MODULE_FIRMWARE(api) \
0089     IWL_SO_A_GF_A_FW_PRE __stringify(api) ".ucode"
0090 #define IWL_TY_A_GF_A_MODULE_FIRMWARE(api) \
0091     IWL_TY_A_GF_A_FW_PRE __stringify(api) ".ucode"
0092 #define IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(api) \
0093     IWL_SNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode"
0094 #define IWL_SNJ_A_GF_A_MODULE_FIRMWARE(api) \
0095     IWL_SNJ_A_GF_A_FW_PRE __stringify(api) ".ucode"
0096 #define IWL_SNJ_A_HR_B_MODULE_FIRMWARE(api) \
0097     IWL_SNJ_A_HR_B_FW_PRE __stringify(api) ".ucode"
0098 #define IWL_SNJ_A_JF_B_MODULE_FIRMWARE(api) \
0099     IWL_SNJ_A_JF_B_FW_PRE __stringify(api) ".ucode"
0100 #define IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(api)       \
0101     IWL_MA_A_HR_B_FW_PRE __stringify(api) ".ucode"
0102 #define IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(api)       \
0103     IWL_MA_A_GF_A_FW_PRE __stringify(api) ".ucode"
0104 #define IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(api)      \
0105     IWL_MA_A_GF4_A_FW_PRE __stringify(api) ".ucode"
0106 #define IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(api) \
0107     IWL_MA_A_MR_A_FW_PRE __stringify(api) ".ucode"
0108 #define IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(api)       \
0109     IWL_MA_A_FM_A_FW_PRE __stringify(api) ".ucode"
0110 #define IWL_SNJ_A_MR_A_MODULE_FIRMWARE(api) \
0111     IWL_SNJ_A_MR_A_FW_PRE __stringify(api) ".ucode"
0112 #define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \
0113     IWL_BZ_A_HR_B_FW_PRE __stringify(api) ".ucode"
0114 #define IWL_BZ_A_GF_A_MODULE_FIRMWARE(api) \
0115     IWL_BZ_A_GF_A_FW_PRE __stringify(api) ".ucode"
0116 #define IWL_BZ_A_GF4_A_MODULE_FIRMWARE(api) \
0117     IWL_BZ_A_GF4_A_FW_PRE __stringify(api) ".ucode"
0118 #define IWL_BZ_A_MR_A_MODULE_FIRMWARE(api) \
0119     IWL_BZ_A_MR_A_FW_PRE __stringify(api) ".ucode"
0120 #define IWL_BZ_A_FM_A_MODULE_FIRMWARE(api) \
0121         IWL_BZ_A_FM_A_FW_PRE __stringify(api) ".ucode"
0122 #define IWL_GL_A_FM_A_MODULE_FIRMWARE(api) \
0123         IWL_GL_A_FM_A_FW_PRE __stringify(api) ".ucode"
0124 #define IWL_BNJ_A_FM_A_MODULE_FIRMWARE(api) \
0125     IWL_BNJ_A_FM_A_FW_PRE __stringify(api) ".ucode"
0126 #define IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(api) \
0127     IWL_BNJ_A_FM4_A_FW_PRE __stringify(api) ".ucode"
0128 #define IWL_BNJ_A_GF_A_MODULE_FIRMWARE(api) \
0129     IWL_BNJ_A_GF_A_FW_PRE __stringify(api) ".ucode"
0130 #define IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(api) \
0131     IWL_BNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode"
0132 #define IWL_BNJ_A_HR_B_MODULE_FIRMWARE(api) \
0133     IWL_BNJ_A_HR_B_FW_PRE __stringify(api) ".ucode"
0134 
0135 static const struct iwl_base_params iwl_22000_base_params = {
0136     .eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
0137     .num_of_queues = 512,
0138     .max_tfd_queue_size = 256,
0139     .shadow_ram_support = true,
0140     .led_compensation = 57,
0141     .wd_timeout = IWL_LONG_WD_TIMEOUT,
0142     .max_event_log_size = 512,
0143     .shadow_reg_enable = true,
0144     .pcie_l1_allowed = true,
0145 };
0146 
0147 static const struct iwl_base_params iwl_ax210_base_params = {
0148     .eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
0149     .num_of_queues = 512,
0150     .max_tfd_queue_size = 65536,
0151     .shadow_ram_support = true,
0152     .led_compensation = 57,
0153     .wd_timeout = IWL_LONG_WD_TIMEOUT,
0154     .max_event_log_size = 512,
0155     .shadow_reg_enable = true,
0156     .pcie_l1_allowed = true,
0157 };
0158 
0159 static const struct iwl_ht_params iwl_22000_ht_params = {
0160     .stbc = true,
0161     .ldpc = true,
0162     .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) |
0163               BIT(NL80211_BAND_6GHZ),
0164 };
0165 
0166 #define IWL_DEVICE_22000_COMMON                     \
0167     .ucode_api_max = IWL_22000_UCODE_API_MAX,           \
0168     .ucode_api_min = IWL_22000_UCODE_API_MIN,           \
0169     .led_mode = IWL_LED_RF_STATE,                   \
0170     .nvm_hw_section_num = 10,                   \
0171     .non_shared_ant = ANT_B,                    \
0172     .dccm_offset = IWL_22000_DCCM_OFFSET,               \
0173     .dccm_len = IWL_22000_DCCM_LEN,                 \
0174     .dccm2_offset = IWL_22000_DCCM2_OFFSET,             \
0175     .dccm2_len = IWL_22000_DCCM2_LEN,               \
0176     .smem_offset = IWL_22000_SMEM_OFFSET,               \
0177     .smem_len = IWL_22000_SMEM_LEN,                 \
0178     .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,       \
0179     .apmg_not_supported = true,                 \
0180     .trans.mq_rx_supported = true,                  \
0181     .vht_mu_mimo_supported = true,                  \
0182     .mac_addr_from_csr = 0x380,                 \
0183     .ht_params = &iwl_22000_ht_params,              \
0184     .nvm_ver = IWL_22000_NVM_VERSION,               \
0185     .trans.use_tfh = true,                      \
0186     .trans.rf_id = true,                        \
0187     .trans.gen2 = true,                     \
0188     .nvm_type = IWL_NVM_EXT,                    \
0189     .dbgc_supported = true,                     \
0190     .min_umac_error_event_table = 0x400000,             \
0191     .d3_debug_data_base_addr = 0x401000,                \
0192     .d3_debug_data_length = 60 * 1024,              \
0193     .mon_smem_regs = {                      \
0194         .write_ptr = {                      \
0195             .addr = LDBG_M2S_BUF_WPTR,          \
0196             .mask = LDBG_M2S_BUF_WPTR_VAL_MSK,      \
0197     },                              \
0198         .cycle_cnt = {                      \
0199             .addr = LDBG_M2S_BUF_WRAP_CNT,          \
0200             .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK,      \
0201         },                          \
0202     }
0203 
0204 #define IWL_DEVICE_22500                        \
0205     IWL_DEVICE_22000_COMMON,                    \
0206     .trans.device_family = IWL_DEVICE_FAMILY_22000,         \
0207     .trans.base_params = &iwl_22000_base_params,            \
0208     .gp2_reg_addr = 0xa02c68,                   \
0209     .mon_dram_regs = {                      \
0210         .write_ptr = {                      \
0211             .addr = MON_BUFF_WRPTR_VER2,            \
0212             .mask = 0xffffffff,             \
0213         },                          \
0214         .cycle_cnt = {                      \
0215             .addr = MON_BUFF_CYCLE_CNT_VER2,        \
0216             .mask = 0xffffffff,             \
0217         },                          \
0218     }
0219 
0220 #define IWL_DEVICE_AX210                        \
0221     IWL_DEVICE_22000_COMMON,                    \
0222     .trans.umac_prph_offset = 0x300000,             \
0223     .trans.device_family = IWL_DEVICE_FAMILY_AX210,         \
0224     .trans.base_params = &iwl_ax210_base_params,            \
0225     .min_txq_size = 128,                        \
0226     .gp2_reg_addr = 0xd02c68,                   \
0227     .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_HE,       \
0228     .mon_dram_regs = {                      \
0229         .write_ptr = {                      \
0230             .addr = DBGC_CUR_DBGBUF_STATUS,         \
0231             .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK,  \
0232         },                          \
0233         .cycle_cnt = {                      \
0234             .addr = DBGC_DBGBUF_WRAP_AROUND,        \
0235             .mask = 0xffffffff,             \
0236         },                          \
0237         .cur_frag = {                       \
0238             .addr = DBGC_CUR_DBGBUF_STATUS,         \
0239             .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK,     \
0240         },                          \
0241     }
0242 
0243 #define IWL_DEVICE_BZ_COMMON                        \
0244     .ucode_api_max = IWL_22000_UCODE_API_MAX,           \
0245     .ucode_api_min = IWL_22000_UCODE_API_MIN,           \
0246     .led_mode = IWL_LED_RF_STATE,                   \
0247     .nvm_hw_section_num = 10,                   \
0248     .non_shared_ant = ANT_B,                    \
0249     .dccm_offset = IWL_22000_DCCM_OFFSET,               \
0250     .dccm_len = IWL_22000_DCCM_LEN,                 \
0251     .dccm2_offset = IWL_22000_DCCM2_OFFSET,             \
0252     .dccm2_len = IWL_22000_DCCM2_LEN,               \
0253     .smem_offset = IWL_22000_SMEM_OFFSET,               \
0254     .smem_len = IWL_22000_SMEM_LEN,                 \
0255     .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,    \
0256     .apmg_not_supported = true,                 \
0257     .trans.mq_rx_supported = true,                  \
0258     .vht_mu_mimo_supported = true,                  \
0259     .mac_addr_from_csr = 0x30,                  \
0260     .ht_params = &iwl_22000_ht_params,              \
0261     .nvm_ver = IWL_22000_NVM_VERSION,               \
0262     .trans.use_tfh = true,                      \
0263     .trans.rf_id = true,                        \
0264     .trans.gen2 = true,                     \
0265     .nvm_type = IWL_NVM_EXT,                    \
0266     .dbgc_supported = true,                     \
0267     .min_umac_error_event_table = 0x400000,             \
0268     .d3_debug_data_base_addr = 0x401000,                \
0269     .d3_debug_data_length = 60 * 1024,              \
0270     .mon_smem_regs = {                      \
0271         .write_ptr = {                      \
0272             .addr = LDBG_M2S_BUF_WPTR,          \
0273             .mask = LDBG_M2S_BUF_WPTR_VAL_MSK,      \
0274     },                              \
0275         .cycle_cnt = {                      \
0276             .addr = LDBG_M2S_BUF_WRAP_CNT,          \
0277             .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK,      \
0278         },                          \
0279     }
0280 
0281 #define IWL_DEVICE_BZ                           \
0282     IWL_DEVICE_BZ_COMMON,                       \
0283     .trans.umac_prph_offset = 0x300000,             \
0284     .trans.device_family = IWL_DEVICE_FAMILY_BZ,            \
0285     .trans.base_params = &iwl_ax210_base_params,            \
0286     .min_txq_size = 128,                        \
0287     .gp2_reg_addr = 0xd02c68,                   \
0288     .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT,      \
0289     .mon_dram_regs = {                      \
0290         .write_ptr = {                      \
0291             .addr = DBGC_CUR_DBGBUF_STATUS,         \
0292             .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK,  \
0293         },                          \
0294         .cycle_cnt = {                      \
0295             .addr = DBGC_DBGBUF_WRAP_AROUND,        \
0296             .mask = 0xffffffff,             \
0297         },                          \
0298         .cur_frag = {                       \
0299             .addr = DBGC_CUR_DBGBUF_STATUS,         \
0300             .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK,     \
0301         },                          \
0302     },                              \
0303     .mon_dbgi_regs = {                      \
0304         .write_ptr = {                      \
0305             .addr = DBGI_SRAM_FIFO_POINTERS,        \
0306             .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, \
0307         },                          \
0308     }
0309 
0310 const struct iwl_cfg_trans_params iwl_qnj_trans_cfg = {
0311     .mq_rx_supported = true,
0312     .use_tfh = true,
0313     .rf_id = true,
0314     .gen2 = true,
0315     .device_family = IWL_DEVICE_FAMILY_22000,
0316     .base_params = &iwl_22000_base_params,
0317 };
0318 
0319 const struct iwl_cfg_trans_params iwl_qu_trans_cfg = {
0320     .mq_rx_supported = true,
0321     .use_tfh = true,
0322     .rf_id = true,
0323     .gen2 = true,
0324     .device_family = IWL_DEVICE_FAMILY_22000,
0325     .base_params = &iwl_22000_base_params,
0326     .integrated = true,
0327     .xtal_latency = 500,
0328     .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US,
0329 };
0330 
0331 const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg = {
0332     .mq_rx_supported = true,
0333     .use_tfh = true,
0334     .rf_id = true,
0335     .gen2 = true,
0336     .device_family = IWL_DEVICE_FAMILY_22000,
0337     .base_params = &iwl_22000_base_params,
0338     .integrated = true,
0339     .xtal_latency = 1820,
0340     .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_1820US,
0341 };
0342 
0343 const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg = {
0344     .mq_rx_supported = true,
0345     .use_tfh = true,
0346     .rf_id = true,
0347     .gen2 = true,
0348     .device_family = IWL_DEVICE_FAMILY_22000,
0349     .base_params = &iwl_22000_base_params,
0350     .integrated = true,
0351     .xtal_latency = 12000,
0352     .low_latency_xtal = true,
0353     .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
0354 };
0355 
0356 const struct iwl_cfg_trans_params iwl_snj_trans_cfg = {
0357     .mq_rx_supported = true,
0358     .use_tfh = true,
0359     .rf_id = true,
0360     .gen2 = true,
0361     .device_family = IWL_DEVICE_FAMILY_AX210,
0362     .base_params = &iwl_ax210_base_params,
0363     .umac_prph_offset = 0x300000,
0364 };
0365 
0366 const struct iwl_cfg_trans_params iwl_so_trans_cfg = {
0367     .mq_rx_supported = true,
0368     .use_tfh = true,
0369     .rf_id = true,
0370     .gen2 = true,
0371     .device_family = IWL_DEVICE_FAMILY_AX210,
0372     .base_params = &iwl_ax210_base_params,
0373     .umac_prph_offset = 0x300000,
0374     .integrated = true,
0375     /* TODO: the following values need to be checked */
0376     .xtal_latency = 500,
0377     .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US,
0378 };
0379 
0380 const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg = {
0381     .mq_rx_supported = true,
0382     .use_tfh = true,
0383     .rf_id = true,
0384     .gen2 = true,
0385     .device_family = IWL_DEVICE_FAMILY_AX210,
0386     .base_params = &iwl_ax210_base_params,
0387     .umac_prph_offset = 0x300000,
0388     .integrated = true,
0389     .low_latency_xtal = true,
0390     .xtal_latency = 12000,
0391     .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
0392 };
0393 
0394 const struct iwl_cfg_trans_params iwl_so_long_latency_imr_trans_cfg = {
0395     .mq_rx_supported = true,
0396     .use_tfh = true,
0397     .rf_id = true,
0398     .gen2 = true,
0399     .device_family = IWL_DEVICE_FAMILY_AX210,
0400     .base_params = &iwl_ax210_base_params,
0401     .umac_prph_offset = 0x300000,
0402     .integrated = true,
0403     .low_latency_xtal = true,
0404     .xtal_latency = 12000,
0405     .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
0406     .imr_enabled = true,
0407 };
0408 
0409 /*
0410  * If the device doesn't support HE, no need to have that many buffers.
0411  * 22000 devices can split multiple frames into a single RB, so fewer are
0412  * needed; AX210 cannot (but use smaller RBs by default) - these sizes
0413  * were picked according to 8 MSDUs inside 256 A-MSDUs in an A-MPDU, with
0414  * additional overhead to account for processing time.
0415  */
0416 #define IWL_NUM_RBDS_NON_HE     512
0417 #define IWL_NUM_RBDS_22000_HE       2048
0418 #define IWL_NUM_RBDS_AX210_HE       4096
0419 
0420 /*
0421  * All JF radio modules are part of the 9000 series, but the MAC part
0422  * looks more like 22000.  That's why this device is here, but called
0423  * 9560 nevertheless.
0424  */
0425 const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg = {
0426     .fw_name_pre = IWL_QU_B_JF_B_FW_PRE,
0427     IWL_DEVICE_22500,
0428     .num_rbds = IWL_NUM_RBDS_NON_HE,
0429 };
0430 
0431 const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg = {
0432     .fw_name_pre = IWL_QU_C_JF_B_FW_PRE,
0433     IWL_DEVICE_22500,
0434     .num_rbds = IWL_NUM_RBDS_NON_HE,
0435 };
0436 
0437 const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg = {
0438     .fw_name_pre = IWL_QUZ_A_JF_B_FW_PRE,
0439     IWL_DEVICE_22500,
0440     /*
0441      * This device doesn't support receiving BlockAck with a large bitmap
0442      * so we need to restrict the size of transmitted aggregation to the
0443      * HT size; mac80211 would otherwise pick the HE max (256) by default.
0444      */
0445     .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
0446     .num_rbds = IWL_NUM_RBDS_NON_HE,
0447 };
0448 
0449 const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg = {
0450     .fw_name_pre = IWL_QNJ_B_JF_B_FW_PRE,
0451     IWL_DEVICE_22500,
0452     /*
0453      * This device doesn't support receiving BlockAck with a large bitmap
0454      * so we need to restrict the size of transmitted aggregation to the
0455      * HT size; mac80211 would otherwise pick the HE max (256) by default.
0456      */
0457     .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
0458     .num_rbds = IWL_NUM_RBDS_NON_HE,
0459 };
0460 
0461 const struct iwl_cfg_trans_params iwl_ax200_trans_cfg = {
0462     .device_family = IWL_DEVICE_FAMILY_22000,
0463     .base_params = &iwl_22000_base_params,
0464     .mq_rx_supported = true,
0465     .use_tfh = true,
0466     .rf_id = true,
0467     .gen2 = true,
0468     .bisr_workaround = 1,
0469 };
0470 
0471 const struct iwl_cfg_trans_params iwl_ma_trans_cfg = {
0472     .device_family = IWL_DEVICE_FAMILY_AX210,
0473     .base_params = &iwl_ax210_base_params,
0474     .mq_rx_supported = true,
0475     .use_tfh = true,
0476     .rf_id = true,
0477     .gen2 = true,
0478     .integrated = true,
0479     .umac_prph_offset = 0x300000
0480 };
0481 
0482 const struct iwl_cfg_trans_params iwl_bz_trans_cfg = {
0483     .device_family = IWL_DEVICE_FAMILY_BZ,
0484     .base_params = &iwl_ax210_base_params,
0485     .mq_rx_supported = true,
0486     .use_tfh = true,
0487     .rf_id = true,
0488     .gen2 = true,
0489     .integrated = true,
0490     .umac_prph_offset = 0x300000,
0491     .xtal_latency = 12000,
0492     .low_latency_xtal = true,
0493     .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
0494 };
0495 
0496 const char iwl_ax101_name[] = "Intel(R) Wi-Fi 6 AX101";
0497 const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz";
0498 const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz";
0499 const char iwl_ax203_name[] = "Intel(R) Wi-Fi 6 AX203";
0500 const char iwl_ax204_name[] = "Intel(R) Wi-Fi 6 AX204 160MHz";
0501 const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6E AX211 160MHz";
0502 const char iwl_ax221_name[] = "Intel(R) Wi-Fi 6E AX221 160MHz";
0503 const char iwl_ax231_name[] = "Intel(R) Wi-Fi 6E AX231 160MHz";
0504 const char iwl_ax411_name[] = "Intel(R) Wi-Fi 6E AX411 160MHz";
0505 const char iwl_bz_name[] = "Intel(R) TBD Bz device";
0506 
0507 const char iwl_ax200_killer_1650w_name[] =
0508     "Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)";
0509 const char iwl_ax200_killer_1650x_name[] =
0510     "Killer(R) Wi-Fi 6 AX1650x 160MHz Wireless Network Adapter (200NGW)";
0511 const char iwl_ax201_killer_1650s_name[] =
0512     "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)";
0513 const char iwl_ax201_killer_1650i_name[] =
0514     "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)";
0515 const char iwl_ax210_killer_1675w_name[] =
0516     "Killer(R) Wi-Fi 6E AX1675w 160MHz Wireless Network Adapter (210D2W)";
0517 const char iwl_ax210_killer_1675x_name[] =
0518     "Killer(R) Wi-Fi 6E AX1675x 160MHz Wireless Network Adapter (210NGW)";
0519 const char iwl_ax211_killer_1675s_name[] =
0520     "Killer(R) Wi-Fi 6E AX1675s 160MHz Wireless Network Adapter (211NGW)";
0521 const char iwl_ax211_killer_1675i_name[] =
0522     "Killer(R) Wi-Fi 6E AX1675i 160MHz Wireless Network Adapter (211NGW)";
0523 const char iwl_ax411_killer_1690s_name[] =
0524     "Killer(R) Wi-Fi 6E AX1690s 160MHz Wireless Network Adapter (411D2W)";
0525 const char iwl_ax411_killer_1690i_name[] =
0526     "Killer(R) Wi-Fi 6E AX1690i 160MHz Wireless Network Adapter (411NGW)";
0527 
0528 const struct iwl_cfg iwl_qu_b0_hr1_b0 = {
0529     .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
0530     IWL_DEVICE_22500,
0531     /*
0532      * This device doesn't support receiving BlockAck with a large bitmap
0533      * so we need to restrict the size of transmitted aggregation to the
0534      * HT size; mac80211 would otherwise pick the HE max (256) by default.
0535      */
0536     .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
0537     .tx_with_siso_diversity = true,
0538     .num_rbds = IWL_NUM_RBDS_22000_HE,
0539 };
0540 
0541 const struct iwl_cfg iwl_qu_b0_hr_b0 = {
0542     .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
0543     IWL_DEVICE_22500,
0544     /*
0545      * This device doesn't support receiving BlockAck with a large bitmap
0546      * so we need to restrict the size of transmitted aggregation to the
0547      * HT size; mac80211 would otherwise pick the HE max (256) by default.
0548      */
0549     .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
0550     .num_rbds = IWL_NUM_RBDS_22000_HE,
0551 };
0552 
0553 const struct iwl_cfg iwl_ax201_cfg_qu_hr = {
0554     .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
0555     .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
0556     IWL_DEVICE_22500,
0557     /*
0558      * This device doesn't support receiving BlockAck with a large bitmap
0559      * so we need to restrict the size of transmitted aggregation to the
0560      * HT size; mac80211 would otherwise pick the HE max (256) by default.
0561      */
0562     .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
0563     .num_rbds = IWL_NUM_RBDS_22000_HE,
0564 };
0565 
0566 const struct iwl_cfg iwl_qu_c0_hr1_b0 = {
0567     .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
0568     IWL_DEVICE_22500,
0569     /*
0570      * This device doesn't support receiving BlockAck with a large bitmap
0571      * so we need to restrict the size of transmitted aggregation to the
0572      * HT size; mac80211 would otherwise pick the HE max (256) by default.
0573      */
0574     .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
0575     .tx_with_siso_diversity = true,
0576     .num_rbds = IWL_NUM_RBDS_22000_HE,
0577 };
0578 
0579 const struct iwl_cfg iwl_qu_c0_hr_b0 = {
0580     .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
0581     IWL_DEVICE_22500,
0582     /*
0583      * This device doesn't support receiving BlockAck with a large bitmap
0584      * so we need to restrict the size of transmitted aggregation to the
0585      * HT size; mac80211 would otherwise pick the HE max (256) by default.
0586      */
0587     .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
0588     .num_rbds = IWL_NUM_RBDS_22000_HE,
0589 };
0590 
0591 const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0 = {
0592     .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
0593     .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
0594     IWL_DEVICE_22500,
0595     /*
0596      * This device doesn't support receiving BlockAck with a large bitmap
0597      * so we need to restrict the size of transmitted aggregation to the
0598      * HT size; mac80211 would otherwise pick the HE max (256) by default.
0599      */
0600     .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
0601     .num_rbds = IWL_NUM_RBDS_22000_HE,
0602 };
0603 
0604 const struct iwl_cfg iwl_quz_a0_hr1_b0 = {
0605     .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
0606     IWL_DEVICE_22500,
0607     /*
0608      * This device doesn't support receiving BlockAck with a large bitmap
0609      * so we need to restrict the size of transmitted aggregation to the
0610      * HT size; mac80211 would otherwise pick the HE max (256) by default.
0611      */
0612     .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
0613     .tx_with_siso_diversity = true,
0614     .num_rbds = IWL_NUM_RBDS_22000_HE,
0615 };
0616 
0617 const struct iwl_cfg iwl_ax201_cfg_quz_hr = {
0618     .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
0619     .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
0620     IWL_DEVICE_22500,
0621     /*
0622          * This device doesn't support receiving BlockAck with a large bitmap
0623          * so we need to restrict the size of transmitted aggregation to the
0624          * HT size; mac80211 would otherwise pick the HE max (256) by default.
0625          */
0626     .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
0627     .num_rbds = IWL_NUM_RBDS_22000_HE,
0628 };
0629 
0630 const struct iwl_cfg iwl_ax1650s_cfg_quz_hr = {
0631     .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)",
0632     .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
0633     IWL_DEVICE_22500,
0634     /*
0635          * This device doesn't support receiving BlockAck with a large bitmap
0636          * so we need to restrict the size of transmitted aggregation to the
0637          * HT size; mac80211 would otherwise pick the HE max (256) by default.
0638          */
0639     .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
0640     .num_rbds = IWL_NUM_RBDS_22000_HE,
0641 };
0642 
0643 const struct iwl_cfg iwl_ax1650i_cfg_quz_hr = {
0644     .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)",
0645     .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
0646     IWL_DEVICE_22500,
0647     /*
0648          * This device doesn't support receiving BlockAck with a large bitmap
0649          * so we need to restrict the size of transmitted aggregation to the
0650          * HT size; mac80211 would otherwise pick the HE max (256) by default.
0651          */
0652     .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
0653     .num_rbds = IWL_NUM_RBDS_22000_HE,
0654 };
0655 
0656 const struct iwl_cfg iwl_ax200_cfg_cc = {
0657     .fw_name_pre = IWL_CC_A_FW_PRE,
0658     IWL_DEVICE_22500,
0659     /*
0660      * This device doesn't support receiving BlockAck with a large bitmap
0661      * so we need to restrict the size of transmitted aggregation to the
0662      * HT size; mac80211 would otherwise pick the HE max (256) by default.
0663      */
0664     .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
0665     .num_rbds = IWL_NUM_RBDS_22000_HE,
0666 };
0667 
0668 const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0 = {
0669     .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)",
0670     .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
0671     IWL_DEVICE_22500,
0672     /*
0673      * This device doesn't support receiving BlockAck with a large bitmap
0674      * so we need to restrict the size of transmitted aggregation to the
0675      * HT size; mac80211 would otherwise pick the HE max (256) by default.
0676      */
0677     .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
0678     .num_rbds = IWL_NUM_RBDS_22000_HE,
0679 };
0680 
0681 const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0 = {
0682     .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)",
0683     .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
0684     IWL_DEVICE_22500,
0685     /*
0686      * This device doesn't support receiving BlockAck with a large bitmap
0687      * so we need to restrict the size of transmitted aggregation to the
0688      * HT size; mac80211 would otherwise pick the HE max (256) by default.
0689      */
0690     .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
0691     .num_rbds = IWL_NUM_RBDS_22000_HE,
0692 };
0693 
0694 const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0 = {
0695     .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)",
0696     .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
0697     IWL_DEVICE_22500,
0698     /*
0699      * This device doesn't support receiving BlockAck with a large bitmap
0700      * so we need to restrict the size of transmitted aggregation to the
0701      * HT size; mac80211 would otherwise pick the HE max (256) by default.
0702      */
0703     .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
0704     .num_rbds = IWL_NUM_RBDS_22000_HE,
0705 };
0706 
0707 const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0 = {
0708     .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)",
0709     .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
0710     IWL_DEVICE_22500,
0711     /*
0712      * This device doesn't support receiving BlockAck with a large bitmap
0713      * so we need to restrict the size of transmitted aggregation to the
0714      * HT size; mac80211 would otherwise pick the HE max (256) by default.
0715      */
0716     .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
0717     .num_rbds = IWL_NUM_RBDS_22000_HE,
0718 };
0719 
0720 const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg = {
0721     .fw_name_pre = IWL_QNJ_B_HR_B_FW_PRE,
0722     IWL_DEVICE_22500,
0723     /*
0724      * This device doesn't support receiving BlockAck with a large bitmap
0725      * so we need to restrict the size of transmitted aggregation to the
0726      * HT size; mac80211 would otherwise pick the HE max (256) by default.
0727      */
0728     .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
0729     .num_rbds = IWL_NUM_RBDS_22000_HE,
0730 };
0731 
0732 const struct iwl_cfg iwlax210_2ax_cfg_so_jf_b0 = {
0733     .name = "Intel(R) Wireless-AC 9560 160MHz",
0734     .fw_name_pre = IWL_SO_A_JF_B_FW_PRE,
0735     IWL_DEVICE_AX210,
0736     .num_rbds = IWL_NUM_RBDS_NON_HE,
0737 };
0738 
0739 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0 = {
0740     .name = iwl_ax211_name,
0741     .fw_name_pre = IWL_SO_A_GF_A_FW_PRE,
0742     .uhb_supported = true,
0743     IWL_DEVICE_AX210,
0744     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0745 };
0746 
0747 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long = {
0748     .name = iwl_ax211_name,
0749     .fw_name_pre = IWL_SO_A_GF_A_FW_PRE,
0750     .uhb_supported = true,
0751     IWL_DEVICE_AX210,
0752     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0753     .trans.xtal_latency = 12000,
0754     .trans.low_latency_xtal = true,
0755 };
0756 
0757 const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0 = {
0758     .name = "Intel(R) Wi-Fi 6 AX210 160MHz",
0759     .fw_name_pre = IWL_TY_A_GF_A_FW_PRE,
0760     .uhb_supported = true,
0761     IWL_DEVICE_AX210,
0762     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0763 };
0764 
0765 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0 = {
0766     .name = iwl_ax411_name,
0767     .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE,
0768     .uhb_supported = true,
0769     IWL_DEVICE_AX210,
0770     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0771 };
0772 
0773 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long = {
0774     .name = iwl_ax411_name,
0775     .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE,
0776     .uhb_supported = true,
0777     IWL_DEVICE_AX210,
0778     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0779     .trans.xtal_latency = 12000,
0780     .trans.low_latency_xtal = true,
0781 };
0782 
0783 const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0 = {
0784     .name = iwl_ax411_name,
0785     .fw_name_pre = IWL_SNJ_A_GF4_A_FW_PRE,
0786     .uhb_supported = true,
0787     IWL_DEVICE_AX210,
0788     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0789 };
0790 
0791 const struct iwl_cfg iwlax211_cfg_snj_gf_a0 = {
0792     .name = iwl_ax211_name,
0793     .fw_name_pre = IWL_SNJ_A_GF_A_FW_PRE,
0794     .uhb_supported = true,
0795     IWL_DEVICE_AX210,
0796     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0797 };
0798 
0799 const struct iwl_cfg iwl_cfg_snj_hr_b0 = {
0800     .fw_name_pre = IWL_SNJ_A_HR_B_FW_PRE,
0801     .uhb_supported = true,
0802     IWL_DEVICE_AX210,
0803     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0804 };
0805 
0806 const struct iwl_cfg iwl_cfg_snj_a0_jf_b0 = {
0807     .fw_name_pre = IWL_SNJ_A_JF_B_FW_PRE,
0808     .uhb_supported = true,
0809     IWL_DEVICE_AX210,
0810     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0811 };
0812 
0813 const struct iwl_cfg iwl_cfg_ma_a0_hr_b0 = {
0814     .fw_name_pre = IWL_MA_A_HR_B_FW_PRE,
0815     .uhb_supported = true,
0816     IWL_DEVICE_AX210,
0817     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0818 };
0819 
0820 const struct iwl_cfg iwl_cfg_ma_a0_gf_a0 = {
0821     .fw_name_pre = IWL_MA_A_GF_A_FW_PRE,
0822     .uhb_supported = true,
0823     IWL_DEVICE_AX210,
0824     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0825 };
0826 
0827 const struct iwl_cfg iwl_cfg_ma_a0_gf4_a0 = {
0828     .fw_name_pre = IWL_MA_A_GF4_A_FW_PRE,
0829     .uhb_supported = true,
0830     IWL_DEVICE_AX210,
0831     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0832 };
0833 
0834 const struct iwl_cfg iwl_cfg_ma_a0_mr_a0 = {
0835     .fw_name_pre = IWL_MA_A_MR_A_FW_PRE,
0836     .uhb_supported = true,
0837     IWL_DEVICE_AX210,
0838     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0839 };
0840 
0841 const struct iwl_cfg iwl_cfg_ma_a0_ms_a0 = {
0842     .fw_name_pre = IWL_MA_A_MR_A_FW_PRE,
0843     .uhb_supported = false,
0844     IWL_DEVICE_AX210,
0845     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0846 };
0847 
0848 const struct iwl_cfg iwl_cfg_so_a0_ms_a0 = {
0849     .fw_name_pre = IWL_SO_A_MR_A_FW_PRE,
0850     .uhb_supported = false,
0851     IWL_DEVICE_AX210,
0852     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0853 };
0854 
0855 const struct iwl_cfg iwl_cfg_ma_a0_fm_a0 = {
0856     .fw_name_pre = IWL_MA_A_FM_A_FW_PRE,
0857     .uhb_supported = true,
0858     IWL_DEVICE_AX210,
0859     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0860 };
0861 
0862 const struct iwl_cfg iwl_cfg_snj_a0_mr_a0 = {
0863     .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE,
0864     .uhb_supported = true,
0865     IWL_DEVICE_AX210,
0866     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0867 };
0868 
0869 const struct iwl_cfg iwl_cfg_snj_a0_ms_a0 = {
0870     .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE,
0871     .uhb_supported = false,
0872     IWL_DEVICE_AX210,
0873     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0874 };
0875 
0876 const struct iwl_cfg iwl_cfg_so_a0_hr_a0 = {
0877     .fw_name_pre = IWL_SO_A_HR_B_FW_PRE,
0878     IWL_DEVICE_AX210,
0879     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0880 };
0881 
0882 const struct iwl_cfg iwl_cfg_quz_a0_hr_b0 = {
0883     .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
0884     IWL_DEVICE_22500,
0885     /*
0886      * This device doesn't support receiving BlockAck with a large bitmap
0887      * so we need to restrict the size of transmitted aggregation to the
0888      * HT size; mac80211 would otherwise pick the HE max (256) by default.
0889      */
0890     .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
0891     .num_rbds = IWL_NUM_RBDS_22000_HE,
0892 };
0893 
0894 const struct iwl_cfg iwl_cfg_bz_a0_hr_b0 = {
0895     .fw_name_pre = IWL_BZ_A_HR_B_FW_PRE,
0896     .uhb_supported = true,
0897     IWL_DEVICE_BZ,
0898     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0899 };
0900 
0901 const struct iwl_cfg iwl_cfg_bz_a0_gf_a0 = {
0902     .fw_name_pre = IWL_BZ_A_GF_A_FW_PRE,
0903     .uhb_supported = true,
0904     IWL_DEVICE_BZ,
0905     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0906 };
0907 
0908 const struct iwl_cfg iwl_cfg_bz_a0_gf4_a0 = {
0909     .fw_name_pre = IWL_BZ_A_GF4_A_FW_PRE,
0910     .uhb_supported = true,
0911     IWL_DEVICE_BZ,
0912     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0913 };
0914 
0915 const struct iwl_cfg iwl_cfg_bz_a0_mr_a0 = {
0916     .fw_name_pre = IWL_BZ_A_MR_A_FW_PRE,
0917     .uhb_supported = true,
0918     IWL_DEVICE_BZ,
0919     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0920 };
0921 
0922 const struct iwl_cfg iwl_cfg_bz_a0_fm_a0 = {
0923     .fw_name_pre = IWL_BZ_A_FM_A_FW_PRE,
0924     .uhb_supported = true,
0925     IWL_DEVICE_BZ,
0926     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0927 };
0928 
0929 const struct iwl_cfg iwl_cfg_gl_a0_fm_a0 = {
0930     .fw_name_pre = IWL_GL_A_FM_A_FW_PRE,
0931     .uhb_supported = true,
0932     IWL_DEVICE_BZ,
0933     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0934 };
0935 
0936 const struct iwl_cfg iwl_cfg_bz_z0_gf_a0 = {
0937     .fw_name_pre = IWL_BZ_Z_GF_A_FW_PRE,
0938     .uhb_supported = true,
0939     IWL_DEVICE_BZ,
0940     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0941 };
0942 
0943 const struct iwl_cfg iwl_cfg_bnj_a0_fm_a0 = {
0944     .fw_name_pre = IWL_BNJ_A_FM_A_FW_PRE,
0945     .uhb_supported = true,
0946     IWL_DEVICE_BZ,
0947     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0948 };
0949 
0950 const struct iwl_cfg iwl_cfg_bnj_a0_fm4_a0 = {
0951     .fw_name_pre = IWL_BNJ_A_FM4_A_FW_PRE,
0952     .uhb_supported = true,
0953     IWL_DEVICE_BZ,
0954     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0955 };
0956 
0957 const struct iwl_cfg iwl_cfg_bnj_a0_gf_a0 = {
0958     .fw_name_pre = IWL_BNJ_A_GF_A_FW_PRE,
0959     .uhb_supported = true,
0960     IWL_DEVICE_BZ,
0961     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0962 };
0963 
0964 const struct iwl_cfg iwl_cfg_bnj_a0_gf4_a0 = {
0965     .fw_name_pre = IWL_BNJ_A_GF4_A_FW_PRE,
0966     .uhb_supported = true,
0967     IWL_DEVICE_BZ,
0968     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0969 };
0970 
0971 const struct iwl_cfg iwl_cfg_bnj_a0_hr_b0 = {
0972     .fw_name_pre = IWL_BNJ_A_HR_B_FW_PRE,
0973     .uhb_supported = true,
0974     IWL_DEVICE_BZ,
0975     .num_rbds = IWL_NUM_RBDS_AX210_HE,
0976 };
0977 MODULE_FIRMWARE(IWL_QU_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
0978 MODULE_FIRMWARE(IWL_QNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
0979 MODULE_FIRMWARE(IWL_QU_C_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
0980 MODULE_FIRMWARE(IWL_QU_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
0981 MODULE_FIRMWARE(IWL_QUZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
0982 MODULE_FIRMWARE(IWL_QUZ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
0983 MODULE_FIRMWARE(IWL_QNJ_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
0984 MODULE_FIRMWARE(IWL_CC_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
0985 MODULE_FIRMWARE(IWL_SO_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
0986 MODULE_FIRMWARE(IWL_SO_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
0987 MODULE_FIRMWARE(IWL_SO_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
0988 MODULE_FIRMWARE(IWL_TY_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
0989 MODULE_FIRMWARE(IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
0990 MODULE_FIRMWARE(IWL_SNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
0991 MODULE_FIRMWARE(IWL_SNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
0992 MODULE_FIRMWARE(IWL_SNJ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
0993 MODULE_FIRMWARE(IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
0994 MODULE_FIRMWARE(IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
0995 MODULE_FIRMWARE(IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
0996 MODULE_FIRMWARE(IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
0997 MODULE_FIRMWARE(IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
0998 MODULE_FIRMWARE(IWL_SNJ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
0999 MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1000 MODULE_FIRMWARE(IWL_BZ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1001 MODULE_FIRMWARE(IWL_BZ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1002 MODULE_FIRMWARE(IWL_BZ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1003 MODULE_FIRMWARE(IWL_BZ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1004 MODULE_FIRMWARE(IWL_GL_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1005 MODULE_FIRMWARE(IWL_BNJ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1006 MODULE_FIRMWARE(IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1007 MODULE_FIRMWARE(IWL_BNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1008 MODULE_FIRMWARE(IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1009 MODULE_FIRMWARE(IWL_BNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));