intel/iwlegacy/csr.h

0001 /******************************************************************************
0002  *
0003  * This file is provided under a dual BSD/GPLv2 license.  When using or
0004  * redistributing this file, you may do so under either license.
0005  *
0006  * GPL LICENSE SUMMARY
0007  *
0008  * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
0009  *
0010  * This program is free software; you can redistribute it and/or modify
0011  * it under the terms of version 2 of the GNU General Public License as
0012  * published by the Free Software Foundation.
0013  *
0014  * This program is distributed in the hope that it will be useful, but
0015  * WITHOUT ANY WARRANTY; without even the implied warranty of
0016  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
0017  * General Public License for more details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this program; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
0022  * USA
0023  *
0024  * The full GNU General Public License is included in this distribution
0025  * in the file called LICENSE.GPL.
0026  *
0027  * Contact Information:
0028  *  Intel Linux Wireless <ilw@linux.intel.com>
0029  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
0030  *
0031  * BSD LICENSE
0032  *
0033  * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
0034  * All rights reserved.
0035  *
0036  * Redistribution and use in source and binary forms, with or without
0037  * modification, are permitted provided that the following conditions
0038  * are met:
0039  *
0040  *  * Redistributions of source code must retain the above copyright
0041  *    notice, this list of conditions and the following disclaimer.
0042  *  * Redistributions in binary form must reproduce the above copyright
0043  *    notice, this list of conditions and the following disclaimer in
0044  *    the documentation and/or other materials provided with the
0045  *    distribution.
0046  *  * Neither the name Intel Corporation nor the names of its
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0048  *    from this software without specific prior written permission.
0049  *
0050  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0051  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0052  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0053  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0054  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0055  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0056  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0057  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0058  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0059  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0060  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0061  *
0062  *****************************************************************************/
0063 #ifndef __il_csr_h__
0064 #define __il_csr_h__
0065 /*
0066  * CSR (control and status registers)
0067  *
0068  * CSR registers are mapped directly into PCI bus space, and are accessible
0069  * whenever platform supplies power to device, even when device is in
0070  * low power states due to driver-invoked device resets
0071  * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
0072  *
0073  * Use _il_wr() and _il_rd() family to access these registers;
0074  * these provide simple PCI bus access, without waking up the MAC.
0075  * Do not use il_wr() family for these registers;
0076  * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
0077  * The MAC (uCode processor, etc.) does not need to be powered up for accessing
0078  * the CSR registers.
0079  *
0080  * NOTE:  Device does need to be awake in order to read this memory
0081  *        via CSR_EEPROM register
0082  */
0083 #define CSR_BASE    (0x000)
0084
0085 #define CSR_HW_IF_CONFIG_REG    (CSR_BASE+0x000)    /* hardware interface config */
0086 #define CSR_INT_COALESCING      (CSR_BASE+0x004)    /* accum ints, 32-usec units */
0087 #define CSR_INT                 (CSR_BASE+0x008)    /* host interrupt status/ack */
0088 #define CSR_INT_MASK            (CSR_BASE+0x00c)    /* host interrupt enable */
0089 #define CSR_FH_INT_STATUS       (CSR_BASE+0x010)    /* busmaster int status/ack */
0090 #define CSR_GPIO_IN             (CSR_BASE+0x018)    /* read external chip pins */
0091 #define CSR_RESET               (CSR_BASE+0x020)    /* busmaster enable, NMI, etc */
0092 #define CSR_GP_CNTRL            (CSR_BASE+0x024)
0093
0094 /* 2nd byte of CSR_INT_COALESCING, not accessible via _il_wr()! */
0095 #define CSR_INT_PERIODIC_REG    (CSR_BASE+0x005)
0096
0097 /*
0098  * Hardware revision info
0099  * Bit fields:
0100  * 31-8:  Reserved
0101  *  7-4:  Type of device:  see CSR_HW_REV_TYPE_xxx definitions
0102  *  3-2:  Revision step:  0 = A, 1 = B, 2 = C, 3 = D
0103  *  1-0:  "Dash" (-) value, as in A-1, etc.
0104  *
0105  * NOTE:  Revision step affects calculation of CCK txpower for 4965.
0106  * NOTE:  See also CSR_HW_REV_WA_REG (work-around for bug in 4965).
0107  */
0108 #define CSR_HW_REV              (CSR_BASE+0x028)
0109
0110 /*
0111  * EEPROM memory reads
0112  *
0113  * NOTE:  Device must be awake, initialized via apm_ops.init(),
0114  *        in order to read.
0115  */
0116 #define CSR_EEPROM_REG          (CSR_BASE+0x02c)
0117 #define CSR_EEPROM_GP           (CSR_BASE+0x030)
0118
0119 #define CSR_GIO_REG     (CSR_BASE+0x03C)
0120 #define CSR_GP_UCODE_REG    (CSR_BASE+0x048)
0121 #define CSR_GP_DRIVER_REG   (CSR_BASE+0x050)
0122
0123 /*
0124  * UCODE-DRIVER GP (general purpose) mailbox registers.
0125  * SET/CLR registers set/clear bit(s) if "1" is written.
0126  */
0127 #define CSR_UCODE_DRV_GP1       (CSR_BASE+0x054)
0128 #define CSR_UCODE_DRV_GP1_SET   (CSR_BASE+0x058)
0129 #define CSR_UCODE_DRV_GP1_CLR   (CSR_BASE+0x05c)
0130 #define CSR_UCODE_DRV_GP2       (CSR_BASE+0x060)
0131
0132 #define CSR_LED_REG             (CSR_BASE+0x094)
0133 #define CSR_DRAM_INT_TBL_REG    (CSR_BASE+0x0A0)
0134
0135 /* GIO Chicken Bits (PCI Express bus link power management) */
0136 #define CSR_GIO_CHICKEN_BITS    (CSR_BASE+0x100)
0137
0138 /* Analog phase-lock-loop configuration  */
0139 #define CSR_ANA_PLL_CFG         (CSR_BASE+0x20c)
0140
0141 /*
0142  * CSR Hardware Revision Workaround Register.  Indicates hardware rev;
0143  * "step" determines CCK backoff for txpower calculation.  Used for 4965 only.
0144  * See also CSR_HW_REV register.
0145  * Bit fields:
0146  *  3-2:  0 = A, 1 = B, 2 = C, 3 = D step
0147  *  1-0:  "Dash" (-) value, as in C-1, etc.
0148  */
0149 #define CSR_HW_REV_WA_REG       (CSR_BASE+0x22C)
0150
0151 #define CSR_DBG_HPET_MEM_REG        (CSR_BASE+0x240)
0152 #define CSR_DBG_LINK_PWR_MGMT_REG   (CSR_BASE+0x250)
0153
0154 /* Bits for CSR_HW_IF_CONFIG_REG */
0155 #define CSR49_HW_IF_CONFIG_REG_BIT_4965_R   (0x00000010)
0156 #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER  (0x00000C00)
0157 #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI     (0x00000100)
0158 #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI   (0x00000200)
0159
0160 #define CSR39_HW_IF_CONFIG_REG_BIT_3945_MB         (0x00000100)
0161 #define CSR39_HW_IF_CONFIG_REG_BIT_3945_MM         (0x00000200)
0162 #define CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC            (0x00000400)
0163 #define CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE         (0x00000800)
0164 #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A    (0x00000000)
0165 #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B    (0x00001000)
0166
0167 #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A   (0x00080000)
0168 #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
0169 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY  (0x00400000)    /* PCI_OWN_SEM */
0170 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000)  /* ME_OWN */
0171 #define CSR_HW_IF_CONFIG_REG_PREPARE          (0x08000000)  /* WAKE_ME */
0172
0173 #define CSR_INT_PERIODIC_DIS            (0x00)  /* disable periodic int */
0174 #define CSR_INT_PERIODIC_ENA            (0xFF)  /* 255*32 usec ~ 8 msec */
0175
0176 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
0177  * acknowledged (reset) by host writing "1" to flagged bits. */
0178 #define CSR_INT_BIT_FH_RX        (1 << 31)  /* Rx DMA, cmd responses, FH_INT[17:16] */
0179 #define CSR_INT_BIT_HW_ERR       (1 << 29)  /* DMA hardware error FH_INT[31] */
0180 #define CSR_INT_BIT_RX_PERIODIC  (1 << 28)  /* Rx periodic */
0181 #define CSR_INT_BIT_FH_TX        (1 << 27)  /* Tx DMA FH_INT[1:0] */
0182 #define CSR_INT_BIT_SCD          (1 << 26)  /* TXQ pointer advanced */
0183 #define CSR_INT_BIT_SW_ERR       (1 << 25)  /* uCode error */
0184 #define CSR_INT_BIT_RF_KILL      (1 << 7)   /* HW RFKILL switch GP_CNTRL[27] toggled */
0185 #define CSR_INT_BIT_CT_KILL      (1 << 6)   /* Critical temp (chip too hot) rfkill */
0186 #define CSR_INT_BIT_SW_RX        (1 << 3)   /* Rx, command responses, 3945 */
0187 #define CSR_INT_BIT_WAKEUP       (1 << 1)   /* NIC controller waking up (pwr mgmt) */
0188 #define CSR_INT_BIT_ALIVE        (1 << 0)   /* uCode interrupts once it initializes */
0189
0190 #define CSR_INI_SET_MASK    (CSR_INT_BIT_FH_RX   | \
0191                  CSR_INT_BIT_HW_ERR  | \
0192                  CSR_INT_BIT_FH_TX   | \
0193                  CSR_INT_BIT_SW_ERR  | \
0194                  CSR_INT_BIT_RF_KILL | \
0195                  CSR_INT_BIT_SW_RX   | \
0196                  CSR_INT_BIT_WAKEUP  | \
0197                  CSR_INT_BIT_ALIVE)
0198
0199 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
0200 #define CSR_FH_INT_BIT_ERR       (1 << 31)  /* Error */
0201 #define CSR_FH_INT_BIT_HI_PRIOR  (1 << 30)  /* High priority Rx, bypass coalescing */
0202 #define CSR39_FH_INT_BIT_RX_CHNL2  (1 << 18)    /* Rx channel 2 (3945 only) */
0203 #define CSR_FH_INT_BIT_RX_CHNL1  (1 << 17)  /* Rx channel 1 */
0204 #define CSR_FH_INT_BIT_RX_CHNL0  (1 << 16)  /* Rx channel 0 */
0205 #define CSR39_FH_INT_BIT_TX_CHNL6  (1 << 6) /* Tx channel 6 (3945 only) */
0206 #define CSR_FH_INT_BIT_TX_CHNL1  (1 << 1)   /* Tx channel 1 */
0207 #define CSR_FH_INT_BIT_TX_CHNL0  (1 << 0)   /* Tx channel 0 */
0208
0209 #define CSR39_FH_INT_RX_MASK    (CSR_FH_INT_BIT_HI_PRIOR | \
0210                  CSR39_FH_INT_BIT_RX_CHNL2 | \
0211                  CSR_FH_INT_BIT_RX_CHNL1 | \
0212                  CSR_FH_INT_BIT_RX_CHNL0)
0213
0214 #define CSR39_FH_INT_TX_MASK    (CSR39_FH_INT_BIT_TX_CHNL6 | \
0215                  CSR_FH_INT_BIT_TX_CHNL1 | \
0216                  CSR_FH_INT_BIT_TX_CHNL0)
0217
0218 #define CSR49_FH_INT_RX_MASK    (CSR_FH_INT_BIT_HI_PRIOR | \
0219                  CSR_FH_INT_BIT_RX_CHNL1 | \
0220                  CSR_FH_INT_BIT_RX_CHNL0)
0221
0222 #define CSR49_FH_INT_TX_MASK    (CSR_FH_INT_BIT_TX_CHNL1 | \
0223                  CSR_FH_INT_BIT_TX_CHNL0)
0224
0225 /* GPIO */
0226 #define CSR_GPIO_IN_BIT_AUX_POWER                   (0x00000200)
0227 #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC                (0x00000000)
0228 #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC               (0x00000200)
0229
0230 /* RESET */
0231 #define CSR_RESET_REG_FLAG_NEVO_RESET                (0x00000001)
0232 #define CSR_RESET_REG_FLAG_FORCE_NMI                 (0x00000002)
0233 #define CSR_RESET_REG_FLAG_SW_RESET                  (0x00000080)
0234 #define CSR_RESET_REG_FLAG_MASTER_DISABLED           (0x00000100)
0235 #define CSR_RESET_REG_FLAG_STOP_MASTER               (0x00000200)
0236 #define CSR_RESET_LINK_PWR_MGMT_DISABLED             (0x80000000)
0237
0238 /*
0239  * GP (general purpose) CONTROL REGISTER
0240  * Bit fields:
0241  *    27:  HW_RF_KILL_SW
0242  *         Indicates state of (platform's) hardware RF-Kill switch
0243  * 26-24:  POWER_SAVE_TYPE
0244  *         Indicates current power-saving mode:
0245  *         000 -- No power saving
0246  *         001 -- MAC power-down
0247  *         010 -- PHY (radio) power-down
0248  *         011 -- Error
0249  *   9-6:  SYS_CONFIG
0250  *         Indicates current system configuration, reflecting pins on chip
0251  *         as forced high/low by device circuit board.
0252  *     4:  GOING_TO_SLEEP
0253  *         Indicates MAC is entering a power-saving sleep power-down.
0254  *         Not a good time to access device-internal resources.
0255  *     3:  MAC_ACCESS_REQ
0256  *         Host sets this to request and maintain MAC wakeup, to allow host
0257  *         access to device-internal resources.  Host must wait for
0258  *         MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
0259  *         device registers.
0260  *     2:  INIT_DONE
0261  *         Host sets this to put device into fully operational D0 power mode.
0262  *         Host resets this after SW_RESET to put device into low power mode.
0263  *     0:  MAC_CLOCK_READY
0264  *         Indicates MAC (ucode processor, etc.) is powered up and can run.
0265  *         Internal resources are accessible.
0266  *         NOTE:  This does not indicate that the processor is actually running.
0267  *         NOTE:  This does not indicate that 4965 or 3945 has completed
0268  *                init or post-power-down restore of internal SRAM memory.
0269  *                Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
0270  *                SRAM is restored and uCode is in normal operation mode.
0271  *                Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
0272  *                do not need to save/restore it.
0273  *         NOTE:  After device reset, this bit remains "0" until host sets
0274  *                INIT_DONE
0275  */
0276 #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY        (0x00000001)
0277 #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE              (0x00000004)
0278 #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ         (0x00000008)
0279 #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP         (0x00000010)
0280
0281 #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN           (0x00000001)
0282
0283 #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE         (0x07000000)
0284 #define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE         (0x04000000)
0285 #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW          (0x08000000)
0286
0287 /* EEPROM REG */
0288 #define CSR_EEPROM_REG_READ_VALID_MSK   (0x00000001)
0289 #define CSR_EEPROM_REG_BIT_CMD      (0x00000002)
0290 #define CSR_EEPROM_REG_MSK_ADDR     (0x0000FFFC)
0291 #define CSR_EEPROM_REG_MSK_DATA     (0xFFFF0000)
0292
0293 /* EEPROM GP */
0294 #define CSR_EEPROM_GP_VALID_MSK     (0x00000007)    /* signature */
0295 #define CSR_EEPROM_GP_IF_OWNER_MSK  (0x00000180)
0296 #define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K     (0x00000002)
0297 #define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K     (0x00000004)
0298
0299 /* GP REG */
0300 #define CSR_GP_REG_POWER_SAVE_STATUS_MSK            (0x03000000)    /* bit 24/25 */
0301 #define CSR_GP_REG_NO_POWER_SAVE            (0x00000000)
0302 #define CSR_GP_REG_MAC_POWER_SAVE           (0x01000000)
0303 #define CSR_GP_REG_PHY_POWER_SAVE           (0x02000000)
0304 #define CSR_GP_REG_POWER_SAVE_ERROR         (0x03000000)
0305
0306 /* CSR GIO */
0307 #define CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)
0308
0309 /*
0310  * UCODE-DRIVER GP (general purpose) mailbox register 1
0311  * Host driver and uCode write and/or read this register to communicate with
0312  * each other.
0313  * Bit fields:
0314  *     4:  UCODE_DISABLE
0315  *         Host sets this to request permanent halt of uCode, same as
0316  *         sending CARD_STATE command with "halt" bit set.
0317  *     3:  CT_KILL_EXIT
0318  *         Host sets this to request exit from CT_KILL state, i.e. host thinks
0319  *         device temperature is low enough to continue normal operation.
0320  *     2:  CMD_BLOCKED
0321  *         Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
0322  *         to release uCode to clear all Tx and command queues, enter
0323  *         unassociated mode, and power down.
0324  *         NOTE:  Some devices also use HBUS_TARG_MBX_C register for this bit.
0325  *     1:  SW_BIT_RFKILL
0326  *         Host sets this when issuing CARD_STATE command to request
0327  *         device sleep.
0328  *     0:  MAC_SLEEP
0329  *         uCode sets this when preparing a power-saving power-down.
0330  *         uCode resets this when power-up is complete and SRAM is sane.
0331  *         NOTE:  3945/4965 saves internal SRAM data to host when powering down,
0332  *                and must restore this data after powering back up.
0333  *                MAC_SLEEP is the best indication that restore is complete.
0334  *                Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
0335  *                do not need to save/restore it.
0336  */
0337 #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP             (0x00000001)
0338 #define CSR_UCODE_SW_BIT_RFKILL                     (0x00000002)
0339 #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED           (0x00000004)
0340 #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT      (0x00000008)
0341
0342 /* GIO Chicken Bits (PCI Express bus link power management) */
0343 #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX  (0x00800000)
0344 #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER  (0x20000000)
0345
0346 /* LED */
0347 #define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
0348 #define CSR_LED_REG_TRUN_ON (0x78)
0349 #define CSR_LED_REG_TRUN_OFF (0x38)
0350
0351 /* ANA_PLL */
0352 #define CSR39_ANA_PLL_CFG_VAL        (0x01000000)
0353
0354 /* HPET MEM debug */
0355 #define CSR_DBG_HPET_MEM_REG_VAL    (0xFFFF0000)
0356
0357 /* DRAM INT TBL */
0358 #define CSR_DRAM_INT_TBL_ENABLE     (1 << 31)
0359 #define CSR_DRAM_INIT_TBL_WRAP_CHECK    (1 << 27)
0360
0361 /*
0362  * HBUS (Host-side Bus)
0363  *
0364  * HBUS registers are mapped directly into PCI bus space, but are used
0365  * to indirectly access device's internal memory or registers that
0366  * may be powered-down.
0367  *
0368  * Use il_wr()/il_rd() family
0369  * for these registers;
0370  * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
0371  * to make sure the MAC (uCode processor, etc.) is powered up for accessing
0372  * internal resources.
0373  *
0374  * Do not use _il_wr()/_il_rd() family to access these registers;
0375  * these provide only simple PCI bus access, without waking up the MAC.
0376  */
0377 #define HBUS_BASE   (0x400)
0378
0379 /*
0380  * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
0381  * structures, error log, event log, verifying uCode load).
0382  * First write to address register, then read from or write to data register
0383  * to complete the job.  Once the address register is set up, accesses to
0384  * data registers auto-increment the address by one dword.
0385  * Bit usage for address registers (read or write):
0386  *  0-31:  memory address within device
0387  */
0388 #define HBUS_TARG_MEM_RADDR     (HBUS_BASE+0x00c)
0389 #define HBUS_TARG_MEM_WADDR     (HBUS_BASE+0x010)
0390 #define HBUS_TARG_MEM_WDAT      (HBUS_BASE+0x018)
0391 #define HBUS_TARG_MEM_RDAT      (HBUS_BASE+0x01c)
0392
0393 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
0394 #define HBUS_TARG_MBX_C         (HBUS_BASE+0x030)
0395 #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED         (0x00000004)
0396
0397 /*
0398  * Registers for accessing device's internal peripheral registers
0399  * (e.g. SCD, BSM, etc.).  First write to address register,
0400  * then read from or write to data register to complete the job.
0401  * Bit usage for address registers (read or write):
0402  *  0-15:  register address (offset) within device
0403  * 24-25:  (# bytes - 1) to read or write (e.g. 3 for dword)
0404  */
0405 #define HBUS_TARG_PRPH_WADDR    (HBUS_BASE+0x044)
0406 #define HBUS_TARG_PRPH_RADDR    (HBUS_BASE+0x048)
0407 #define HBUS_TARG_PRPH_WDAT     (HBUS_BASE+0x04c)
0408 #define HBUS_TARG_PRPH_RDAT     (HBUS_BASE+0x050)
0409
0410 /*
0411  * Per-Tx-queue write pointer (idx, really!)
0412  * Indicates idx to next TFD that driver will fill (1 past latest filled).
0413  * Bit usage:
0414  *  0-7:  queue write idx
0415  * 11-8:  queue selector
0416  */
0417 #define HBUS_TARG_WRPTR         (HBUS_BASE+0x060)
0418
0419 #endif /* !__il_csr_h__ */