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0001 /* SPDX-License-Identifier: GPL-2.0-only */ 0002 /****************************************************************************** 0003 * 0004 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 0005 * 0006 * Contact Information: 0007 * Intel Linux Wireless <ilw@linux.intel.com> 0008 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 0009 * 0010 *****************************************************************************/ 0011 0012 #ifndef __il_4965_h__ 0013 #define __il_4965_h__ 0014 0015 struct il_rx_queue; 0016 struct il_rx_buf; 0017 struct il_rx_pkt; 0018 struct il_tx_queue; 0019 struct il_rxon_context; 0020 0021 /* configuration for the _4965 devices */ 0022 extern struct il_cfg il4965_cfg; 0023 extern const struct il_ops il4965_ops; 0024 0025 extern struct il_mod_params il4965_mod_params; 0026 0027 /* tx queue */ 0028 void il4965_free_tfds_in_queue(struct il_priv *il, int sta_id, int tid, 0029 int freed); 0030 0031 /* RXON */ 0032 void il4965_set_rxon_chain(struct il_priv *il); 0033 0034 /* uCode */ 0035 int il4965_verify_ucode(struct il_priv *il); 0036 0037 /* lib */ 0038 void il4965_check_abort_status(struct il_priv *il, u8 frame_count, u32 status); 0039 0040 void il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq); 0041 int il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq); 0042 int il4965_hw_nic_init(struct il_priv *il); 0043 int il4965_dump_fh(struct il_priv *il, char **buf, bool display); 0044 0045 void il4965_nic_config(struct il_priv *il); 0046 0047 /* rx */ 0048 void il4965_rx_queue_restock(struct il_priv *il); 0049 void il4965_rx_replenish(struct il_priv *il); 0050 void il4965_rx_replenish_now(struct il_priv *il); 0051 void il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq); 0052 int il4965_rxq_stop(struct il_priv *il); 0053 int il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum nl80211_band band); 0054 void il4965_rx_handle(struct il_priv *il); 0055 0056 /* tx */ 0057 void il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq); 0058 int il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq, 0059 dma_addr_t addr, u16 len, u8 reset, u8 pad); 0060 int il4965_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq); 0061 void il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags, 0062 struct ieee80211_tx_info *info); 0063 int il4965_tx_skb(struct il_priv *il, 0064 struct ieee80211_sta *sta, 0065 struct sk_buff *skb); 0066 int il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif, 0067 struct ieee80211_sta *sta, u16 tid, u16 * ssn); 0068 int il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif, 0069 struct ieee80211_sta *sta, u16 tid); 0070 int il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id); 0071 int il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx); 0072 void il4965_hw_txq_ctx_free(struct il_priv *il); 0073 int il4965_txq_ctx_alloc(struct il_priv *il); 0074 void il4965_txq_ctx_reset(struct il_priv *il); 0075 void il4965_txq_ctx_stop(struct il_priv *il); 0076 void il4965_txq_set_sched(struct il_priv *il, u32 mask); 0077 0078 /* 0079 * Acquire il->lock before calling this function ! 0080 */ 0081 void il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx); 0082 /** 0083 * il4965_tx_queue_set_status - (optionally) start Tx/Cmd queue 0084 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed 0085 * @scd_retry: (1) Indicates queue will be used in aggregation mode 0086 * 0087 * NOTE: Acquire il->lock before calling this function ! 0088 */ 0089 void il4965_tx_queue_set_status(struct il_priv *il, struct il_tx_queue *txq, 0090 int tx_fifo_id, int scd_retry); 0091 0092 /* scan */ 0093 int il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif); 0094 0095 /* station mgmt */ 0096 int il4965_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif, 0097 bool add); 0098 0099 /* hcmd */ 0100 int il4965_send_beacon_cmd(struct il_priv *il); 0101 0102 #ifdef CONFIG_IWLEGACY_DEBUG 0103 const char *il4965_get_tx_fail_reason(u32 status); 0104 #else 0105 static inline const char * 0106 il4965_get_tx_fail_reason(u32 status) 0107 { 0108 return ""; 0109 } 0110 #endif 0111 0112 /* station management */ 0113 int il4965_alloc_bcast_station(struct il_priv *il); 0114 int il4965_add_bssid_station(struct il_priv *il, const u8 *addr, u8 *sta_id_r); 0115 int il4965_remove_default_wep_key(struct il_priv *il, 0116 struct ieee80211_key_conf *key); 0117 int il4965_set_default_wep_key(struct il_priv *il, 0118 struct ieee80211_key_conf *key); 0119 int il4965_restore_default_wep_keys(struct il_priv *il); 0120 int il4965_set_dynamic_key(struct il_priv *il, 0121 struct ieee80211_key_conf *key, u8 sta_id); 0122 int il4965_remove_dynamic_key(struct il_priv *il, 0123 struct ieee80211_key_conf *key, u8 sta_id); 0124 void il4965_update_tkip_key(struct il_priv *il, 0125 struct ieee80211_key_conf *keyconf, 0126 struct ieee80211_sta *sta, u32 iv32, 0127 u16 *phase1key); 0128 int il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid); 0129 int il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta, 0130 int tid, u16 ssn); 0131 int il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta, 0132 int tid); 0133 void il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt); 0134 int il4965_update_bcast_stations(struct il_priv *il); 0135 0136 /* rate */ 0137 static inline u8 0138 il4965_hw_get_rate(__le32 rate_n_flags) 0139 { 0140 return le32_to_cpu(rate_n_flags) & 0xFF; 0141 } 0142 0143 /* eeprom */ 0144 void il4965_eeprom_get_mac(const struct il_priv *il, u8 * mac); 0145 int il4965_eeprom_acquire_semaphore(struct il_priv *il); 0146 void il4965_eeprom_release_semaphore(struct il_priv *il); 0147 int il4965_eeprom_check_version(struct il_priv *il); 0148 0149 /* mac80211 handlers (for 4965) */ 0150 void il4965_mac_tx(struct ieee80211_hw *hw, 0151 struct ieee80211_tx_control *control, 0152 struct sk_buff *skb); 0153 int il4965_mac_start(struct ieee80211_hw *hw); 0154 void il4965_mac_stop(struct ieee80211_hw *hw); 0155 void il4965_configure_filter(struct ieee80211_hw *hw, 0156 unsigned int changed_flags, 0157 unsigned int *total_flags, u64 multicast); 0158 int il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 0159 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 0160 struct ieee80211_key_conf *key); 0161 void il4965_mac_update_tkip_key(struct ieee80211_hw *hw, 0162 struct ieee80211_vif *vif, 0163 struct ieee80211_key_conf *keyconf, 0164 struct ieee80211_sta *sta, u32 iv32, 0165 u16 *phase1key); 0166 int il4965_mac_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 0167 struct ieee80211_ampdu_params *params); 0168 int il4965_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 0169 struct ieee80211_sta *sta); 0170 void 0171 il4965_mac_channel_switch(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 0172 struct ieee80211_channel_switch *ch_switch); 0173 0174 void il4965_led_enable(struct il_priv *il); 0175 0176 /* EEPROM */ 0177 #define IL4965_EEPROM_IMG_SIZE 1024 0178 0179 /* 0180 * uCode queue management definitions ... 0181 * The first queue used for block-ack aggregation is #7 (4965 only). 0182 * All block-ack aggregation queues should map to Tx DMA/FIFO channel 7. 0183 */ 0184 #define IL49_FIRST_AMPDU_QUEUE 7 0185 0186 /* Sizes and addresses for instruction and data memory (SRAM) in 0187 * 4965's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */ 0188 #define IL49_RTC_INST_LOWER_BOUND (0x000000) 0189 #define IL49_RTC_INST_UPPER_BOUND (0x018000) 0190 0191 #define IL49_RTC_DATA_LOWER_BOUND (0x800000) 0192 #define IL49_RTC_DATA_UPPER_BOUND (0x80A000) 0193 0194 #define IL49_RTC_INST_SIZE (IL49_RTC_INST_UPPER_BOUND - \ 0195 IL49_RTC_INST_LOWER_BOUND) 0196 #define IL49_RTC_DATA_SIZE (IL49_RTC_DATA_UPPER_BOUND - \ 0197 IL49_RTC_DATA_LOWER_BOUND) 0198 0199 #define IL49_MAX_INST_SIZE IL49_RTC_INST_SIZE 0200 #define IL49_MAX_DATA_SIZE IL49_RTC_DATA_SIZE 0201 0202 /* Size of uCode instruction memory in bootstrap state machine */ 0203 #define IL49_MAX_BSM_SIZE BSM_SRAM_SIZE 0204 0205 static inline int 0206 il4965_hw_valid_rtc_data_addr(u32 addr) 0207 { 0208 return (addr >= IL49_RTC_DATA_LOWER_BOUND && 0209 addr < IL49_RTC_DATA_UPPER_BOUND); 0210 } 0211 0212 /********************* START TEMPERATURE *************************************/ 0213 0214 /** 0215 * 4965 temperature calculation. 0216 * 0217 * The driver must calculate the device temperature before calculating 0218 * a txpower setting (amplifier gain is temperature dependent). The 0219 * calculation uses 4 measurements, 3 of which (R1, R2, R3) are calibration 0220 * values used for the life of the driver, and one of which (R4) is the 0221 * real-time temperature indicator. 0222 * 0223 * uCode provides all 4 values to the driver via the "initialize alive" 0224 * notification (see struct il4965_init_alive_resp). After the runtime uCode 0225 * image loads, uCode updates the R4 value via stats notifications 0226 * (see N_STATS), which occur after each received beacon 0227 * when associated, or can be requested via C_STATS. 0228 * 0229 * NOTE: uCode provides the R4 value as a 23-bit signed value. Driver 0230 * must sign-extend to 32 bits before applying formula below. 0231 * 0232 * Formula: 0233 * 0234 * degrees Kelvin = ((97 * 259 * (R4 - R2) / (R3 - R1)) / 100) + 8 0235 * 0236 * NOTE: The basic formula is 259 * (R4-R2) / (R3-R1). The 97/100 is 0237 * an additional correction, which should be centered around 0 degrees 0238 * Celsius (273 degrees Kelvin). The 8 (3 percent of 273) compensates for 0239 * centering the 97/100 correction around 0 degrees K. 0240 * 0241 * Add 273 to Kelvin value to find degrees Celsius, for comparing current 0242 * temperature with factory-measured temperatures when calculating txpower 0243 * settings. 0244 */ 0245 #define TEMPERATURE_CALIB_KELVIN_OFFSET 8 0246 #define TEMPERATURE_CALIB_A_VAL 259 0247 0248 /* Limit range of calculated temperature to be between these Kelvin values */ 0249 #define IL_TX_POWER_TEMPERATURE_MIN (263) 0250 #define IL_TX_POWER_TEMPERATURE_MAX (410) 0251 0252 #define IL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \ 0253 ((t) < IL_TX_POWER_TEMPERATURE_MIN || \ 0254 (t) > IL_TX_POWER_TEMPERATURE_MAX) 0255 0256 void il4965_temperature_calib(struct il_priv *il); 0257 /********************* END TEMPERATURE ***************************************/ 0258 0259 /********************* START TXPOWER *****************************************/ 0260 0261 /** 0262 * 4965 txpower calculations rely on information from three sources: 0263 * 0264 * 1) EEPROM 0265 * 2) "initialize" alive notification 0266 * 3) stats notifications 0267 * 0268 * EEPROM data consists of: 0269 * 0270 * 1) Regulatory information (max txpower and channel usage flags) is provided 0271 * separately for each channel that can possibly supported by 4965. 0272 * 40 MHz wide (.11n HT40) channels are listed separately from 20 MHz 0273 * (legacy) channels. 0274 * 0275 * See struct il4965_eeprom_channel for format, and struct il4965_eeprom 0276 * for locations in EEPROM. 0277 * 0278 * 2) Factory txpower calibration information is provided separately for 0279 * sub-bands of contiguous channels. 2.4GHz has just one sub-band, 0280 * but 5 GHz has several sub-bands. 0281 * 0282 * In addition, per-band (2.4 and 5 Ghz) saturation txpowers are provided. 0283 * 0284 * See struct il4965_eeprom_calib_info (and the tree of structures 0285 * contained within it) for format, and struct il4965_eeprom for 0286 * locations in EEPROM. 0287 * 0288 * "Initialization alive" notification (see struct il4965_init_alive_resp) 0289 * consists of: 0290 * 0291 * 1) Temperature calculation parameters. 0292 * 0293 * 2) Power supply voltage measurement. 0294 * 0295 * 3) Tx gain compensation to balance 2 transmitters for MIMO use. 0296 * 0297 * Statistics notifications deliver: 0298 * 0299 * 1) Current values for temperature param R4. 0300 */ 0301 0302 /** 0303 * To calculate a txpower setting for a given desired target txpower, channel, 0304 * modulation bit rate, and transmitter chain (4965 has 2 transmitters to 0305 * support MIMO and transmit diversity), driver must do the following: 0306 * 0307 * 1) Compare desired txpower vs. (EEPROM) regulatory limit for this channel. 0308 * Do not exceed regulatory limit; reduce target txpower if necessary. 0309 * 0310 * If setting up txpowers for MIMO rates (rate idxes 8-15, 24-31), 0311 * 2 transmitters will be used simultaneously; driver must reduce the 0312 * regulatory limit by 3 dB (half-power) for each transmitter, so the 0313 * combined total output of the 2 transmitters is within regulatory limits. 0314 * 0315 * 0316 * 2) Compare target txpower vs. (EEPROM) saturation txpower *reduced by 0317 * backoff for this bit rate*. Do not exceed (saturation - backoff[rate]); 0318 * reduce target txpower if necessary. 0319 * 0320 * Backoff values below are in 1/2 dB units (equivalent to steps in 0321 * txpower gain tables): 0322 * 0323 * OFDM 6 - 36 MBit: 10 steps (5 dB) 0324 * OFDM 48 MBit: 15 steps (7.5 dB) 0325 * OFDM 54 MBit: 17 steps (8.5 dB) 0326 * OFDM 60 MBit: 20 steps (10 dB) 0327 * CCK all rates: 10 steps (5 dB) 0328 * 0329 * Backoff values apply to saturation txpower on a per-transmitter basis; 0330 * when using MIMO (2 transmitters), each transmitter uses the same 0331 * saturation level provided in EEPROM, and the same backoff values; 0332 * no reduction (such as with regulatory txpower limits) is required. 0333 * 0334 * Saturation and Backoff values apply equally to 20 Mhz (legacy) channel 0335 * widths and 40 Mhz (.11n HT40) channel widths; there is no separate 0336 * factory measurement for ht40 channels. 0337 * 0338 * The result of this step is the final target txpower. The rest of 0339 * the steps figure out the proper settings for the device to achieve 0340 * that target txpower. 0341 * 0342 * 0343 * 3) Determine (EEPROM) calibration sub band for the target channel, by 0344 * comparing against first and last channels in each sub band 0345 * (see struct il4965_eeprom_calib_subband_info). 0346 * 0347 * 0348 * 4) Linearly interpolate (EEPROM) factory calibration measurement sets, 0349 * referencing the 2 factory-measured (sample) channels within the sub band. 0350 * 0351 * Interpolation is based on difference between target channel's frequency 0352 * and the sample channels' frequencies. Since channel numbers are based 0353 * on frequency (5 MHz between each channel number), this is equivalent 0354 * to interpolating based on channel number differences. 0355 * 0356 * Note that the sample channels may or may not be the channels at the 0357 * edges of the sub band. The target channel may be "outside" of the 0358 * span of the sampled channels. 0359 * 0360 * Driver may choose the pair (for 2 Tx chains) of measurements (see 0361 * struct il4965_eeprom_calib_ch_info) for which the actual measured 0362 * txpower comes closest to the desired txpower. Usually, though, 0363 * the middle set of measurements is closest to the regulatory limits, 0364 * and is therefore a good choice for all txpower calculations (this 0365 * assumes that high accuracy is needed for maximizing legal txpower, 0366 * while lower txpower configurations do not need as much accuracy). 0367 * 0368 * Driver should interpolate both members of the chosen measurement pair, 0369 * i.e. for both Tx chains (radio transmitters), unless the driver knows 0370 * that only one of the chains will be used (e.g. only one tx antenna 0371 * connected, but this should be unusual). The rate scaling algorithm 0372 * switches antennas to find best performance, so both Tx chains will 0373 * be used (although only one at a time) even for non-MIMO transmissions. 0374 * 0375 * Driver should interpolate factory values for temperature, gain table 0376 * idx, and actual power. The power amplifier detector values are 0377 * not used by the driver. 0378 * 0379 * Sanity check: If the target channel happens to be one of the sample 0380 * channels, the results should agree with the sample channel's 0381 * measurements! 0382 * 0383 * 0384 * 5) Find difference between desired txpower and (interpolated) 0385 * factory-measured txpower. Using (interpolated) factory gain table idx 0386 * (shown elsewhere) as a starting point, adjust this idx lower to 0387 * increase txpower, or higher to decrease txpower, until the target 0388 * txpower is reached. Each step in the gain table is 1/2 dB. 0389 * 0390 * For example, if factory measured txpower is 16 dBm, and target txpower 0391 * is 13 dBm, add 6 steps to the factory gain idx to reduce txpower 0392 * by 3 dB. 0393 * 0394 * 0395 * 6) Find difference between current device temperature and (interpolated) 0396 * factory-measured temperature for sub-band. Factory values are in 0397 * degrees Celsius. To calculate current temperature, see comments for 0398 * "4965 temperature calculation". 0399 * 0400 * If current temperature is higher than factory temperature, driver must 0401 * increase gain (lower gain table idx), and vice verse. 0402 * 0403 * Temperature affects gain differently for different channels: 0404 * 0405 * 2.4 GHz all channels: 3.5 degrees per half-dB step 0406 * 5 GHz channels 34-43: 4.5 degrees per half-dB step 0407 * 5 GHz channels >= 44: 4.0 degrees per half-dB step 0408 * 0409 * NOTE: Temperature can increase rapidly when transmitting, especially 0410 * with heavy traffic at high txpowers. Driver should update 0411 * temperature calculations often under these conditions to 0412 * maintain strong txpower in the face of rising temperature. 0413 * 0414 * 0415 * 7) Find difference between current power supply voltage indicator 0416 * (from "initialize alive") and factory-measured power supply voltage 0417 * indicator (EEPROM). 0418 * 0419 * If the current voltage is higher (indicator is lower) than factory 0420 * voltage, gain should be reduced (gain table idx increased) by: 0421 * 0422 * (eeprom - current) / 7 0423 * 0424 * If the current voltage is lower (indicator is higher) than factory 0425 * voltage, gain should be increased (gain table idx decreased) by: 0426 * 0427 * 2 * (current - eeprom) / 7 0428 * 0429 * If number of idx steps in either direction turns out to be > 2, 0430 * something is wrong ... just use 0. 0431 * 0432 * NOTE: Voltage compensation is independent of band/channel. 0433 * 0434 * NOTE: "Initialize" uCode measures current voltage, which is assumed 0435 * to be constant after this initial measurement. Voltage 0436 * compensation for txpower (number of steps in gain table) 0437 * may be calculated once and used until the next uCode bootload. 0438 * 0439 * 0440 * 8) If setting up txpowers for MIMO rates (rate idxes 8-15, 24-31), 0441 * adjust txpower for each transmitter chain, so txpower is balanced 0442 * between the two chains. There are 5 pairs of tx_atten[group][chain] 0443 * values in "initialize alive", one pair for each of 5 channel ranges: 0444 * 0445 * Group 0: 5 GHz channel 34-43 0446 * Group 1: 5 GHz channel 44-70 0447 * Group 2: 5 GHz channel 71-124 0448 * Group 3: 5 GHz channel 125-200 0449 * Group 4: 2.4 GHz all channels 0450 * 0451 * Add the tx_atten[group][chain] value to the idx for the target chain. 0452 * The values are signed, but are in pairs of 0 and a non-negative number, 0453 * so as to reduce gain (if necessary) of the "hotter" channel. This 0454 * avoids any need to double-check for regulatory compliance after 0455 * this step. 0456 * 0457 * 0458 * 9) If setting up for a CCK rate, lower the gain by adding a CCK compensation 0459 * value to the idx: 0460 * 0461 * Hardware rev B: 9 steps (4.5 dB) 0462 * Hardware rev C: 5 steps (2.5 dB) 0463 * 0464 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG, 0465 * bits [3:2], 1 = B, 2 = C. 0466 * 0467 * NOTE: This compensation is in addition to any saturation backoff that 0468 * might have been applied in an earlier step. 0469 * 0470 * 0471 * 10) Select the gain table, based on band (2.4 vs 5 GHz). 0472 * 0473 * Limit the adjusted idx to stay within the table! 0474 * 0475 * 0476 * 11) Read gain table entries for DSP and radio gain, place into appropriate 0477 * location(s) in command (struct il4965_txpowertable_cmd). 0478 */ 0479 0480 /** 0481 * When MIMO is used (2 transmitters operating simultaneously), driver should 0482 * limit each transmitter to deliver a max of 3 dB below the regulatory limit 0483 * for the device. That is, use half power for each transmitter, so total 0484 * txpower is within regulatory limits. 0485 * 0486 * The value "6" represents number of steps in gain table to reduce power 3 dB. 0487 * Each step is 1/2 dB. 0488 */ 0489 #define IL_TX_POWER_MIMO_REGULATORY_COMPENSATION (6) 0490 0491 /** 0492 * CCK gain compensation. 0493 * 0494 * When calculating txpowers for CCK, after making sure that the target power 0495 * is within regulatory and saturation limits, driver must additionally 0496 * back off gain by adding these values to the gain table idx. 0497 * 0498 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG, 0499 * bits [3:2], 1 = B, 2 = C. 0500 */ 0501 #define IL_TX_POWER_CCK_COMPENSATION_B_STEP (9) 0502 #define IL_TX_POWER_CCK_COMPENSATION_C_STEP (5) 0503 0504 /* 0505 * 4965 power supply voltage compensation for txpower 0506 */ 0507 #define TX_POWER_IL_VOLTAGE_CODES_PER_03V (7) 0508 0509 /** 0510 * Gain tables. 0511 * 0512 * The following tables contain pair of values for setting txpower, i.e. 0513 * gain settings for the output of the device's digital signal processor (DSP), 0514 * and for the analog gain structure of the transmitter. 0515 * 0516 * Each entry in the gain tables represents a step of 1/2 dB. Note that these 0517 * are *relative* steps, not indications of absolute output power. Output 0518 * power varies with temperature, voltage, and channel frequency, and also 0519 * requires consideration of average power (to satisfy regulatory constraints), 0520 * and peak power (to avoid distortion of the output signal). 0521 * 0522 * Each entry contains two values: 0523 * 1) DSP gain (or sometimes called DSP attenuation). This is a fine-grained 0524 * linear value that multiplies the output of the digital signal processor, 0525 * before being sent to the analog radio. 0526 * 2) Radio gain. This sets the analog gain of the radio Tx path. 0527 * It is a coarser setting, and behaves in a logarithmic (dB) fashion. 0528 * 0529 * EEPROM contains factory calibration data for txpower. This maps actual 0530 * measured txpower levels to gain settings in the "well known" tables 0531 * below ("well-known" means here that both factory calibration *and* the 0532 * driver work with the same table). 0533 * 0534 * There are separate tables for 2.4 GHz and 5 GHz bands. The 5 GHz table 0535 * has an extension (into negative idxes), in case the driver needs to 0536 * boost power setting for high device temperatures (higher than would be 0537 * present during factory calibration). A 5 Ghz EEPROM idx of "40" 0538 * corresponds to the 49th entry in the table used by the driver. 0539 */ 0540 #define MIN_TX_GAIN_IDX (0) /* highest gain, lowest idx, 2.4 */ 0541 #define MIN_TX_GAIN_IDX_52GHZ_EXT (-9) /* highest gain, lowest idx, 5 */ 0542 0543 /** 0544 * 2.4 GHz gain table 0545 * 0546 * Index Dsp gain Radio gain 0547 * 0 110 0x3f (highest gain) 0548 * 1 104 0x3f 0549 * 2 98 0x3f 0550 * 3 110 0x3e 0551 * 4 104 0x3e 0552 * 5 98 0x3e 0553 * 6 110 0x3d 0554 * 7 104 0x3d 0555 * 8 98 0x3d 0556 * 9 110 0x3c 0557 * 10 104 0x3c 0558 * 11 98 0x3c 0559 * 12 110 0x3b 0560 * 13 104 0x3b 0561 * 14 98 0x3b 0562 * 15 110 0x3a 0563 * 16 104 0x3a 0564 * 17 98 0x3a 0565 * 18 110 0x39 0566 * 19 104 0x39 0567 * 20 98 0x39 0568 * 21 110 0x38 0569 * 22 104 0x38 0570 * 23 98 0x38 0571 * 24 110 0x37 0572 * 25 104 0x37 0573 * 26 98 0x37 0574 * 27 110 0x36 0575 * 28 104 0x36 0576 * 29 98 0x36 0577 * 30 110 0x35 0578 * 31 104 0x35 0579 * 32 98 0x35 0580 * 33 110 0x34 0581 * 34 104 0x34 0582 * 35 98 0x34 0583 * 36 110 0x33 0584 * 37 104 0x33 0585 * 38 98 0x33 0586 * 39 110 0x32 0587 * 40 104 0x32 0588 * 41 98 0x32 0589 * 42 110 0x31 0590 * 43 104 0x31 0591 * 44 98 0x31 0592 * 45 110 0x30 0593 * 46 104 0x30 0594 * 47 98 0x30 0595 * 48 110 0x6 0596 * 49 104 0x6 0597 * 50 98 0x6 0598 * 51 110 0x5 0599 * 52 104 0x5 0600 * 53 98 0x5 0601 * 54 110 0x4 0602 * 55 104 0x4 0603 * 56 98 0x4 0604 * 57 110 0x3 0605 * 58 104 0x3 0606 * 59 98 0x3 0607 * 60 110 0x2 0608 * 61 104 0x2 0609 * 62 98 0x2 0610 * 63 110 0x1 0611 * 64 104 0x1 0612 * 65 98 0x1 0613 * 66 110 0x0 0614 * 67 104 0x0 0615 * 68 98 0x0 0616 * 69 97 0 0617 * 70 96 0 0618 * 71 95 0 0619 * 72 94 0 0620 * 73 93 0 0621 * 74 92 0 0622 * 75 91 0 0623 * 76 90 0 0624 * 77 89 0 0625 * 78 88 0 0626 * 79 87 0 0627 * 80 86 0 0628 * 81 85 0 0629 * 82 84 0 0630 * 83 83 0 0631 * 84 82 0 0632 * 85 81 0 0633 * 86 80 0 0634 * 87 79 0 0635 * 88 78 0 0636 * 89 77 0 0637 * 90 76 0 0638 * 91 75 0 0639 * 92 74 0 0640 * 93 73 0 0641 * 94 72 0 0642 * 95 71 0 0643 * 96 70 0 0644 * 97 69 0 0645 * 98 68 0 0646 */ 0647 0648 /** 0649 * 5 GHz gain table 0650 * 0651 * Index Dsp gain Radio gain 0652 * -9 123 0x3F (highest gain) 0653 * -8 117 0x3F 0654 * -7 110 0x3F 0655 * -6 104 0x3F 0656 * -5 98 0x3F 0657 * -4 110 0x3E 0658 * -3 104 0x3E 0659 * -2 98 0x3E 0660 * -1 110 0x3D 0661 * 0 104 0x3D 0662 * 1 98 0x3D 0663 * 2 110 0x3C 0664 * 3 104 0x3C 0665 * 4 98 0x3C 0666 * 5 110 0x3B 0667 * 6 104 0x3B 0668 * 7 98 0x3B 0669 * 8 110 0x3A 0670 * 9 104 0x3A 0671 * 10 98 0x3A 0672 * 11 110 0x39 0673 * 12 104 0x39 0674 * 13 98 0x39 0675 * 14 110 0x38 0676 * 15 104 0x38 0677 * 16 98 0x38 0678 * 17 110 0x37 0679 * 18 104 0x37 0680 * 19 98 0x37 0681 * 20 110 0x36 0682 * 21 104 0x36 0683 * 22 98 0x36 0684 * 23 110 0x35 0685 * 24 104 0x35 0686 * 25 98 0x35 0687 * 26 110 0x34 0688 * 27 104 0x34 0689 * 28 98 0x34 0690 * 29 110 0x33 0691 * 30 104 0x33 0692 * 31 98 0x33 0693 * 32 110 0x32 0694 * 33 104 0x32 0695 * 34 98 0x32 0696 * 35 110 0x31 0697 * 36 104 0x31 0698 * 37 98 0x31 0699 * 38 110 0x30 0700 * 39 104 0x30 0701 * 40 98 0x30 0702 * 41 110 0x25 0703 * 42 104 0x25 0704 * 43 98 0x25 0705 * 44 110 0x24 0706 * 45 104 0x24 0707 * 46 98 0x24 0708 * 47 110 0x23 0709 * 48 104 0x23 0710 * 49 98 0x23 0711 * 50 110 0x22 0712 * 51 104 0x18 0713 * 52 98 0x18 0714 * 53 110 0x17 0715 * 54 104 0x17 0716 * 55 98 0x17 0717 * 56 110 0x16 0718 * 57 104 0x16 0719 * 58 98 0x16 0720 * 59 110 0x15 0721 * 60 104 0x15 0722 * 61 98 0x15 0723 * 62 110 0x14 0724 * 63 104 0x14 0725 * 64 98 0x14 0726 * 65 110 0x13 0727 * 66 104 0x13 0728 * 67 98 0x13 0729 * 68 110 0x12 0730 * 69 104 0x08 0731 * 70 98 0x08 0732 * 71 110 0x07 0733 * 72 104 0x07 0734 * 73 98 0x07 0735 * 74 110 0x06 0736 * 75 104 0x06 0737 * 76 98 0x06 0738 * 77 110 0x05 0739 * 78 104 0x05 0740 * 79 98 0x05 0741 * 80 110 0x04 0742 * 81 104 0x04 0743 * 82 98 0x04 0744 * 83 110 0x03 0745 * 84 104 0x03 0746 * 85 98 0x03 0747 * 86 110 0x02 0748 * 87 104 0x02 0749 * 88 98 0x02 0750 * 89 110 0x01 0751 * 90 104 0x01 0752 * 91 98 0x01 0753 * 92 110 0x00 0754 * 93 104 0x00 0755 * 94 98 0x00 0756 * 95 93 0x00 0757 * 96 88 0x00 0758 * 97 83 0x00 0759 * 98 78 0x00 0760 */ 0761 0762 /** 0763 * Sanity checks and default values for EEPROM regulatory levels. 0764 * If EEPROM values fall outside MIN/MAX range, use default values. 0765 * 0766 * Regulatory limits refer to the maximum average txpower allowed by 0767 * regulatory agencies in the geographies in which the device is meant 0768 * to be operated. These limits are SKU-specific (i.e. geography-specific), 0769 * and channel-specific; each channel has an individual regulatory limit 0770 * listed in the EEPROM. 0771 * 0772 * Units are in half-dBm (i.e. "34" means 17 dBm). 0773 */ 0774 #define IL_TX_POWER_DEFAULT_REGULATORY_24 (34) 0775 #define IL_TX_POWER_DEFAULT_REGULATORY_52 (34) 0776 #define IL_TX_POWER_REGULATORY_MIN (0) 0777 #define IL_TX_POWER_REGULATORY_MAX (34) 0778 0779 /** 0780 * Sanity checks and default values for EEPROM saturation levels. 0781 * If EEPROM values fall outside MIN/MAX range, use default values. 0782 * 0783 * Saturation is the highest level that the output power amplifier can produce 0784 * without significant clipping distortion. This is a "peak" power level. 0785 * Different types of modulation (i.e. various "rates", and OFDM vs. CCK) 0786 * require differing amounts of backoff, relative to their average power output, 0787 * in order to avoid clipping distortion. 0788 * 0789 * Driver must make sure that it is violating neither the saturation limit, 0790 * nor the regulatory limit, when calculating Tx power settings for various 0791 * rates. 0792 * 0793 * Units are in half-dBm (i.e. "38" means 19 dBm). 0794 */ 0795 #define IL_TX_POWER_DEFAULT_SATURATION_24 (38) 0796 #define IL_TX_POWER_DEFAULT_SATURATION_52 (38) 0797 #define IL_TX_POWER_SATURATION_MIN (20) 0798 #define IL_TX_POWER_SATURATION_MAX (50) 0799 0800 /** 0801 * Channel groups used for Tx Attenuation calibration (MIMO tx channel balance) 0802 * and thermal Txpower calibration. 0803 * 0804 * When calculating txpower, driver must compensate for current device 0805 * temperature; higher temperature requires higher gain. Driver must calculate 0806 * current temperature (see "4965 temperature calculation"), then compare vs. 0807 * factory calibration temperature in EEPROM; if current temperature is higher 0808 * than factory temperature, driver must *increase* gain by proportions shown 0809 * in table below. If current temperature is lower than factory, driver must 0810 * *decrease* gain. 0811 * 0812 * Different frequency ranges require different compensation, as shown below. 0813 */ 0814 /* Group 0, 5.2 GHz ch 34-43: 4.5 degrees per 1/2 dB. */ 0815 #define CALIB_IL_TX_ATTEN_GR1_FCH 34 0816 #define CALIB_IL_TX_ATTEN_GR1_LCH 43 0817 0818 /* Group 1, 5.3 GHz ch 44-70: 4.0 degrees per 1/2 dB. */ 0819 #define CALIB_IL_TX_ATTEN_GR2_FCH 44 0820 #define CALIB_IL_TX_ATTEN_GR2_LCH 70 0821 0822 /* Group 2, 5.5 GHz ch 71-124: 4.0 degrees per 1/2 dB. */ 0823 #define CALIB_IL_TX_ATTEN_GR3_FCH 71 0824 #define CALIB_IL_TX_ATTEN_GR3_LCH 124 0825 0826 /* Group 3, 5.7 GHz ch 125-200: 4.0 degrees per 1/2 dB. */ 0827 #define CALIB_IL_TX_ATTEN_GR4_FCH 125 0828 #define CALIB_IL_TX_ATTEN_GR4_LCH 200 0829 0830 /* Group 4, 2.4 GHz all channels: 3.5 degrees per 1/2 dB. */ 0831 #define CALIB_IL_TX_ATTEN_GR5_FCH 1 0832 #define CALIB_IL_TX_ATTEN_GR5_LCH 20 0833 0834 enum { 0835 CALIB_CH_GROUP_1 = 0, 0836 CALIB_CH_GROUP_2 = 1, 0837 CALIB_CH_GROUP_3 = 2, 0838 CALIB_CH_GROUP_4 = 3, 0839 CALIB_CH_GROUP_5 = 4, 0840 CALIB_CH_GROUP_MAX 0841 }; 0842 0843 /********************* END TXPOWER *****************************************/ 0844 0845 /** 0846 * Tx/Rx Queues 0847 * 0848 * Most communication between driver and 4965 is via queues of data buffers. 0849 * For example, all commands that the driver issues to device's embedded 0850 * controller (uCode) are via the command queue (one of the Tx queues). All 0851 * uCode command responses/replies/notifications, including Rx frames, are 0852 * conveyed from uCode to driver via the Rx queue. 0853 * 0854 * Most support for these queues, including handshake support, resides in 0855 * structures in host DRAM, shared between the driver and the device. When 0856 * allocating this memory, the driver must make sure that data written by 0857 * the host CPU updates DRAM immediately (and does not get "stuck" in CPU's 0858 * cache memory), so DRAM and cache are consistent, and the device can 0859 * immediately see changes made by the driver. 0860 * 0861 * 4965 supports up to 16 DRAM-based Tx queues, and services these queues via 0862 * up to 7 DMA channels (FIFOs). Each Tx queue is supported by a circular array 0863 * in DRAM containing 256 Transmit Frame Descriptors (TFDs). 0864 */ 0865 #define IL49_NUM_FIFOS 7 0866 #define IL49_CMD_FIFO_NUM 4 0867 #define IL49_NUM_QUEUES 16 0868 #define IL49_NUM_AMPDU_QUEUES 8 0869 0870 /** 0871 * struct il4965_schedq_bc_tbl 0872 * 0873 * Byte Count table 0874 * 0875 * Each Tx queue uses a byte-count table containing 320 entries: 0876 * one 16-bit entry for each of 256 TFDs, plus an additional 64 entries that 0877 * duplicate the first 64 entries (to avoid wrap-around within a Tx win; 0878 * max Tx win is 64 TFDs). 0879 * 0880 * When driver sets up a new TFD, it must also enter the total byte count 0881 * of the frame to be transmitted into the corresponding entry in the byte 0882 * count table for the chosen Tx queue. If the TFD idx is 0-63, the driver 0883 * must duplicate the byte count entry in corresponding idx 256-319. 0884 * 0885 * padding puts each byte count table on a 1024-byte boundary; 0886 * 4965 assumes tables are separated by 1024 bytes. 0887 */ 0888 struct il4965_scd_bc_tbl { 0889 __le16 tfd_offset[TFD_QUEUE_BC_SIZE]; 0890 u8 pad[1024 - (TFD_QUEUE_BC_SIZE) * sizeof(__le16)]; 0891 } __packed; 0892 0893 #define IL4965_RTC_INST_LOWER_BOUND (0x000000) 0894 0895 /* RSSI to dBm */ 0896 #define IL4965_RSSI_OFFSET 44 0897 0898 /* PCI registers */ 0899 #define PCI_CFG_RETRY_TIMEOUT 0x041 0900 0901 #define IL4965_DEFAULT_TX_RETRY 15 0902 0903 /* EEPROM */ 0904 #define IL4965_FIRST_AMPDU_QUEUE 10 0905 0906 /* Calibration */ 0907 void il4965_chain_noise_calibration(struct il_priv *il, void *stat_resp); 0908 void il4965_sensitivity_calibration(struct il_priv *il, void *resp); 0909 void il4965_init_sensitivity(struct il_priv *il); 0910 void il4965_reset_run_time_calib(struct il_priv *il); 0911 0912 /* Debug */ 0913 #ifdef CONFIG_IWLEGACY_DEBUGFS 0914 extern const struct il_debugfs_ops il4965_debugfs_ops; 0915 #endif 0916 0917 /****************************/ 0918 /* Flow Handler Definitions */ 0919 /****************************/ 0920 0921 /** 0922 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 0923 * Addresses are offsets from device's PCI hardware base address. 0924 */ 0925 #define FH49_MEM_LOWER_BOUND (0x1000) 0926 #define FH49_MEM_UPPER_BOUND (0x2000) 0927 0928 /** 0929 * Keep-Warm (KW) buffer base address. 0930 * 0931 * Driver must allocate a 4KByte buffer that is used by 4965 for keeping the 0932 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 0933 * DRAM access when 4965 is Txing or Rxing. The dummy accesses prevent host 0934 * from going into a power-savings mode that would cause higher DRAM latency, 0935 * and possible data over/under-runs, before all Tx/Rx is complete. 0936 * 0937 * Driver loads FH49_KW_MEM_ADDR_REG with the physical address (bits 35:4) 0938 * of the buffer, which must be 4K aligned. Once this is set up, the 4965 0939 * automatically invokes keep-warm accesses when normal accesses might not 0940 * be sufficient to maintain fast DRAM response. 0941 * 0942 * Bit fields: 0943 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 0944 */ 0945 #define FH49_KW_MEM_ADDR_REG (FH49_MEM_LOWER_BOUND + 0x97C) 0946 0947 /** 0948 * TFD Circular Buffers Base (CBBC) addresses 0949 * 0950 * 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident 0951 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 0952 * (see struct il_tfd_frame). These 16 pointer registers are offset by 0x04 0953 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 0954 * aligned (address bits 0-7 must be 0). 0955 * 0956 * Bit fields in each pointer register: 0957 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 0958 */ 0959 #define FH49_MEM_CBBC_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x9D0) 0960 #define FH49_MEM_CBBC_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xA10) 0961 0962 /* Find TFD CB base pointer for given queue (range 0-15). */ 0963 #define FH49_MEM_CBBC_QUEUE(x) (FH49_MEM_CBBC_LOWER_BOUND + (x) * 0x4) 0964 0965 /** 0966 * Rx SRAM Control and Status Registers (RSCSR) 0967 * 0968 * These registers provide handshake between driver and 4965 for the Rx queue 0969 * (this queue handles *all* command responses, notifications, Rx data, etc. 0970 * sent from 4965 uCode to host driver). Unlike Tx, there is only one Rx 0971 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 0972 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 0973 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 0974 * mapping between RBDs and RBs. 0975 * 0976 * Driver must allocate host DRAM memory for the following, and set the 0977 * physical address of each into 4965 registers: 0978 * 0979 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 0980 * entries (although any power of 2, up to 4096, is selectable by driver). 0981 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 0982 * (typically 4K, although 8K or 16K are also selectable by driver). 0983 * Driver sets up RB size and number of RBDs in the CB via Rx config 0984 * register FH49_MEM_RCSR_CHNL0_CONFIG_REG. 0985 * 0986 * Bit fields within one RBD: 0987 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 0988 * 0989 * Driver sets physical address [35:8] of base of RBD circular buffer 0990 * into FH49_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 0991 * 0992 * 2) Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers 0993 * (RBs) have been filled, via a "write pointer", actually the idx of 0994 * the RB's corresponding RBD within the circular buffer. Driver sets 0995 * physical address [35:4] into FH49_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 0996 * 0997 * Bit fields in lower dword of Rx status buffer (upper dword not used 0998 * by driver; see struct il4965_shared, val0): 0999 * 31-12: Not used by driver 1000 * 11- 0: Index of last filled Rx buffer descriptor 1001 * (4965 writes, driver reads this value) 1002 * 1003 * As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must 1004 * enter pointers to these RBs into contiguous RBD circular buffer entries, 1005 * and update the 4965's "write" idx register, 1006 * FH49_RSCSR_CHNL0_RBDCB_WPTR_REG. 1007 * 1008 * This "write" idx corresponds to the *next* RBD that the driver will make 1009 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 1010 * the circular buffer. This value should initially be 0 (before preparing any 1011 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 1012 * wrap back to 0 at the end of the circular buffer (but don't wrap before 1013 * "read" idx has advanced past 1! See below). 1014 * NOTE: 4965 EXPECTS THE WRITE IDX TO BE INCREMENTED IN MULTIPLES OF 8. 1015 * 1016 * As the 4965 fills RBs (referenced from contiguous RBDs within the circular 1017 * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 1018 * to tell the driver the idx of the latest filled RBD. The driver must 1019 * read this "read" idx from DRAM after receiving an Rx interrupt from 4965. 1020 * 1021 * The driver must also internally keep track of a third idx, which is the 1022 * next RBD to process. When receiving an Rx interrupt, driver should process 1023 * all filled but unprocessed RBs up to, but not including, the RB 1024 * corresponding to the "read" idx. For example, if "read" idx becomes "1", 1025 * driver may process the RB pointed to by RBD 0. Depending on volume of 1026 * traffic, there may be many RBs to process. 1027 * 1028 * If read idx == write idx, 4965 thinks there is no room to put new data. 1029 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 1030 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 1031 * and "read" idxes; that is, make sure that there are no more than 254 1032 * buffers waiting to be filled. 1033 */ 1034 #define FH49_MEM_RSCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xBC0) 1035 #define FH49_MEM_RSCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xC00) 1036 #define FH49_MEM_RSCSR_CHNL0 (FH49_MEM_RSCSR_LOWER_BOUND) 1037 1038 /** 1039 * Physical base address of 8-byte Rx Status buffer. 1040 * Bit fields: 1041 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 1042 */ 1043 #define FH49_RSCSR_CHNL0_STTS_WPTR_REG (FH49_MEM_RSCSR_CHNL0) 1044 1045 /** 1046 * Physical base address of Rx Buffer Descriptor Circular Buffer. 1047 * Bit fields: 1048 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 1049 */ 1050 #define FH49_RSCSR_CHNL0_RBDCB_BASE_REG (FH49_MEM_RSCSR_CHNL0 + 0x004) 1051 1052 /** 1053 * Rx write pointer (idx, really!). 1054 * Bit fields: 1055 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 1056 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 1057 */ 1058 #define FH49_RSCSR_CHNL0_RBDCB_WPTR_REG (FH49_MEM_RSCSR_CHNL0 + 0x008) 1059 #define FH49_RSCSR_CHNL0_WPTR (FH49_RSCSR_CHNL0_RBDCB_WPTR_REG) 1060 1061 /** 1062 * Rx Config/Status Registers (RCSR) 1063 * Rx Config Reg for channel 0 (only channel used) 1064 * 1065 * Driver must initialize FH49_MEM_RCSR_CHNL0_CONFIG_REG as follows for 1066 * normal operation (see bit fields). 1067 * 1068 * Clearing FH49_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 1069 * Driver should poll FH49_MEM_RSSR_RX_STATUS_REG for 1070 * FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 1071 * 1072 * Bit fields: 1073 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1074 * '10' operate normally 1075 * 29-24: reserved 1076 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 1077 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 1078 * 19-18: reserved 1079 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 1080 * '10' 12K, '11' 16K. 1081 * 15-14: reserved 1082 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 1083 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 1084 * typical value 0x10 (about 1/2 msec) 1085 * 3- 0: reserved 1086 */ 1087 #define FH49_MEM_RCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xC00) 1088 #define FH49_MEM_RCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xCC0) 1089 #define FH49_MEM_RCSR_CHNL0 (FH49_MEM_RCSR_LOWER_BOUND) 1090 1091 #define FH49_MEM_RCSR_CHNL0_CONFIG_REG (FH49_MEM_RCSR_CHNL0) 1092 1093 #define FH49_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 1094 #define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 1095 #define FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 1096 #define FH49_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 1097 #define FH49_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 1098 #define FH49_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31 */ 1099 1100 #define FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 1101 #define FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 1102 #define RX_RB_TIMEOUT (0x10) 1103 1104 #define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 1105 #define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 1106 #define FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 1107 1108 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 1109 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 1110 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 1111 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 1112 1113 #define FH49_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 1114 #define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 1115 #define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 1116 1117 /** 1118 * Rx Shared Status Registers (RSSR) 1119 * 1120 * After stopping Rx DMA channel (writing 0 to 1121 * FH49_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 1122 * FH49_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 1123 * 1124 * Bit fields: 1125 * 24: 1 = Channel 0 is idle 1126 * 1127 * FH49_MEM_RSSR_SHARED_CTRL_REG and FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 1128 * contain default values that should not be altered by the driver. 1129 */ 1130 #define FH49_MEM_RSSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xC40) 1131 #define FH49_MEM_RSSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xD00) 1132 1133 #define FH49_MEM_RSSR_SHARED_CTRL_REG (FH49_MEM_RSSR_LOWER_BOUND) 1134 #define FH49_MEM_RSSR_RX_STATUS_REG (FH49_MEM_RSSR_LOWER_BOUND + 0x004) 1135 #define FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 1136 (FH49_MEM_RSSR_LOWER_BOUND + 0x008) 1137 1138 #define FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 1139 1140 #define FH49_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 1141 1142 /* TFDB Area - TFDs buffer table */ 1143 #define FH49_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 1144 #define FH49_TFDIB_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x900) 1145 #define FH49_TFDIB_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0x958) 1146 #define FH49_TFDIB_CTRL0_REG(_chnl) (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 1147 #define FH49_TFDIB_CTRL1_REG(_chnl) (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 1148 1149 /** 1150 * Transmit DMA Channel Control/Status Registers (TCSR) 1151 * 1152 * 4965 has one configuration register for each of 8 Tx DMA/FIFO channels 1153 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 1154 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 1155 * 1156 * To use a Tx DMA channel, driver must initialize its 1157 * FH49_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 1158 * 1159 * FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1160 * FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 1161 * 1162 * All other bits should be 0. 1163 * 1164 * Bit fields: 1165 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1166 * '10' operate normally 1167 * 29- 4: Reserved, set to "0" 1168 * 3: Enable internal DMA requests (1, normal operation), disable (0) 1169 * 2- 0: Reserved, set to "0" 1170 */ 1171 #define FH49_TCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xD00) 1172 #define FH49_TCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xE60) 1173 1174 /* Find Control/Status reg for given Tx DMA/FIFO channel */ 1175 #define FH49_TCSR_CHNL_NUM (7) 1176 #define FH50_TCSR_CHNL_NUM (8) 1177 1178 /* TCSR: tx_config register values */ 1179 #define FH49_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 1180 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 1181 #define FH49_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 1182 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 1183 #define FH49_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 1184 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 1185 1186 #define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1187 #define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 1188 1189 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 1190 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 1191 1192 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 1193 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 1194 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1195 1196 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1197 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 1198 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 1199 1200 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1201 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 1202 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1203 1204 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 1205 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 1206 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 1207 1208 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 1209 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 1210 1211 /** 1212 * Tx Shared Status Registers (TSSR) 1213 * 1214 * After stopping Tx DMA channel (writing 0 to 1215 * FH49_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 1216 * FH49_TSSR_TX_STATUS_REG until selected Tx channel is idle 1217 * (channel's buffers empty | no pending requests). 1218 * 1219 * Bit fields: 1220 * 31-24: 1 = Channel buffers empty (channel 7:0) 1221 * 23-16: 1 = No pending requests (channel 7:0) 1222 */ 1223 #define FH49_TSSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xEA0) 1224 #define FH49_TSSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xEC0) 1225 1226 #define FH49_TSSR_TX_STATUS_REG (FH49_TSSR_LOWER_BOUND + 0x010) 1227 1228 /** 1229 * Bit fields for TSSR(Tx Shared Status & Control) error status register: 1230 * 31: Indicates an address error when accessed to internal memory 1231 * uCode/driver must write "1" in order to clear this flag 1232 * 30: Indicates that Host did not send the expected number of dwords to FH 1233 * uCode/driver must write "1" in order to clear this flag 1234 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 1235 * command was received from the scheduler while the TRB was already full 1236 * with previous command 1237 * uCode/driver must write "1" in order to clear this flag 1238 * 7-0: Each status bit indicates a channel's TxCredit error. When an error 1239 * bit is set, it indicates that the FH has received a full indication 1240 * from the RTC TxFIFO and the current value of the TxCredit counter was 1241 * not equal to zero. This mean that the credit mechanism was not 1242 * synchronized to the TxFIFO status 1243 * uCode/driver must write "1" in order to clear this flag 1244 */ 1245 #define FH49_TSSR_TX_ERROR_REG (FH49_TSSR_LOWER_BOUND + 0x018) 1246 1247 #define FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 1248 1249 /* Tx service channels */ 1250 #define FH49_SRVC_CHNL (9) 1251 #define FH49_SRVC_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x9C8) 1252 #define FH49_SRVC_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0x9D0) 1253 #define FH49_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 1254 (FH49_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 1255 1256 #define FH49_TX_CHICKEN_BITS_REG (FH49_MEM_LOWER_BOUND + 0xE98) 1257 /* Instruct FH to increment the retry count of a packet when 1258 * it is brought from the memory to TX-FIFO 1259 */ 1260 #define FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 1261 1262 /* Keep Warm Size */ 1263 #define IL_KW_SIZE 0x1000 /* 4k */ 1264 1265 #endif /* __il_4965_h__ */
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