intel/iwlegacy/3945.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /******************************************************************************
0003  *
0004  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
0005  *
0006  * Contact Information:
0007  *  Intel Linux Wireless <ilw@linux.intel.com>
0008  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
0009  *
0010  *****************************************************************************/
0011
0012 #ifndef __il_3945_h__
0013 #define __il_3945_h__
0014
0015 #include <linux/pci.h>      /* for struct pci_device_id */
0016 #include <linux/kernel.h>
0017 #include <net/ieee80211_radiotap.h>
0018
0019 /* Hardware specific file defines the PCI IDs table for that hardware module */
0020 extern const struct pci_device_id il3945_hw_card_ids[];
0021
0022 #include "common.h"
0023
0024 extern const struct il_ops il3945_ops;
0025
0026 /* Highest firmware API version supported */
0027 #define IL3945_UCODE_API_MAX 2
0028
0029 /* Lowest firmware API version supported */
0030 #define IL3945_UCODE_API_MIN 1
0031
0032 #define IL3945_FW_PRE   "iwlwifi-3945-"
0033 #define _IL3945_MODULE_FIRMWARE(api) IL3945_FW_PRE #api ".ucode"
0034 #define IL3945_MODULE_FIRMWARE(api) _IL3945_MODULE_FIRMWARE(api)
0035
0036 /* Default noise level to report when noise measurement is not available.
0037  *   This may be because we're:
0038  *   1)  Not associated (4965, no beacon stats being sent to driver)
0039  *   2)  Scanning (noise measurement does not apply to associated channel)
0040  *   3)  Receiving CCK (3945 delivers noise info only for OFDM frames)
0041  * Use default noise value of -127 ... this is below the range of measurable
0042  *   Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
0043  *   Also, -127 works better than 0 when averaging frames with/without
0044  *   noise info (e.g. averaging might be done in app); measured dBm values are
0045  *   always negative ... using a negative value as the default keeps all
0046  *   averages within an s8's (used in some apps) range of negative values. */
0047 #define IL_NOISE_MEAS_NOT_AVAILABLE (-127)
0048
0049 /* Module parameters accessible from iwl-*.c */
0050 extern struct il_mod_params il3945_mod_params;
0051
0052 struct il3945_rate_scale_data {
0053     u64 data;
0054     s32 success_counter;
0055     s32 success_ratio;
0056     s32 counter;
0057     s32 average_tpt;
0058     unsigned long stamp;
0059 };
0060
0061 struct il3945_rs_sta {
0062     spinlock_t lock;
0063     struct il_priv *il;
0064     s32 *expected_tpt;
0065     unsigned long last_partial_flush;
0066     unsigned long last_flush;
0067     u32 flush_time;
0068     u32 last_tx_packets;
0069     u32 tx_packets;
0070     u8 tgg;
0071     u8 flush_pending;
0072     u8 start_rate;
0073     struct timer_list rate_scale_flush;
0074     struct il3945_rate_scale_data win[RATE_COUNT_3945];
0075
0076     /* used to be in sta_info */
0077     int last_txrate_idx;
0078 };
0079
0080 /*
0081  * The common struct MUST be first because it is shared between
0082  * 3945 and 4965!
0083  */
0084 struct il3945_sta_priv {
0085     struct il_station_priv_common common;
0086     struct il3945_rs_sta rs_sta;
0087 };
0088
0089 enum il3945_antenna {
0090     IL_ANTENNA_DIVERSITY,
0091     IL_ANTENNA_MAIN,
0092     IL_ANTENNA_AUX
0093 };
0094
0095 /*
0096  * RTS threshold here is total size [2347] minus 4 FCS bytes
0097  * Per spec:
0098  *   a value of 0 means RTS on all data/management packets
0099  *   a value > max MSDU size means no RTS
0100  * else RTS for data/management frames where MPDU is larger
0101  *   than RTS value.
0102  */
0103 #define DEFAULT_RTS_THRESHOLD     2347U
0104 #define MIN_RTS_THRESHOLD         0U
0105 #define MAX_RTS_THRESHOLD         2347U
0106 #define MAX_MSDU_SIZE         2304U
0107 #define MAX_MPDU_SIZE         2346U
0108 #define DEFAULT_BEACON_INTERVAL   100U
0109 #define DEFAULT_SHORT_RETRY_LIMIT 7U
0110 #define DEFAULT_LONG_RETRY_LIMIT  4U
0111
0112 #define IL_TX_FIFO_AC0  0
0113 #define IL_TX_FIFO_AC1  1
0114 #define IL_TX_FIFO_AC2  2
0115 #define IL_TX_FIFO_AC3  3
0116 #define IL_TX_FIFO_HCCA_1   5
0117 #define IL_TX_FIFO_HCCA_2   6
0118 #define IL_TX_FIFO_NONE 7
0119
0120 #define IEEE80211_DATA_LEN              2304
0121 #define IEEE80211_4ADDR_LEN             30
0122 #define IEEE80211_HLEN                  (IEEE80211_4ADDR_LEN)
0123 #define IEEE80211_FRAME_LEN             (IEEE80211_DATA_LEN + IEEE80211_HLEN)
0124
0125 struct il3945_frame {
0126     union {
0127         struct ieee80211_hdr frame;
0128         struct il3945_tx_beacon_cmd beacon;
0129         u8 raw[IEEE80211_FRAME_LEN];
0130         u8 cmd[360];
0131     } u;
0132     struct list_head list;
0133 };
0134
0135 #define SUP_RATE_11A_MAX_NUM_CHANNELS  8
0136 #define SUP_RATE_11B_MAX_NUM_CHANNELS  4
0137 #define SUP_RATE_11G_MAX_NUM_CHANNELS  12
0138
0139 #define IL_SUPPORTED_RATES_IE_LEN         8
0140
0141 #define SCAN_INTERVAL 100
0142
0143 #define MAX_TID_COUNT        9
0144
0145 #define IL_INVALID_RATE     0xFF
0146 #define IL_INVALID_VALUE    -1
0147
0148 #define STA_PS_STATUS_WAKE             0
0149 #define STA_PS_STATUS_SLEEP            1
0150
0151 struct il3945_ibss_seq {
0152     u8 mac[ETH_ALEN];
0153     u16 seq_num;
0154     u16 frag_num;
0155     unsigned long packet_time;
0156     struct list_head list;
0157 };
0158
0159 #define IL_RX_HDR(x) ((struct il3945_rx_frame_hdr *)(\
0160                x->u.rx_frame.stats.payload + \
0161                x->u.rx_frame.stats.phy_count))
0162 #define IL_RX_END(x) ((struct il3945_rx_frame_end *)(\
0163                IL_RX_HDR(x)->payload + \
0164                le16_to_cpu(IL_RX_HDR(x)->len)))
0165 #define IL_RX_STATS(x) (&x->u.rx_frame.stats)
0166 #define IL_RX_DATA(x) (IL_RX_HDR(x)->payload)
0167
0168 /******************************************************************************
0169  *
0170  * Functions implemented in iwl3945-base.c which are forward declared here
0171  * for use by iwl-*.c
0172  *
0173  *****************************************************************************/
0174 int il3945_calc_db_from_ratio(int sig_ratio);
0175 void il3945_rx_replenish(void *data);
0176 void il3945_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq);
0177 unsigned int il3945_fill_beacon_frame(struct il_priv *il,
0178                       struct ieee80211_hdr *hdr, int left);
0179 int il3945_dump_nic_event_log(struct il_priv *il, bool full_log, char **buf,
0180                   bool display);
0181 void il3945_dump_nic_error_log(struct il_priv *il);
0182
0183 /******************************************************************************
0184  *
0185  * Functions implemented in iwl-[34]*.c which are forward declared here
0186  * for use by iwl3945-base.c
0187  *
0188  * NOTE:  The implementation of these functions are hardware specific
0189  * which is why they are in the hardware specific files (vs. iwl-base.c)
0190  *
0191  * Naming convention --
0192  * il3945_         <-- Its part of iwlwifi (should be changed to il3945_)
0193  * il3945_hw_      <-- Hardware specific (implemented in iwl-XXXX.c by all HW)
0194  * iwlXXXX_     <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
0195  * il3945_bg_      <-- Called from work queue context
0196  * il3945_mac_     <-- mac80211 callback
0197  *
0198  ****************************************************************************/
0199 void il3945_hw_handler_setup(struct il_priv *il);
0200 void il3945_hw_setup_deferred_work(struct il_priv *il);
0201 void il3945_hw_cancel_deferred_work(struct il_priv *il);
0202 int il3945_hw_rxq_stop(struct il_priv *il);
0203 int il3945_hw_set_hw_params(struct il_priv *il);
0204 int il3945_hw_nic_init(struct il_priv *il);
0205 int il3945_hw_nic_stop_master(struct il_priv *il);
0206 void il3945_hw_txq_ctx_free(struct il_priv *il);
0207 void il3945_hw_txq_ctx_stop(struct il_priv *il);
0208 int il3945_hw_nic_reset(struct il_priv *il);
0209 int il3945_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
0210                     dma_addr_t addr, u16 len, u8 reset, u8 pad);
0211 void il3945_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq);
0212 int il3945_hw_get_temperature(struct il_priv *il);
0213 int il3945_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq);
0214 unsigned int il3945_hw_get_beacon_cmd(struct il_priv *il,
0215                       struct il3945_frame *frame, u8 rate);
0216 void il3945_hw_build_tx_cmd_rate(struct il_priv *il, struct il_device_cmd *cmd,
0217                  struct ieee80211_tx_info *info,
0218                  struct ieee80211_hdr *hdr, int sta_id);
0219 int il3945_hw_reg_send_txpower(struct il_priv *il);
0220 int il3945_hw_reg_set_txpower(struct il_priv *il, s8 power);
0221 void il3945_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb);
0222 void il3945_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb);
0223 void il3945_disable_events(struct il_priv *il);
0224 int il4965_get_temperature(const struct il_priv *il);
0225 void il3945_post_associate(struct il_priv *il);
0226 void il3945_config_ap(struct il_priv *il);
0227
0228 int il3945_commit_rxon(struct il_priv *il);
0229
0230 /**
0231  * il3945_hw_find_station - Find station id for a given BSSID
0232  * @bssid: MAC address of station ID to find
0233  *
0234  * NOTE:  This should not be hardware specific but the code has
0235  * not yet been merged into a single common layer for managing the
0236  * station tables.
0237  */
0238 u8 il3945_hw_find_station(struct il_priv *il, const u8 *bssid);
0239
0240 __le32 il3945_get_antenna_flags(const struct il_priv *il);
0241 int il3945_init_hw_rate_table(struct il_priv *il);
0242 void il3945_reg_txpower_periodic(struct il_priv *il);
0243 int il3945_txpower_set_from_eeprom(struct il_priv *il);
0244
0245 int il3945_rs_next_rate(struct il_priv *il, int rate);
0246
0247 /* scanning */
0248 int il3945_request_scan(struct il_priv *il, struct ieee80211_vif *vif);
0249 void il3945_post_scan(struct il_priv *il);
0250
0251 /* rates */
0252 extern const struct il3945_rate_info il3945_rates[RATE_COUNT_3945];
0253
0254 /* RSSI to dBm */
0255 #define IL39_RSSI_OFFSET    95
0256
0257 /*
0258  * EEPROM related constants, enums, and structures.
0259  */
0260 #define EEPROM_SKU_CAP_OP_MODE_MRC                      (1 << 7)
0261
0262 /*
0263  * Mapping of a Tx power level, at factory calibration temperature,
0264  *   to a radio/DSP gain table idx.
0265  * One for each of 5 "sample" power levels in each band.
0266  * v_det is measured at the factory, using the 3945's built-in power amplifier
0267  *   (PA) output voltage detector.  This same detector is used during Tx of
0268  *   long packets in normal operation to provide feedback as to proper output
0269  *   level.
0270  * Data copied from EEPROM.
0271  * DO NOT ALTER THIS STRUCTURE!!!
0272  */
0273 struct il3945_eeprom_txpower_sample {
0274     u8 gain_idx;        /* idx into power (gain) setup table ... */
0275     s8 power;       /* ... for this pwr level for this chnl group */
0276     u16 v_det;      /* PA output voltage */
0277 } __packed;
0278
0279 /*
0280  * Mappings of Tx power levels -> nominal radio/DSP gain table idxes.
0281  * One for each channel group (a.k.a. "band") (1 for BG, 4 for A).
0282  * Tx power setup code interpolates between the 5 "sample" power levels
0283  *    to determine the nominal setup for a requested power level.
0284  * Data copied from EEPROM.
0285  * DO NOT ALTER THIS STRUCTURE!!!
0286  */
0287 struct il3945_eeprom_txpower_group {
0288     struct il3945_eeprom_txpower_sample samples[5]; /* 5 power levels */
0289     s32 a, b, c, d, e;  /* coefficients for voltage->power
0290                  * formula (signed) */
0291     s32 Fa, Fb, Fc, Fd, Fe; /* these modify coeffs based on
0292                  * frequency (signed) */
0293     s8 saturation_power;    /* highest power possible by h/w in this
0294                  * band */
0295     u8 group_channel;   /* "representative" channel # in this band */
0296     s16 temperature;    /* h/w temperature at factory calib this band
0297                  * (signed) */
0298 } __packed;
0299
0300 /*
0301  * Temperature-based Tx-power compensation data, not band-specific.
0302  * These coefficients are use to modify a/b/c/d/e coeffs based on
0303  *   difference between current temperature and factory calib temperature.
0304  * Data copied from EEPROM.
0305  */
0306 struct il3945_eeprom_temperature_corr {
0307     u32 Ta;
0308     u32 Tb;
0309     u32 Tc;
0310     u32 Td;
0311     u32 Te;
0312 } __packed;
0313
0314 /*
0315  * EEPROM map
0316  */
0317 struct il3945_eeprom {
0318     u8 reserved0[16];
0319     u16 device_id;      /* abs.ofs: 16 */
0320     u8 reserved1[2];
0321     u16 pmc;        /* abs.ofs: 20 */
0322     u8 reserved2[20];
0323     u8 mac_address[6];  /* abs.ofs: 42 */
0324     u8 reserved3[58];
0325     u16 board_revision; /* abs.ofs: 106 */
0326     u8 reserved4[11];
0327     u8 board_pba_number[9]; /* abs.ofs: 119 */
0328     u8 reserved5[8];
0329     u16 version;        /* abs.ofs: 136 */
0330     u8 sku_cap;     /* abs.ofs: 138 */
0331     u8 leds_mode;       /* abs.ofs: 139 */
0332     u16 oem_mode;
0333     u16 wowlan_mode;    /* abs.ofs: 142 */
0334     u16 leds_time_interval; /* abs.ofs: 144 */
0335     u8 leds_off_time;   /* abs.ofs: 146 */
0336     u8 leds_on_time;    /* abs.ofs: 147 */
0337     u8 almgor_m_version;    /* abs.ofs: 148 */
0338     u8 antenna_switch_type; /* abs.ofs: 149 */
0339     u8 reserved6[42];
0340     u8 sku_id[4];       /* abs.ofs: 192 */
0341
0342 /*
0343  * Per-channel regulatory data.
0344  *
0345  * Each channel that *might* be supported by 3945 has a fixed location
0346  * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
0347  * txpower (MSB).
0348  *
0349  * Entries immediately below are for 20 MHz channel width.
0350  *
0351  * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
0352  */
0353     u16 band_1_count;   /* abs.ofs: 196 */
0354     struct il_eeprom_channel band_1_channels[14];   /* abs.ofs: 198 */
0355
0356 /*
0357  * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
0358  * 5.0 GHz channels 7, 8, 11, 12, 16
0359  * (4915-5080MHz) (none of these is ever supported)
0360  */
0361     u16 band_2_count;   /* abs.ofs: 226 */
0362     struct il_eeprom_channel band_2_channels[13];   /* abs.ofs: 228 */
0363
0364 /*
0365  * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
0366  * (5170-5320MHz)
0367  */
0368     u16 band_3_count;   /* abs.ofs: 254 */
0369     struct il_eeprom_channel band_3_channels[12];   /* abs.ofs: 256 */
0370
0371 /*
0372  * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
0373  * (5500-5700MHz)
0374  */
0375     u16 band_4_count;   /* abs.ofs: 280 */
0376     struct il_eeprom_channel band_4_channels[11];   /* abs.ofs: 282 */
0377
0378 /*
0379  * 5.7 GHz channels 145, 149, 153, 157, 161, 165
0380  * (5725-5825MHz)
0381  */
0382     u16 band_5_count;   /* abs.ofs: 304 */
0383     struct il_eeprom_channel band_5_channels[6];    /* abs.ofs: 306 */
0384
0385     u8 reserved9[194];
0386
0387 /*
0388  * 3945 Txpower calibration data.
0389  */
0390 #define IL_NUM_TX_CALIB_GROUPS 5
0391     struct il3945_eeprom_txpower_group groups[IL_NUM_TX_CALIB_GROUPS];
0392 /* abs.ofs: 512 */
0393     struct il3945_eeprom_temperature_corr corrections;  /* abs.ofs: 832 */
0394     u8 reserved16[172]; /* fill out to full 1024 byte block */
0395 } __packed;
0396
0397 #define IL3945_EEPROM_IMG_SIZE 1024
0398
0399 /* End of EEPROM */
0400
0401 #define PCI_CFG_REV_ID_BIT_BASIC_SKU                (0x40)  /* bit 6    */
0402 #define PCI_CFG_REV_ID_BIT_RTP                      (0x80)  /* bit 7    */
0403
0404 /* 4 DATA + 1 CMD. There are 2 HCCA queues that are not used. */
0405 #define IL39_NUM_QUEUES        5
0406 #define IL39_CMD_QUEUE_NUM  4
0407
0408 #define IL_DEFAULT_TX_RETRY  15
0409
0410 /*********************************************/
0411
0412 #define RFD_SIZE                              4
0413 #define NUM_TFD_CHUNKS                        4
0414
0415 #define TFD_CTL_COUNT_SET(n)       (n << 24)
0416 #define TFD_CTL_COUNT_GET(ctl)     ((ctl >> 24) & 7)
0417 #define TFD_CTL_PAD_SET(n)         (n << 28)
0418 #define TFD_CTL_PAD_GET(ctl)       (ctl >> 28)
0419
0420 /* Sizes and addresses for instruction and data memory (SRAM) in
0421  * 3945's embedded processor.  Driver access is via HBUS_TARG_MEM_* regs. */
0422 #define IL39_RTC_INST_LOWER_BOUND       (0x000000)
0423 #define IL39_RTC_INST_UPPER_BOUND       (0x014000)
0424
0425 #define IL39_RTC_DATA_LOWER_BOUND       (0x800000)
0426 #define IL39_RTC_DATA_UPPER_BOUND       (0x808000)
0427
0428 #define IL39_RTC_INST_SIZE (IL39_RTC_INST_UPPER_BOUND - \
0429                 IL39_RTC_INST_LOWER_BOUND)
0430 #define IL39_RTC_DATA_SIZE (IL39_RTC_DATA_UPPER_BOUND - \
0431                 IL39_RTC_DATA_LOWER_BOUND)
0432
0433 #define IL39_MAX_INST_SIZE IL39_RTC_INST_SIZE
0434 #define IL39_MAX_DATA_SIZE IL39_RTC_DATA_SIZE
0435
0436 /* Size of uCode instruction memory in bootstrap state machine */
0437 #define IL39_MAX_BSM_SIZE IL39_RTC_INST_SIZE
0438
0439 static inline int
0440 il3945_hw_valid_rtc_data_addr(u32 addr)
0441 {
0442     return (addr >= IL39_RTC_DATA_LOWER_BOUND &&
0443         addr < IL39_RTC_DATA_UPPER_BOUND);
0444 }
0445
0446 /* Base physical address of il3945_shared is provided to FH39_TSSR_CBB_BASE
0447  * and &il3945_shared.rx_read_ptr[0] is provided to FH39_RCSR_RPTR_ADDR(0) */
0448 struct il3945_shared {
0449     __le32 tx_base_ptr[8];
0450 } __packed;
0451
0452 /************************************/
0453 /* iwl3945 Flow Handler Definitions */
0454 /************************************/
0455
0456 /**
0457  * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
0458  * Addresses are offsets from device's PCI hardware base address.
0459  */
0460 #define FH39_MEM_LOWER_BOUND                   (0x0800)
0461 #define FH39_MEM_UPPER_BOUND                   (0x1000)
0462
0463 #define FH39_CBCC_TBL       (FH39_MEM_LOWER_BOUND + 0x140)
0464 #define FH39_TFDB_TBL       (FH39_MEM_LOWER_BOUND + 0x180)
0465 #define FH39_RCSR_TBL       (FH39_MEM_LOWER_BOUND + 0x400)
0466 #define FH39_RSSR_TBL       (FH39_MEM_LOWER_BOUND + 0x4c0)
0467 #define FH39_TCSR_TBL       (FH39_MEM_LOWER_BOUND + 0x500)
0468 #define FH39_TSSR_TBL       (FH39_MEM_LOWER_BOUND + 0x680)
0469
0470 /* TFDB (Transmit Frame Buffer Descriptor) */
0471 #define FH39_TFDB(_ch, buf)         (FH39_TFDB_TBL + \
0472                          ((_ch) * 2 + (buf)) * 0x28)
0473 #define FH39_TFDB_CHNL_BUF_CTRL_REG(_ch)    (FH39_TFDB_TBL + 0x50 * (_ch))
0474
0475 /* CBCC channel is [0,2] */
0476 #define FH39_CBCC(_ch)      (FH39_CBCC_TBL + (_ch) * 0x8)
0477 #define FH39_CBCC_CTRL(_ch) (FH39_CBCC(_ch) + 0x00)
0478 #define FH39_CBCC_BASE(_ch) (FH39_CBCC(_ch) + 0x04)
0479
0480 /* RCSR channel is [0,2] */
0481 #define FH39_RCSR(_ch)          (FH39_RCSR_TBL + (_ch) * 0x40)
0482 #define FH39_RCSR_CONFIG(_ch)       (FH39_RCSR(_ch) + 0x00)
0483 #define FH39_RCSR_RBD_BASE(_ch)     (FH39_RCSR(_ch) + 0x04)
0484 #define FH39_RCSR_WPTR(_ch)     (FH39_RCSR(_ch) + 0x20)
0485 #define FH39_RCSR_RPTR_ADDR(_ch)    (FH39_RCSR(_ch) + 0x24)
0486
0487 #define FH39_RSCSR_CHNL0_WPTR       (FH39_RCSR_WPTR(0))
0488
0489 /* RSSR */
0490 #define FH39_RSSR_CTRL          (FH39_RSSR_TBL + 0x000)
0491 #define FH39_RSSR_STATUS        (FH39_RSSR_TBL + 0x004)
0492
0493 /* TCSR */
0494 #define FH39_TCSR(_ch)          (FH39_TCSR_TBL + (_ch) * 0x20)
0495 #define FH39_TCSR_CONFIG(_ch)       (FH39_TCSR(_ch) + 0x00)
0496 #define FH39_TCSR_CREDIT(_ch)       (FH39_TCSR(_ch) + 0x04)
0497 #define FH39_TCSR_BUFF_STTS(_ch)    (FH39_TCSR(_ch) + 0x08)
0498
0499 /* TSSR */
0500 #define FH39_TSSR_CBB_BASE        (FH39_TSSR_TBL + 0x000)
0501 #define FH39_TSSR_MSG_CONFIG      (FH39_TSSR_TBL + 0x008)
0502 #define FH39_TSSR_TX_STATUS       (FH39_TSSR_TBL + 0x010)
0503
0504 /* DBM */
0505
0506 #define FH39_SRVC_CHNL                            (6)
0507
0508 #define FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE     (20)
0509 #define FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH      (4)
0510
0511 #define FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN    (0x08000000)
0512
0513 #define FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE        (0x80000000)
0514
0515 #define FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE           (0x20000000)
0516
0517 #define FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128       (0x01000000)
0518
0519 #define FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST       (0x00001000)
0520
0521 #define FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH         (0x00000000)
0522
0523 #define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF        (0x00000000)
0524 #define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER     (0x00000001)
0525
0526 #define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL  (0x00000000)
0527 #define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL   (0x00000008)
0528
0529 #define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD     (0x00200000)
0530
0531 #define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT      (0x00000000)
0532
0533 #define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE      (0x00000000)
0534 #define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE     (0x80000000)
0535
0536 #define FH39_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID        (0x00004000)
0537
0538 #define FH39_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR     (0x00000001)
0539
0540 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON    (0xFF000000)
0541 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON    (0x00FF0000)
0542
0543 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B  (0x00000400)
0544
0545 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON     (0x00000100)
0546 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON     (0x00000080)
0547
0548 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH   (0x00000020)
0549 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH     (0x00000005)
0550
0551 #define FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch) (BIT(_ch) << 24)
0552 #define FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch)    (BIT(_ch) << 16)
0553
0554 #define FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_ch) \
0555     (FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch) | \
0556      FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch))
0557
0558 #define FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE         (0x01000000)
0559
0560 struct il3945_tfd_tb {
0561     __le32 addr;
0562     __le32 len;
0563 } __packed;
0564
0565 struct il3945_tfd {
0566     __le32 control_flags;
0567     struct il3945_tfd_tb tbs[4];
0568     u8 __pad[28];
0569 } __packed;
0570
0571 #ifdef CONFIG_IWLEGACY_DEBUGFS
0572 extern const struct il_debugfs_ops il3945_debugfs_ops;
0573 #endif
0574
0575 #endif