0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0016
0017 #include <linux/kernel.h>
0018 #include <linux/module.h>
0019 #include <linux/init.h>
0020 #include <linux/pci.h>
0021 #include <linux/slab.h>
0022 #include <linux/dma-mapping.h>
0023 #include <linux/delay.h>
0024 #include <linux/sched.h>
0025 #include <linux/skbuff.h>
0026 #include <linux/netdevice.h>
0027 #include <linux/firmware.h>
0028 #include <linux/etherdevice.h>
0029 #include <linux/if_arp.h>
0030
0031 #include <net/ieee80211_radiotap.h>
0032 #include <net/mac80211.h>
0033
0034 #include <asm/div64.h>
0035
0036 #define DRV_NAME "iwl3945"
0037
0038 #include "commands.h"
0039 #include "common.h"
0040 #include "3945.h"
0041 #include "iwl-spectrum.h"
0042
0043
0044
0045
0046
0047 #define DRV_DESCRIPTION \
0048 "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
0049
0050 #ifdef CONFIG_IWLEGACY_DEBUG
0051 #define VD "d"
0052 #else
0053 #define VD
0054 #endif
0055
0056
0057
0058
0059
0060
0061 #define DRV_VERSION IWLWIFI_VERSION VD "s"
0062 #define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
0063 #define DRV_AUTHOR "<ilw@linux.intel.com>"
0064
0065 MODULE_DESCRIPTION(DRV_DESCRIPTION);
0066 MODULE_VERSION(DRV_VERSION);
0067 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
0068 MODULE_LICENSE("GPL");
0069
0070
0071 struct il_mod_params il3945_mod_params = {
0072 .sw_crypto = 1,
0073 .restart_fw = 1,
0074 .disable_hw_scan = 1,
0075
0076 };
0077
0078
0079
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089 __le32
0090 il3945_get_antenna_flags(const struct il_priv *il)
0091 {
0092 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
0093
0094 switch (il3945_mod_params.antenna) {
0095 case IL_ANTENNA_DIVERSITY:
0096 return 0;
0097
0098 case IL_ANTENNA_MAIN:
0099 if (eeprom->antenna_switch_type)
0100 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
0101 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
0102
0103 case IL_ANTENNA_AUX:
0104 if (eeprom->antenna_switch_type)
0105 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
0106 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
0107 }
0108
0109
0110 IL_ERR("Bad antenna selector value (0x%x)\n",
0111 il3945_mod_params.antenna);
0112
0113 return 0;
0114 }
0115
0116 static int
0117 il3945_set_ccmp_dynamic_key_info(struct il_priv *il,
0118 struct ieee80211_key_conf *keyconf, u8 sta_id)
0119 {
0120 unsigned long flags;
0121 __le16 key_flags = 0;
0122 int ret;
0123
0124 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
0125 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
0126
0127 if (sta_id == il->hw_params.bcast_id)
0128 key_flags |= STA_KEY_MULTICAST_MSK;
0129
0130 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
0131 keyconf->hw_key_idx = keyconf->keyidx;
0132 key_flags &= ~STA_KEY_FLG_INVALID;
0133
0134 spin_lock_irqsave(&il->sta_lock, flags);
0135 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
0136 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
0137 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
0138
0139 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, keyconf->keylen);
0140
0141 if ((il->stations[sta_id].sta.key.
0142 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
0143 il->stations[sta_id].sta.key.key_offset =
0144 il_get_free_ucode_key_idx(il);
0145
0146
0147
0148 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
0149 "no space for a new key");
0150
0151 il->stations[sta_id].sta.key.key_flags = key_flags;
0152 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
0153 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
0154
0155 D_INFO("hwcrypto: modify ucode station key info\n");
0156
0157 ret = il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
0158
0159 spin_unlock_irqrestore(&il->sta_lock, flags);
0160
0161 return ret;
0162 }
0163
0164 static int
0165 il3945_set_tkip_dynamic_key_info(struct il_priv *il,
0166 struct ieee80211_key_conf *keyconf, u8 sta_id)
0167 {
0168 return -EOPNOTSUPP;
0169 }
0170
0171 static int
0172 il3945_set_wep_dynamic_key_info(struct il_priv *il,
0173 struct ieee80211_key_conf *keyconf, u8 sta_id)
0174 {
0175 return -EOPNOTSUPP;
0176 }
0177
0178 static int
0179 il3945_clear_sta_key_info(struct il_priv *il, u8 sta_id)
0180 {
0181 unsigned long flags;
0182 struct il_addsta_cmd sta_cmd;
0183
0184 spin_lock_irqsave(&il->sta_lock, flags);
0185 memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key));
0186 memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo));
0187 il->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
0188 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
0189 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
0190 memcpy(&sta_cmd, &il->stations[sta_id].sta,
0191 sizeof(struct il_addsta_cmd));
0192 spin_unlock_irqrestore(&il->sta_lock, flags);
0193
0194 D_INFO("hwcrypto: clear ucode station key info\n");
0195 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
0196 }
0197
0198 static int
0199 il3945_set_dynamic_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
0200 u8 sta_id)
0201 {
0202 int ret = 0;
0203
0204 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
0205
0206 switch (keyconf->cipher) {
0207 case WLAN_CIPHER_SUITE_CCMP:
0208 ret = il3945_set_ccmp_dynamic_key_info(il, keyconf, sta_id);
0209 break;
0210 case WLAN_CIPHER_SUITE_TKIP:
0211 ret = il3945_set_tkip_dynamic_key_info(il, keyconf, sta_id);
0212 break;
0213 case WLAN_CIPHER_SUITE_WEP40:
0214 case WLAN_CIPHER_SUITE_WEP104:
0215 ret = il3945_set_wep_dynamic_key_info(il, keyconf, sta_id);
0216 break;
0217 default:
0218 IL_ERR("Unknown alg: %s alg=%x\n", __func__, keyconf->cipher);
0219 ret = -EINVAL;
0220 }
0221
0222 D_WEP("Set dynamic key: alg=%x len=%d idx=%d sta=%d ret=%d\n",
0223 keyconf->cipher, keyconf->keylen, keyconf->keyidx, sta_id, ret);
0224
0225 return ret;
0226 }
0227
0228 static int
0229 il3945_remove_static_key(struct il_priv *il)
0230 {
0231 return -EOPNOTSUPP;
0232 }
0233
0234 static int
0235 il3945_set_static_key(struct il_priv *il, struct ieee80211_key_conf *key)
0236 {
0237 if (key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
0238 key->cipher == WLAN_CIPHER_SUITE_WEP104)
0239 return -EOPNOTSUPP;
0240
0241 IL_ERR("Static key invalid: cipher %x\n", key->cipher);
0242 return -EINVAL;
0243 }
0244
0245 static void
0246 il3945_clear_free_frames(struct il_priv *il)
0247 {
0248 struct list_head *element;
0249
0250 D_INFO("%d frames on pre-allocated heap on clear.\n", il->frames_count);
0251
0252 while (!list_empty(&il->free_frames)) {
0253 element = il->free_frames.next;
0254 list_del(element);
0255 kfree(list_entry(element, struct il3945_frame, list));
0256 il->frames_count--;
0257 }
0258
0259 if (il->frames_count) {
0260 IL_WARN("%d frames still in use. Did we lose one?\n",
0261 il->frames_count);
0262 il->frames_count = 0;
0263 }
0264 }
0265
0266 static struct il3945_frame *
0267 il3945_get_free_frame(struct il_priv *il)
0268 {
0269 struct il3945_frame *frame;
0270 struct list_head *element;
0271 if (list_empty(&il->free_frames)) {
0272 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
0273 if (!frame) {
0274 IL_ERR("Could not allocate frame!\n");
0275 return NULL;
0276 }
0277
0278 il->frames_count++;
0279 return frame;
0280 }
0281
0282 element = il->free_frames.next;
0283 list_del(element);
0284 return list_entry(element, struct il3945_frame, list);
0285 }
0286
0287 static void
0288 il3945_free_frame(struct il_priv *il, struct il3945_frame *frame)
0289 {
0290 memset(frame, 0, sizeof(*frame));
0291 list_add(&frame->list, &il->free_frames);
0292 }
0293
0294 unsigned int
0295 il3945_fill_beacon_frame(struct il_priv *il, struct ieee80211_hdr *hdr,
0296 int left)
0297 {
0298
0299 if (!il_is_associated(il) || !il->beacon_skb)
0300 return 0;
0301
0302 if (il->beacon_skb->len > left)
0303 return 0;
0304
0305 memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
0306
0307 return il->beacon_skb->len;
0308 }
0309
0310 static int
0311 il3945_send_beacon_cmd(struct il_priv *il)
0312 {
0313 struct il3945_frame *frame;
0314 unsigned int frame_size;
0315 int rc;
0316 u8 rate;
0317
0318 frame = il3945_get_free_frame(il);
0319
0320 if (!frame) {
0321 IL_ERR("Could not obtain free frame buffer for beacon "
0322 "command.\n");
0323 return -ENOMEM;
0324 }
0325
0326 rate = il_get_lowest_plcp(il);
0327
0328 frame_size = il3945_hw_get_beacon_cmd(il, frame, rate);
0329
0330 rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]);
0331
0332 il3945_free_frame(il, frame);
0333
0334 return rc;
0335 }
0336
0337 static void
0338 il3945_unset_hw_params(struct il_priv *il)
0339 {
0340 if (il->_3945.shared_virt)
0341 dma_free_coherent(&il->pci_dev->dev,
0342 sizeof(struct il3945_shared),
0343 il->_3945.shared_virt, il->_3945.shared_phys);
0344 }
0345
0346 static void
0347 il3945_build_tx_cmd_hwcrypto(struct il_priv *il, struct ieee80211_tx_info *info,
0348 struct il_device_cmd *cmd,
0349 struct sk_buff *skb_frag, int sta_id)
0350 {
0351 struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
0352 struct il_hw_key *keyinfo = &il->stations[sta_id].keyinfo;
0353
0354 tx_cmd->sec_ctl = 0;
0355
0356 switch (keyinfo->cipher) {
0357 case WLAN_CIPHER_SUITE_CCMP:
0358 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
0359 memcpy(tx_cmd->key, keyinfo->key, keyinfo->keylen);
0360 D_TX("tx_cmd with AES hwcrypto\n");
0361 break;
0362
0363 case WLAN_CIPHER_SUITE_TKIP:
0364 break;
0365
0366 case WLAN_CIPHER_SUITE_WEP104:
0367 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
0368 fallthrough;
0369 case WLAN_CIPHER_SUITE_WEP40:
0370 tx_cmd->sec_ctl |=
0371 TX_CMD_SEC_WEP | (info->control.hw_key->
0372 hw_key_idx & TX_CMD_SEC_MSK) <<
0373 TX_CMD_SEC_SHIFT;
0374
0375 memcpy(&tx_cmd->key[3], keyinfo->key, keyinfo->keylen);
0376
0377 D_TX("Configuring packet for WEP encryption " "with key %d\n",
0378 info->control.hw_key->hw_key_idx);
0379 break;
0380
0381 default:
0382 IL_ERR("Unknown encode cipher %x\n", keyinfo->cipher);
0383 break;
0384 }
0385 }
0386
0387
0388
0389
0390 static void
0391 il3945_build_tx_cmd_basic(struct il_priv *il, struct il_device_cmd *cmd,
0392 struct ieee80211_tx_info *info,
0393 struct ieee80211_hdr *hdr, u8 std_id)
0394 {
0395 struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
0396 __le32 tx_flags = tx_cmd->tx_flags;
0397 __le16 fc = hdr->frame_control;
0398
0399 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
0400 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
0401 tx_flags |= TX_CMD_FLG_ACK_MSK;
0402 if (ieee80211_is_mgmt(fc))
0403 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
0404 if (ieee80211_is_probe_resp(fc) &&
0405 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
0406 tx_flags |= TX_CMD_FLG_TSF_MSK;
0407 } else {
0408 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
0409 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
0410 }
0411
0412 tx_cmd->sta_id = std_id;
0413 if (ieee80211_has_morefrags(fc))
0414 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
0415
0416 if (ieee80211_is_data_qos(fc)) {
0417 u8 *qc = ieee80211_get_qos_ctl(hdr);
0418 tx_cmd->tid_tspec = qc[0] & 0xf;
0419 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
0420 } else {
0421 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
0422 }
0423
0424 il_tx_cmd_protection(il, info, fc, &tx_flags);
0425
0426 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
0427 if (ieee80211_is_mgmt(fc)) {
0428 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
0429 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
0430 else
0431 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
0432 } else {
0433 tx_cmd->timeout.pm_frame_timeout = 0;
0434 }
0435
0436 tx_cmd->driver_txop = 0;
0437 tx_cmd->tx_flags = tx_flags;
0438 tx_cmd->next_frame_len = 0;
0439 }
0440
0441
0442
0443
0444 static int
0445 il3945_tx_skb(struct il_priv *il,
0446 struct ieee80211_sta *sta,
0447 struct sk_buff *skb)
0448 {
0449 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
0450 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
0451 struct il3945_tx_cmd *tx_cmd;
0452 struct il_tx_queue *txq = NULL;
0453 struct il_queue *q = NULL;
0454 struct il_device_cmd *out_cmd;
0455 struct il_cmd_meta *out_meta;
0456 dma_addr_t phys_addr;
0457 dma_addr_t txcmd_phys;
0458 int txq_id = skb_get_queue_mapping(skb);
0459 u16 len, idx, hdr_len;
0460 u16 firstlen, secondlen;
0461 u8 sta_id;
0462 u8 tid = 0;
0463 __le16 fc;
0464 u8 wait_write_ptr = 0;
0465 unsigned long flags;
0466
0467 spin_lock_irqsave(&il->lock, flags);
0468 if (il_is_rfkill(il)) {
0469 D_DROP("Dropping - RF KILL\n");
0470 goto drop_unlock;
0471 }
0472
0473 if ((ieee80211_get_tx_rate(il->hw, info)->hw_value & 0xFF) ==
0474 IL_INVALID_RATE) {
0475 IL_ERR("ERROR: No TX rate available.\n");
0476 goto drop_unlock;
0477 }
0478
0479 fc = hdr->frame_control;
0480
0481 #ifdef CONFIG_IWLEGACY_DEBUG
0482 if (ieee80211_is_auth(fc))
0483 D_TX("Sending AUTH frame\n");
0484 else if (ieee80211_is_assoc_req(fc))
0485 D_TX("Sending ASSOC frame\n");
0486 else if (ieee80211_is_reassoc_req(fc))
0487 D_TX("Sending REASSOC frame\n");
0488 #endif
0489
0490 spin_unlock_irqrestore(&il->lock, flags);
0491
0492 hdr_len = ieee80211_hdrlen(fc);
0493
0494
0495 sta_id = il_sta_id_or_broadcast(il, sta);
0496 if (sta_id == IL_INVALID_STATION) {
0497 D_DROP("Dropping - INVALID STATION: %pM\n", hdr->addr1);
0498 goto drop;
0499 }
0500
0501 D_RATE("station Id %d\n", sta_id);
0502
0503 if (ieee80211_is_data_qos(fc)) {
0504 u8 *qc = ieee80211_get_qos_ctl(hdr);
0505 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
0506 if (unlikely(tid >= MAX_TID_COUNT))
0507 goto drop;
0508 }
0509
0510
0511 txq = &il->txq[txq_id];
0512 q = &txq->q;
0513
0514 if ((il_queue_space(q) < q->high_mark))
0515 goto drop;
0516
0517 spin_lock_irqsave(&il->lock, flags);
0518
0519 idx = il_get_cmd_idx(q, q->write_ptr, 0);
0520
0521 txq->skbs[q->write_ptr] = skb;
0522
0523
0524 out_cmd = txq->cmd[idx];
0525 out_meta = &txq->meta[idx];
0526 tx_cmd = (struct il3945_tx_cmd *)out_cmd->cmd.payload;
0527 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
0528 memset(tx_cmd, 0, sizeof(*tx_cmd));
0529
0530
0531
0532
0533
0534
0535
0536 out_cmd->hdr.cmd = C_TX;
0537 out_cmd->hdr.sequence =
0538 cpu_to_le16((u16)
0539 (QUEUE_TO_SEQ(txq_id) | IDX_TO_SEQ(q->write_ptr)));
0540
0541
0542 memcpy(tx_cmd->hdr, hdr, hdr_len);
0543
0544 if (info->control.hw_key)
0545 il3945_build_tx_cmd_hwcrypto(il, info, out_cmd, skb, sta_id);
0546
0547
0548 il3945_build_tx_cmd_basic(il, out_cmd, info, hdr, sta_id);
0549
0550 il3945_hw_build_tx_cmd_rate(il, out_cmd, info, hdr, sta_id);
0551
0552
0553 tx_cmd->len = cpu_to_le16((u16) skb->len);
0554
0555 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
0556 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
0557
0558
0559
0560
0561
0562
0563
0564
0565
0566
0567 len =
0568 sizeof(struct il3945_tx_cmd) + sizeof(struct il_cmd_header) +
0569 hdr_len;
0570 firstlen = (len + 3) & ~3;
0571
0572
0573
0574 txcmd_phys = dma_map_single(&il->pci_dev->dev, &out_cmd->hdr, firstlen,
0575 DMA_TO_DEVICE);
0576 if (unlikely(dma_mapping_error(&il->pci_dev->dev, txcmd_phys)))
0577 goto drop_unlock;
0578
0579
0580
0581 secondlen = skb->len - hdr_len;
0582 if (secondlen > 0) {
0583 phys_addr = dma_map_single(&il->pci_dev->dev, skb->data + hdr_len,
0584 secondlen, DMA_TO_DEVICE);
0585 if (unlikely(dma_mapping_error(&il->pci_dev->dev, phys_addr)))
0586 goto drop_unlock;
0587 }
0588
0589
0590
0591 il->ops->txq_attach_buf_to_tfd(il, txq, txcmd_phys, firstlen, 1, 0);
0592 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
0593 dma_unmap_len_set(out_meta, len, firstlen);
0594 if (secondlen > 0)
0595 il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, secondlen, 0,
0596 U32_PAD(secondlen));
0597
0598 if (!ieee80211_has_morefrags(hdr->frame_control)) {
0599 txq->need_update = 1;
0600 } else {
0601 wait_write_ptr = 1;
0602 txq->need_update = 0;
0603 }
0604
0605 il_update_stats(il, true, fc, skb->len);
0606
0607 D_TX("sequence nr = 0X%x\n", le16_to_cpu(out_cmd->hdr.sequence));
0608 D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
0609 il_print_hex_dump(il, IL_DL_TX, tx_cmd, sizeof(*tx_cmd));
0610 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd->hdr,
0611 ieee80211_hdrlen(fc));
0612
0613
0614 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
0615 il_txq_update_write_ptr(il, txq);
0616 spin_unlock_irqrestore(&il->lock, flags);
0617
0618 if (il_queue_space(q) < q->high_mark && il->mac80211_registered) {
0619 if (wait_write_ptr) {
0620 spin_lock_irqsave(&il->lock, flags);
0621 txq->need_update = 1;
0622 il_txq_update_write_ptr(il, txq);
0623 spin_unlock_irqrestore(&il->lock, flags);
0624 }
0625
0626 il_stop_queue(il, txq);
0627 }
0628
0629 return 0;
0630
0631 drop_unlock:
0632 spin_unlock_irqrestore(&il->lock, flags);
0633 drop:
0634 return -1;
0635 }
0636
0637 static int
0638 il3945_get_measurement(struct il_priv *il,
0639 struct ieee80211_measurement_params *params, u8 type)
0640 {
0641 struct il_spectrum_cmd spectrum;
0642 struct il_rx_pkt *pkt;
0643 struct il_host_cmd cmd = {
0644 .id = C_SPECTRUM_MEASUREMENT,
0645 .data = (void *)&spectrum,
0646 .flags = CMD_WANT_SKB,
0647 };
0648 u32 add_time = le64_to_cpu(params->start_time);
0649 int rc;
0650 int spectrum_resp_status;
0651 int duration = le16_to_cpu(params->duration);
0652
0653 if (il_is_associated(il))
0654 add_time =
0655 il_usecs_to_beacons(il,
0656 le64_to_cpu(params->start_time) -
0657 il->_3945.last_tsf,
0658 le16_to_cpu(il->timing.beacon_interval));
0659
0660 memset(&spectrum, 0, sizeof(spectrum));
0661
0662 spectrum.channel_count = cpu_to_le16(1);
0663 spectrum.flags =
0664 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
0665 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
0666 cmd.len = sizeof(spectrum);
0667 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
0668
0669 if (il_is_associated(il))
0670 spectrum.start_time =
0671 il_add_beacon_time(il, il->_3945.last_beacon_time, add_time,
0672 le16_to_cpu(il->timing.beacon_interval));
0673 else
0674 spectrum.start_time = 0;
0675
0676 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
0677 spectrum.channels[0].channel = params->channel;
0678 spectrum.channels[0].type = type;
0679 if (il->active.flags & RXON_FLG_BAND_24G_MSK)
0680 spectrum.flags |=
0681 RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
0682 RXON_FLG_TGG_PROTECT_MSK;
0683
0684 rc = il_send_cmd_sync(il, &cmd);
0685 if (rc)
0686 return rc;
0687
0688 pkt = (struct il_rx_pkt *)cmd.reply_page;
0689 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
0690 IL_ERR("Bad return from N_RX_ON_ASSOC command\n");
0691 rc = -EIO;
0692 }
0693
0694 spectrum_resp_status = le16_to_cpu(pkt->u.spectrum.status);
0695 switch (spectrum_resp_status) {
0696 case 0:
0697 if (pkt->u.spectrum.id != 0xff) {
0698 D_INFO("Replaced existing measurement: %d\n",
0699 pkt->u.spectrum.id);
0700 il->measurement_status &= ~MEASUREMENT_READY;
0701 }
0702 il->measurement_status |= MEASUREMENT_ACTIVE;
0703 rc = 0;
0704 break;
0705
0706 case 1:
0707 rc = -EAGAIN;
0708 break;
0709 }
0710
0711 il_free_pages(il, cmd.reply_page);
0712
0713 return rc;
0714 }
0715
0716 static void
0717 il3945_hdl_alive(struct il_priv *il, struct il_rx_buf *rxb)
0718 {
0719 struct il_rx_pkt *pkt = rxb_addr(rxb);
0720 struct il_alive_resp *palive;
0721 struct delayed_work *pwork;
0722
0723 palive = &pkt->u.alive_frame;
0724
0725 D_INFO("Alive ucode status 0x%08X revision " "0x%01X 0x%01X\n",
0726 palive->is_valid, palive->ver_type, palive->ver_subtype);
0727
0728 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
0729 D_INFO("Initialization Alive received.\n");
0730 memcpy(&il->card_alive_init, &pkt->u.alive_frame,
0731 sizeof(struct il_alive_resp));
0732 pwork = &il->init_alive_start;
0733 } else {
0734 D_INFO("Runtime Alive received.\n");
0735 memcpy(&il->card_alive, &pkt->u.alive_frame,
0736 sizeof(struct il_alive_resp));
0737 pwork = &il->alive_start;
0738 il3945_disable_events(il);
0739 }
0740
0741
0742
0743 if (palive->is_valid == UCODE_VALID_OK)
0744 queue_delayed_work(il->workqueue, pwork, msecs_to_jiffies(5));
0745 else
0746 IL_WARN("uCode did not respond OK.\n");
0747 }
0748
0749 static void
0750 il3945_hdl_add_sta(struct il_priv *il, struct il_rx_buf *rxb)
0751 {
0752 struct il_rx_pkt *pkt = rxb_addr(rxb);
0753
0754 D_RX("Received C_ADD_STA: 0x%02X\n", pkt->u.status);
0755 }
0756
0757 static void
0758 il3945_hdl_beacon(struct il_priv *il, struct il_rx_buf *rxb)
0759 {
0760 struct il_rx_pkt *pkt = rxb_addr(rxb);
0761 struct il3945_beacon_notif *beacon = &(pkt->u.beacon_status);
0762 #ifdef CONFIG_IWLEGACY_DEBUG
0763 u8 rate = beacon->beacon_notify_hdr.rate;
0764
0765 D_RX("beacon status %x retries %d iss %d " "tsf %d %d rate %d\n",
0766 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
0767 beacon->beacon_notify_hdr.failure_frame,
0768 le32_to_cpu(beacon->ibss_mgr_status),
0769 le32_to_cpu(beacon->high_tsf), le32_to_cpu(beacon->low_tsf), rate);
0770 #endif
0771
0772 il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
0773
0774 }
0775
0776
0777
0778 static void
0779 il3945_hdl_card_state(struct il_priv *il, struct il_rx_buf *rxb)
0780 {
0781 struct il_rx_pkt *pkt = rxb_addr(rxb);
0782 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
0783 unsigned long status = il->status;
0784
0785 IL_WARN("Card state received: HW:%s SW:%s\n",
0786 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
0787 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
0788
0789 _il_wr(il, CSR_UCODE_DRV_GP1_SET, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
0790
0791 if (flags & HW_CARD_DISABLED)
0792 set_bit(S_RFKILL, &il->status);
0793 else
0794 clear_bit(S_RFKILL, &il->status);
0795
0796 il_scan_cancel(il);
0797
0798 if ((test_bit(S_RFKILL, &status) !=
0799 test_bit(S_RFKILL, &il->status)))
0800 wiphy_rfkill_set_hw_state(il->hw->wiphy,
0801 test_bit(S_RFKILL, &il->status));
0802 else
0803 wake_up(&il->wait_command_queue);
0804 }
0805
0806
0807
0808
0809
0810
0811
0812
0813
0814
0815 static void
0816 il3945_setup_handlers(struct il_priv *il)
0817 {
0818 il->handlers[N_ALIVE] = il3945_hdl_alive;
0819 il->handlers[C_ADD_STA] = il3945_hdl_add_sta;
0820 il->handlers[N_ERROR] = il_hdl_error;
0821 il->handlers[N_CHANNEL_SWITCH] = il_hdl_csa;
0822 il->handlers[N_SPECTRUM_MEASUREMENT] = il_hdl_spectrum_measurement;
0823 il->handlers[N_PM_SLEEP] = il_hdl_pm_sleep;
0824 il->handlers[N_PM_DEBUG_STATS] = il_hdl_pm_debug_stats;
0825 il->handlers[N_BEACON] = il3945_hdl_beacon;
0826
0827
0828
0829
0830
0831
0832 il->handlers[C_STATS] = il3945_hdl_c_stats;
0833 il->handlers[N_STATS] = il3945_hdl_stats;
0834
0835 il_setup_rx_scan_handlers(il);
0836 il->handlers[N_CARD_STATE] = il3945_hdl_card_state;
0837
0838
0839 il3945_hw_handler_setup(il);
0840 }
0841
0842
0843
0844
0845
0846
0847
0848
0849
0850
0851
0852
0853
0854
0855
0856
0857
0858
0859
0860
0861
0862
0863
0864
0865
0866
0867
0868
0869
0870
0871
0872
0873
0874
0875
0876
0877
0878
0879
0880
0881
0882
0883
0884
0885
0886
0887
0888
0889
0890
0891
0892
0893
0894
0895
0896
0897
0898
0899
0900
0901
0902
0903
0904
0905
0906
0907
0908
0909 static inline __le32
0910 il3945_dma_addr2rbd_ptr(struct il_priv *il, dma_addr_t dma_addr)
0911 {
0912 return cpu_to_le32((u32) dma_addr);
0913 }
0914
0915
0916
0917
0918
0919
0920
0921
0922
0923
0924
0925
0926 static void
0927 il3945_rx_queue_restock(struct il_priv *il)
0928 {
0929 struct il_rx_queue *rxq = &il->rxq;
0930 struct list_head *element;
0931 struct il_rx_buf *rxb;
0932 unsigned long flags;
0933
0934 spin_lock_irqsave(&rxq->lock, flags);
0935 while (il_rx_queue_space(rxq) > 0 && rxq->free_count) {
0936
0937 element = rxq->rx_free.next;
0938 rxb = list_entry(element, struct il_rx_buf, list);
0939 list_del(element);
0940
0941
0942 rxq->bd[rxq->write] =
0943 il3945_dma_addr2rbd_ptr(il, rxb->page_dma);
0944 rxq->queue[rxq->write] = rxb;
0945 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
0946 rxq->free_count--;
0947 }
0948 spin_unlock_irqrestore(&rxq->lock, flags);
0949
0950
0951 if (rxq->free_count <= RX_LOW_WATERMARK)
0952 queue_work(il->workqueue, &il->rx_replenish);
0953
0954
0955
0956 if (rxq->write_actual != (rxq->write & ~0x7) ||
0957 abs(rxq->write - rxq->read) > 7) {
0958 spin_lock_irqsave(&rxq->lock, flags);
0959 rxq->need_update = 1;
0960 spin_unlock_irqrestore(&rxq->lock, flags);
0961 il_rx_queue_update_write_ptr(il, rxq);
0962 }
0963 }
0964
0965
0966
0967
0968
0969
0970
0971
0972
0973 static void
0974 il3945_rx_allocate(struct il_priv *il, gfp_t priority)
0975 {
0976 struct il_rx_queue *rxq = &il->rxq;
0977 struct list_head *element;
0978 struct il_rx_buf *rxb;
0979 struct page *page;
0980 dma_addr_t page_dma;
0981 unsigned long flags;
0982 gfp_t gfp_mask = priority;
0983
0984 while (1) {
0985 spin_lock_irqsave(&rxq->lock, flags);
0986 if (list_empty(&rxq->rx_used)) {
0987 spin_unlock_irqrestore(&rxq->lock, flags);
0988 return;
0989 }
0990 spin_unlock_irqrestore(&rxq->lock, flags);
0991
0992 if (rxq->free_count > RX_LOW_WATERMARK)
0993 gfp_mask |= __GFP_NOWARN;
0994
0995 if (il->hw_params.rx_page_order > 0)
0996 gfp_mask |= __GFP_COMP;
0997
0998
0999 page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
1000 if (!page) {
1001 if (net_ratelimit())
1002 D_INFO("Failed to allocate SKB buffer.\n");
1003 if (rxq->free_count <= RX_LOW_WATERMARK &&
1004 net_ratelimit())
1005 IL_ERR("Failed to allocate SKB buffer with %0x."
1006 "Only %u free buffers remaining.\n",
1007 priority, rxq->free_count);
1008
1009
1010
1011 break;
1012 }
1013
1014
1015 page_dma =
1016 dma_map_page(&il->pci_dev->dev, page, 0,
1017 PAGE_SIZE << il->hw_params.rx_page_order,
1018 DMA_FROM_DEVICE);
1019
1020 if (unlikely(dma_mapping_error(&il->pci_dev->dev, page_dma))) {
1021 __free_pages(page, il->hw_params.rx_page_order);
1022 break;
1023 }
1024
1025 spin_lock_irqsave(&rxq->lock, flags);
1026
1027 if (list_empty(&rxq->rx_used)) {
1028 spin_unlock_irqrestore(&rxq->lock, flags);
1029 dma_unmap_page(&il->pci_dev->dev, page_dma,
1030 PAGE_SIZE << il->hw_params.rx_page_order,
1031 DMA_FROM_DEVICE);
1032 __free_pages(page, il->hw_params.rx_page_order);
1033 return;
1034 }
1035
1036 element = rxq->rx_used.next;
1037 rxb = list_entry(element, struct il_rx_buf, list);
1038 list_del(element);
1039
1040 rxb->page = page;
1041 rxb->page_dma = page_dma;
1042 list_add_tail(&rxb->list, &rxq->rx_free);
1043 rxq->free_count++;
1044 il->alloc_rxb_page++;
1045
1046 spin_unlock_irqrestore(&rxq->lock, flags);
1047 }
1048 }
1049
1050 void
1051 il3945_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
1052 {
1053 unsigned long flags;
1054 int i;
1055 spin_lock_irqsave(&rxq->lock, flags);
1056 INIT_LIST_HEAD(&rxq->rx_free);
1057 INIT_LIST_HEAD(&rxq->rx_used);
1058
1059 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
1060
1061
1062 if (rxq->pool[i].page != NULL) {
1063 dma_unmap_page(&il->pci_dev->dev,
1064 rxq->pool[i].page_dma,
1065 PAGE_SIZE << il->hw_params.rx_page_order,
1066 DMA_FROM_DEVICE);
1067 __il_free_pages(il, rxq->pool[i].page);
1068 rxq->pool[i].page = NULL;
1069 }
1070 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
1071 }
1072
1073
1074
1075 rxq->read = rxq->write = 0;
1076 rxq->write_actual = 0;
1077 rxq->free_count = 0;
1078 spin_unlock_irqrestore(&rxq->lock, flags);
1079 }
1080
1081 void
1082 il3945_rx_replenish(void *data)
1083 {
1084 struct il_priv *il = data;
1085 unsigned long flags;
1086
1087 il3945_rx_allocate(il, GFP_KERNEL);
1088
1089 spin_lock_irqsave(&il->lock, flags);
1090 il3945_rx_queue_restock(il);
1091 spin_unlock_irqrestore(&il->lock, flags);
1092 }
1093
1094 static void
1095 il3945_rx_replenish_now(struct il_priv *il)
1096 {
1097 il3945_rx_allocate(il, GFP_ATOMIC);
1098
1099 il3945_rx_queue_restock(il);
1100 }
1101
1102
1103
1104
1105
1106
1107 static void
1108 il3945_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
1109 {
1110 int i;
1111 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
1112 if (rxq->pool[i].page != NULL) {
1113 dma_unmap_page(&il->pci_dev->dev,
1114 rxq->pool[i].page_dma,
1115 PAGE_SIZE << il->hw_params.rx_page_order,
1116 DMA_FROM_DEVICE);
1117 __il_free_pages(il, rxq->pool[i].page);
1118 rxq->pool[i].page = NULL;
1119 }
1120 }
1121
1122 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
1123 rxq->bd_dma);
1124 dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
1125 rxq->rb_stts, rxq->rb_stts_dma);
1126 rxq->bd = NULL;
1127 rxq->rb_stts = NULL;
1128 }
1129
1130
1131 static u8 ratio2dB[100] = {
1132
1133 0, 0, 6, 10, 12, 14, 16, 17, 18, 19,
1134 20, 21, 22, 22, 23, 23, 24, 25, 26, 26,
1135 26, 26, 26, 27, 27, 28, 28, 28, 29, 29,
1136 29, 30, 30, 30, 31, 31, 31, 31, 32, 32,
1137 32, 32, 32, 33, 33, 33, 33, 33, 34, 34,
1138 34, 34, 34, 34, 35, 35, 35, 35, 35, 35,
1139 36, 36, 36, 36, 36, 36, 36, 37, 37, 37,
1140 37, 37, 37, 37, 37, 38, 38, 38, 38, 38,
1141 38, 38, 38, 38, 38, 39, 39, 39, 39, 39,
1142 39, 39, 39, 39, 39, 40, 40, 40, 40, 40
1143 };
1144
1145
1146
1147
1148 int
1149 il3945_calc_db_from_ratio(int sig_ratio)
1150 {
1151
1152 if (sig_ratio >= 1000)
1153 return 60;
1154
1155
1156
1157 if (sig_ratio >= 100)
1158 return 20 + (int)ratio2dB[sig_ratio / 10];
1159
1160
1161 if (sig_ratio < 1)
1162 return 0;
1163
1164
1165 return (int)ratio2dB[sig_ratio];
1166 }
1167
1168
1169
1170
1171
1172
1173
1174
1175 static void
1176 il3945_rx_handle(struct il_priv *il)
1177 {
1178 struct il_rx_buf *rxb;
1179 struct il_rx_pkt *pkt;
1180 struct il_rx_queue *rxq = &il->rxq;
1181 u32 r, i;
1182 int reclaim;
1183 unsigned long flags;
1184 u8 fill_rx = 0;
1185 u32 count = 8;
1186 int total_empty = 0;
1187
1188
1189
1190 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
1191 i = rxq->read;
1192
1193
1194 total_empty = r - rxq->write_actual;
1195 if (total_empty < 0)
1196 total_empty += RX_QUEUE_SIZE;
1197
1198 if (total_empty > (RX_QUEUE_SIZE / 2))
1199 fill_rx = 1;
1200
1201 if (i == r)
1202 D_RX("r = %d, i = %d\n", r, i);
1203
1204 while (i != r) {
1205 int len;
1206
1207 rxb = rxq->queue[i];
1208
1209
1210
1211
1212 BUG_ON(rxb == NULL);
1213
1214 rxq->queue[i] = NULL;
1215
1216 dma_unmap_page(&il->pci_dev->dev, rxb->page_dma,
1217 PAGE_SIZE << il->hw_params.rx_page_order,
1218 DMA_FROM_DEVICE);
1219 pkt = rxb_addr(rxb);
1220
1221 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
1222 len += sizeof(u32);
1223
1224 reclaim = il_need_reclaim(il, pkt);
1225
1226
1227
1228
1229 if (il->handlers[pkt->hdr.cmd]) {
1230 D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i,
1231 il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
1232 il->isr_stats.handlers[pkt->hdr.cmd]++;
1233 il->handlers[pkt->hdr.cmd] (il, rxb);
1234 } else {
1235
1236 D_RX("r %d i %d No handler needed for %s, 0x%02x\n", r,
1237 i, il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
1238 }
1239
1240
1241
1242
1243
1244
1245
1246
1247 if (reclaim) {
1248
1249
1250
1251 if (rxb->page)
1252 il_tx_cmd_complete(il, rxb);
1253 else
1254 IL_WARN("Claim null rxb?\n");
1255 }
1256
1257
1258
1259
1260 spin_lock_irqsave(&rxq->lock, flags);
1261 if (rxb->page != NULL) {
1262 rxb->page_dma =
1263 dma_map_page(&il->pci_dev->dev, rxb->page, 0,
1264 PAGE_SIZE << il->hw_params.rx_page_order,
1265 DMA_FROM_DEVICE);
1266 if (unlikely(dma_mapping_error(&il->pci_dev->dev,
1267 rxb->page_dma))) {
1268 __il_free_pages(il, rxb->page);
1269 rxb->page = NULL;
1270 list_add_tail(&rxb->list, &rxq->rx_used);
1271 } else {
1272 list_add_tail(&rxb->list, &rxq->rx_free);
1273 rxq->free_count++;
1274 }
1275 } else
1276 list_add_tail(&rxb->list, &rxq->rx_used);
1277
1278 spin_unlock_irqrestore(&rxq->lock, flags);
1279
1280 i = (i + 1) & RX_QUEUE_MASK;
1281
1282
1283 if (fill_rx) {
1284 count++;
1285 if (count >= 8) {
1286 rxq->read = i;
1287 il3945_rx_replenish_now(il);
1288 count = 0;
1289 }
1290 }
1291 }
1292
1293
1294 rxq->read = i;
1295 if (fill_rx)
1296 il3945_rx_replenish_now(il);
1297 else
1298 il3945_rx_queue_restock(il);
1299 }
1300
1301
1302 static inline void
1303 il3945_synchronize_irq(struct il_priv *il)
1304 {
1305
1306 synchronize_irq(il->pci_dev->irq);
1307 tasklet_kill(&il->irq_tasklet);
1308 }
1309
1310 static const char *
1311 il3945_desc_lookup(int i)
1312 {
1313 switch (i) {
1314 case 1:
1315 return "FAIL";
1316 case 2:
1317 return "BAD_PARAM";
1318 case 3:
1319 return "BAD_CHECKSUM";
1320 case 4:
1321 return "NMI_INTERRUPT";
1322 case 5:
1323 return "SYSASSERT";
1324 case 6:
1325 return "FATAL_ERROR";
1326 }
1327
1328 return "UNKNOWN";
1329 }
1330
1331 #define ERROR_START_OFFSET (1 * sizeof(u32))
1332 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1333
1334 void
1335 il3945_dump_nic_error_log(struct il_priv *il)
1336 {
1337 u32 i;
1338 u32 desc, time, count, base, data1;
1339 u32 blink1, blink2, ilink1, ilink2;
1340
1341 base = le32_to_cpu(il->card_alive.error_event_table_ptr);
1342
1343 if (!il3945_hw_valid_rtc_data_addr(base)) {
1344 IL_ERR("Not valid error log pointer 0x%08X\n", base);
1345 return;
1346 }
1347
1348 count = il_read_targ_mem(il, base);
1349
1350 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1351 IL_ERR("Start IWL Error Log Dump:\n");
1352 IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count);
1353 }
1354
1355 IL_ERR("Desc Time asrtPC blink2 "
1356 "ilink1 nmiPC Line\n");
1357 for (i = ERROR_START_OFFSET;
1358 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
1359 i += ERROR_ELEM_SIZE) {
1360 desc = il_read_targ_mem(il, base + i);
1361 time = il_read_targ_mem(il, base + i + 1 * sizeof(u32));
1362 blink1 = il_read_targ_mem(il, base + i + 2 * sizeof(u32));
1363 blink2 = il_read_targ_mem(il, base + i + 3 * sizeof(u32));
1364 ilink1 = il_read_targ_mem(il, base + i + 4 * sizeof(u32));
1365 ilink2 = il_read_targ_mem(il, base + i + 5 * sizeof(u32));
1366 data1 = il_read_targ_mem(il, base + i + 6 * sizeof(u32));
1367
1368 IL_ERR("%-13s (0x%X) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
1369 il3945_desc_lookup(desc), desc, time, blink1, blink2,
1370 ilink1, ilink2, data1);
1371 }
1372 }
1373
1374 static void
1375 il3945_irq_tasklet(struct tasklet_struct *t)
1376 {
1377 struct il_priv *il = from_tasklet(il, t, irq_tasklet);
1378 u32 inta, handled = 0;
1379 u32 inta_fh;
1380 unsigned long flags;
1381 #ifdef CONFIG_IWLEGACY_DEBUG
1382 u32 inta_mask;
1383 #endif
1384
1385 spin_lock_irqsave(&il->lock, flags);
1386
1387
1388
1389
1390 inta = _il_rd(il, CSR_INT);
1391 _il_wr(il, CSR_INT, inta);
1392
1393
1394
1395
1396 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
1397 _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
1398
1399 #ifdef CONFIG_IWLEGACY_DEBUG
1400 if (il_get_debug_level(il) & IL_DL_ISR) {
1401
1402 inta_mask = _il_rd(il, CSR_INT_MASK);
1403 D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta,
1404 inta_mask, inta_fh);
1405 }
1406 #endif
1407
1408 spin_unlock_irqrestore(&il->lock, flags);
1409
1410
1411
1412
1413
1414 if (inta_fh & CSR39_FH_INT_RX_MASK)
1415 inta |= CSR_INT_BIT_FH_RX;
1416 if (inta_fh & CSR39_FH_INT_TX_MASK)
1417 inta |= CSR_INT_BIT_FH_TX;
1418
1419
1420 if (inta & CSR_INT_BIT_HW_ERR) {
1421 IL_ERR("Hardware error detected. Restarting.\n");
1422
1423
1424 il_disable_interrupts(il);
1425
1426 il->isr_stats.hw++;
1427 il_irq_handle_error(il);
1428
1429 handled |= CSR_INT_BIT_HW_ERR;
1430
1431 return;
1432 }
1433 #ifdef CONFIG_IWLEGACY_DEBUG
1434 if (il_get_debug_level(il) & (IL_DL_ISR)) {
1435
1436 if (inta & CSR_INT_BIT_SCD) {
1437 D_ISR("Scheduler finished to transmit "
1438 "the frame/frames.\n");
1439 il->isr_stats.sch++;
1440 }
1441
1442
1443 if (inta & CSR_INT_BIT_ALIVE) {
1444 D_ISR("Alive interrupt\n");
1445 il->isr_stats.alive++;
1446 }
1447 }
1448 #endif
1449
1450 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1451
1452
1453 if (inta & CSR_INT_BIT_SW_ERR) {
1454 IL_ERR("Microcode SW error detected. " "Restarting 0x%X.\n",
1455 inta);
1456 il->isr_stats.sw++;
1457 il_irq_handle_error(il);
1458 handled |= CSR_INT_BIT_SW_ERR;
1459 }
1460
1461
1462 if (inta & CSR_INT_BIT_WAKEUP) {
1463 D_ISR("Wakeup interrupt\n");
1464 il_rx_queue_update_write_ptr(il, &il->rxq);
1465
1466 spin_lock_irqsave(&il->lock, flags);
1467 il_txq_update_write_ptr(il, &il->txq[0]);
1468 il_txq_update_write_ptr(il, &il->txq[1]);
1469 il_txq_update_write_ptr(il, &il->txq[2]);
1470 il_txq_update_write_ptr(il, &il->txq[3]);
1471 il_txq_update_write_ptr(il, &il->txq[4]);
1472 spin_unlock_irqrestore(&il->lock, flags);
1473
1474 il->isr_stats.wakeup++;
1475 handled |= CSR_INT_BIT_WAKEUP;
1476 }
1477
1478
1479
1480
1481 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1482 il3945_rx_handle(il);
1483 il->isr_stats.rx++;
1484 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1485 }
1486
1487 if (inta & CSR_INT_BIT_FH_TX) {
1488 D_ISR("Tx interrupt\n");
1489 il->isr_stats.tx++;
1490
1491 _il_wr(il, CSR_FH_INT_STATUS, (1 << 6));
1492 il_wr(il, FH39_TCSR_CREDIT(FH39_SRVC_CHNL), 0x0);
1493 handled |= CSR_INT_BIT_FH_TX;
1494 }
1495
1496 if (inta & ~handled) {
1497 IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
1498 il->isr_stats.unhandled++;
1499 }
1500
1501 if (inta & ~il->inta_mask) {
1502 IL_WARN("Disabled INTA bits 0x%08x were pending\n",
1503 inta & ~il->inta_mask);
1504 IL_WARN(" with inta_fh = 0x%08x\n", inta_fh);
1505 }
1506
1507
1508
1509 if (test_bit(S_INT_ENABLED, &il->status))
1510 il_enable_interrupts(il);
1511
1512 #ifdef CONFIG_IWLEGACY_DEBUG
1513 if (il_get_debug_level(il) & (IL_DL_ISR)) {
1514 inta = _il_rd(il, CSR_INT);
1515 inta_mask = _il_rd(il, CSR_INT_MASK);
1516 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
1517 D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1518 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1519 }
1520 #endif
1521 }
1522
1523 static int
1524 il3945_get_channels_for_scan(struct il_priv *il, enum nl80211_band band,
1525 u8 is_active, u8 n_probes,
1526 struct il3945_scan_channel *scan_ch,
1527 struct ieee80211_vif *vif)
1528 {
1529 struct ieee80211_channel *chan;
1530 const struct ieee80211_supported_band *sband;
1531 const struct il_channel_info *ch_info;
1532 u16 passive_dwell = 0;
1533 u16 active_dwell = 0;
1534 int added, i;
1535
1536 sband = il_get_hw_mode(il, band);
1537 if (!sband)
1538 return 0;
1539
1540 active_dwell = il_get_active_dwell_time(il, band, n_probes);
1541 passive_dwell = il_get_passive_dwell_time(il, band, vif);
1542
1543 if (passive_dwell <= active_dwell)
1544 passive_dwell = active_dwell + 1;
1545
1546 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
1547 chan = il->scan_request->channels[i];
1548
1549 if (chan->band != band)
1550 continue;
1551
1552 scan_ch->channel = chan->hw_value;
1553
1554 ch_info = il_get_channel_info(il, band, scan_ch->channel);
1555 if (!il_is_channel_valid(ch_info)) {
1556 D_SCAN("Channel %d is INVALID for this band.\n",
1557 scan_ch->channel);
1558 continue;
1559 }
1560
1561 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1562 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1563
1564
1565
1566 if (!is_active || il_is_channel_passive(ch_info) ||
1567 (chan->flags & IEEE80211_CHAN_NO_IR)) {
1568 scan_ch->type = 0;
1569 if (IL_UCODE_API(il->ucode_ver) == 1)
1570 scan_ch->active_dwell =
1571 cpu_to_le16(passive_dwell - 1);
1572 } else {
1573 scan_ch->type = 1;
1574 }
1575
1576
1577
1578
1579
1580 if (IL_UCODE_API(il->ucode_ver) >= 2) {
1581 if (n_probes)
1582 scan_ch->type |= IL39_SCAN_PROBE_MASK(n_probes);
1583 } else {
1584
1585
1586 if ((scan_ch->type & 1) && n_probes)
1587 scan_ch->type |= IL39_SCAN_PROBE_MASK(n_probes);
1588 }
1589
1590
1591 scan_ch->tpc.dsp_atten = 110;
1592
1593
1594
1595 if (band == NL80211_BAND_5GHZ)
1596 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
1597 else {
1598 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
1599
1600
1601
1602
1603 }
1604
1605 D_SCAN("Scanning %d [%s %d]\n", scan_ch->channel,
1606 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
1607 (scan_ch->type & 1) ? active_dwell : passive_dwell);
1608
1609 scan_ch++;
1610 added++;
1611 }
1612
1613 D_SCAN("total channels to scan %d\n", added);
1614 return added;
1615 }
1616
1617 static void
1618 il3945_init_hw_rates(struct il_priv *il, struct ieee80211_rate *rates)
1619 {
1620 int i;
1621
1622 for (i = 0; i < RATE_COUNT_LEGACY; i++) {
1623 rates[i].bitrate = il3945_rates[i].ieee * 5;
1624 rates[i].hw_value = i;
1625 rates[i].hw_value_short = i;
1626 rates[i].flags = 0;
1627 if (i > IL39_LAST_OFDM_RATE || i < IL_FIRST_OFDM_RATE) {
1628
1629
1630
1631 rates[i].flags |=
1632 (il3945_rates[i].plcp ==
1633 10) ? 0 : IEEE80211_RATE_SHORT_PREAMBLE;
1634 }
1635 }
1636 }
1637
1638
1639
1640
1641
1642
1643
1644 static void
1645 il3945_dealloc_ucode_pci(struct il_priv *il)
1646 {
1647 il_free_fw_desc(il->pci_dev, &il->ucode_code);
1648 il_free_fw_desc(il->pci_dev, &il->ucode_data);
1649 il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
1650 il_free_fw_desc(il->pci_dev, &il->ucode_init);
1651 il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
1652 il_free_fw_desc(il->pci_dev, &il->ucode_boot);
1653 }
1654
1655
1656
1657
1658
1659 static int
1660 il3945_verify_inst_full(struct il_priv *il, __le32 * image, u32 len)
1661 {
1662 u32 val;
1663 u32 save_len = len;
1664 int rc = 0;
1665 u32 errcnt;
1666
1667 D_INFO("ucode inst image size is %u\n", len);
1668
1669 il_wr(il, HBUS_TARG_MEM_RADDR, IL39_RTC_INST_LOWER_BOUND);
1670
1671 errcnt = 0;
1672 for (; len > 0; len -= sizeof(u32), image++) {
1673
1674
1675
1676 val = _il_rd(il, HBUS_TARG_MEM_RDAT);
1677 if (val != le32_to_cpu(*image)) {
1678 IL_ERR("uCode INST section is invalid at "
1679 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1680 save_len - len, val, le32_to_cpu(*image));
1681 rc = -EIO;
1682 errcnt++;
1683 if (errcnt >= 20)
1684 break;
1685 }
1686 }
1687
1688 if (!errcnt)
1689 D_INFO("ucode image in INSTRUCTION memory is good\n");
1690
1691 return rc;
1692 }
1693
1694
1695
1696
1697
1698
1699 static int
1700 il3945_verify_inst_sparse(struct il_priv *il, __le32 * image, u32 len)
1701 {
1702 u32 val;
1703 int rc = 0;
1704 u32 errcnt = 0;
1705 u32 i;
1706
1707 D_INFO("ucode inst image size is %u\n", len);
1708
1709 for (i = 0; i < len; i += 100, image += 100 / sizeof(u32)) {
1710
1711
1712
1713 il_wr(il, HBUS_TARG_MEM_RADDR, i + IL39_RTC_INST_LOWER_BOUND);
1714 val = _il_rd(il, HBUS_TARG_MEM_RDAT);
1715 if (val != le32_to_cpu(*image)) {
1716 #if 0
1717 IL_ERR("uCode INST section is invalid at "
1718 "offset 0x%x, is 0x%x, s/b 0x%x\n", i, val,
1719 *image);
1720 #endif
1721 rc = -EIO;
1722 errcnt++;
1723 if (errcnt >= 3)
1724 break;
1725 }
1726 }
1727
1728 return rc;
1729 }
1730
1731
1732
1733
1734
1735 static int
1736 il3945_verify_ucode(struct il_priv *il)
1737 {
1738 __le32 *image;
1739 u32 len;
1740 int rc = 0;
1741
1742
1743 image = (__le32 *) il->ucode_boot.v_addr;
1744 len = il->ucode_boot.len;
1745 rc = il3945_verify_inst_sparse(il, image, len);
1746 if (rc == 0) {
1747 D_INFO("Bootstrap uCode is good in inst SRAM\n");
1748 return 0;
1749 }
1750
1751
1752 image = (__le32 *) il->ucode_init.v_addr;
1753 len = il->ucode_init.len;
1754 rc = il3945_verify_inst_sparse(il, image, len);
1755 if (rc == 0) {
1756 D_INFO("Initialize uCode is good in inst SRAM\n");
1757 return 0;
1758 }
1759
1760
1761 image = (__le32 *) il->ucode_code.v_addr;
1762 len = il->ucode_code.len;
1763 rc = il3945_verify_inst_sparse(il, image, len);
1764 if (rc == 0) {
1765 D_INFO("Runtime uCode is good in inst SRAM\n");
1766 return 0;
1767 }
1768
1769 IL_ERR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1770
1771
1772
1773
1774 image = (__le32 *) il->ucode_boot.v_addr;
1775 len = il->ucode_boot.len;
1776 rc = il3945_verify_inst_full(il, image, len);
1777
1778 return rc;
1779 }
1780
1781 static void
1782 il3945_nic_start(struct il_priv *il)
1783 {
1784
1785 _il_wr(il, CSR_RESET, 0);
1786 }
1787
1788 #define IL3945_UCODE_GET(item) \
1789 static u32 il3945_ucode_get_##item(const struct il_ucode_header *ucode)\
1790 { \
1791 return le32_to_cpu(ucode->v1.item); \
1792 }
1793
1794 static u32
1795 il3945_ucode_get_header_size(u32 api_ver)
1796 {
1797 return 24;
1798 }
1799
1800 static u8 *
1801 il3945_ucode_get_data(const struct il_ucode_header *ucode)
1802 {
1803 return (u8 *) ucode->v1.data;
1804 }
1805
1806 IL3945_UCODE_GET(inst_size);
1807 IL3945_UCODE_GET(data_size);
1808 IL3945_UCODE_GET(init_size);
1809 IL3945_UCODE_GET(init_data_size);
1810 IL3945_UCODE_GET(boot_size);
1811
1812
1813
1814
1815
1816
1817 static int
1818 il3945_read_ucode(struct il_priv *il)
1819 {
1820 const struct il_ucode_header *ucode;
1821 int ret = -EINVAL, idx;
1822 const struct firmware *ucode_raw;
1823
1824 const char *name_pre = il->cfg->fw_name_pre;
1825 const unsigned int api_max = il->cfg->ucode_api_max;
1826 const unsigned int api_min = il->cfg->ucode_api_min;
1827 char buf[25];
1828 u8 *src;
1829 size_t len;
1830 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
1831
1832
1833
1834 for (idx = api_max; idx >= api_min; idx--) {
1835 sprintf(buf, "%s%u%s", name_pre, idx, ".ucode");
1836 ret = request_firmware(&ucode_raw, buf, &il->pci_dev->dev);
1837 if (ret < 0) {
1838 IL_ERR("%s firmware file req failed: %d\n", buf, ret);
1839 if (ret == -ENOENT)
1840 continue;
1841 else
1842 goto error;
1843 } else {
1844 if (idx < api_max)
1845 IL_ERR("Loaded firmware %s, "
1846 "which is deprecated. "
1847 " Please use API v%u instead.\n", buf,
1848 api_max);
1849 D_INFO("Got firmware '%s' file "
1850 "(%zd bytes) from disk\n", buf, ucode_raw->size);
1851 break;
1852 }
1853 }
1854
1855 if (ret < 0)
1856 goto error;
1857
1858
1859 if (ucode_raw->size < il3945_ucode_get_header_size(1)) {
1860 IL_ERR("File size way too small!\n");
1861 ret = -EINVAL;
1862 goto err_release;
1863 }
1864
1865
1866 ucode = (struct il_ucode_header *)ucode_raw->data;
1867
1868 il->ucode_ver = le32_to_cpu(ucode->ver);
1869 api_ver = IL_UCODE_API(il->ucode_ver);
1870 inst_size = il3945_ucode_get_inst_size(ucode);
1871 data_size = il3945_ucode_get_data_size(ucode);
1872 init_size = il3945_ucode_get_init_size(ucode);
1873 init_data_size = il3945_ucode_get_init_data_size(ucode);
1874 boot_size = il3945_ucode_get_boot_size(ucode);
1875 src = il3945_ucode_get_data(ucode);
1876
1877
1878
1879
1880
1881 if (api_ver < api_min || api_ver > api_max) {
1882 IL_ERR("Driver unable to support your firmware API. "
1883 "Driver supports v%u, firmware is v%u.\n", api_max,
1884 api_ver);
1885 il->ucode_ver = 0;
1886 ret = -EINVAL;
1887 goto err_release;
1888 }
1889 if (api_ver != api_max)
1890 IL_ERR("Firmware has old API version. Expected %u, "
1891 "got %u. New firmware can be obtained "
1892 "from http://www.intellinuxwireless.org.\n", api_max,
1893 api_ver);
1894
1895 IL_INFO("loaded firmware version %u.%u.%u.%u\n",
1896 IL_UCODE_MAJOR(il->ucode_ver), IL_UCODE_MINOR(il->ucode_ver),
1897 IL_UCODE_API(il->ucode_ver), IL_UCODE_SERIAL(il->ucode_ver));
1898
1899 snprintf(il->hw->wiphy->fw_version, sizeof(il->hw->wiphy->fw_version),
1900 "%u.%u.%u.%u", IL_UCODE_MAJOR(il->ucode_ver),
1901 IL_UCODE_MINOR(il->ucode_ver), IL_UCODE_API(il->ucode_ver),
1902 IL_UCODE_SERIAL(il->ucode_ver));
1903
1904 D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver);
1905 D_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
1906 D_INFO("f/w package hdr runtime data size = %u\n", data_size);
1907 D_INFO("f/w package hdr init inst size = %u\n", init_size);
1908 D_INFO("f/w package hdr init data size = %u\n", init_data_size);
1909 D_INFO("f/w package hdr boot inst size = %u\n", boot_size);
1910
1911
1912 if (ucode_raw->size !=
1913 il3945_ucode_get_header_size(api_ver) + inst_size + data_size +
1914 init_size + init_data_size + boot_size) {
1915
1916 D_INFO("uCode file size %zd does not match expected size\n",
1917 ucode_raw->size);
1918 ret = -EINVAL;
1919 goto err_release;
1920 }
1921
1922
1923 if (inst_size > IL39_MAX_INST_SIZE) {
1924 D_INFO("uCode instr len %d too large to fit in\n", inst_size);
1925 ret = -EINVAL;
1926 goto err_release;
1927 }
1928
1929 if (data_size > IL39_MAX_DATA_SIZE) {
1930 D_INFO("uCode data len %d too large to fit in\n", data_size);
1931 ret = -EINVAL;
1932 goto err_release;
1933 }
1934 if (init_size > IL39_MAX_INST_SIZE) {
1935 D_INFO("uCode init instr len %d too large to fit in\n",
1936 init_size);
1937 ret = -EINVAL;
1938 goto err_release;
1939 }
1940 if (init_data_size > IL39_MAX_DATA_SIZE) {
1941 D_INFO("uCode init data len %d too large to fit in\n",
1942 init_data_size);
1943 ret = -EINVAL;
1944 goto err_release;
1945 }
1946 if (boot_size > IL39_MAX_BSM_SIZE) {
1947 D_INFO("uCode boot instr len %d too large to fit in\n",
1948 boot_size);
1949 ret = -EINVAL;
1950 goto err_release;
1951 }
1952
1953
1954
1955
1956
1957
1958 il->ucode_code.len = inst_size;
1959 il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
1960
1961 il->ucode_data.len = data_size;
1962 il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
1963
1964 il->ucode_data_backup.len = data_size;
1965 il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
1966
1967 if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
1968 !il->ucode_data_backup.v_addr)
1969 goto err_pci_alloc;
1970
1971
1972 if (init_size && init_data_size) {
1973 il->ucode_init.len = init_size;
1974 il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
1975
1976 il->ucode_init_data.len = init_data_size;
1977 il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
1978
1979 if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
1980 goto err_pci_alloc;
1981 }
1982
1983
1984 if (boot_size) {
1985 il->ucode_boot.len = boot_size;
1986 il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
1987
1988 if (!il->ucode_boot.v_addr)
1989 goto err_pci_alloc;
1990 }
1991
1992
1993
1994
1995 len = inst_size;
1996 D_INFO("Copying (but not loading) uCode instr len %zd\n", len);
1997 memcpy(il->ucode_code.v_addr, src, len);
1998 src += len;
1999
2000 D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
2001 il->ucode_code.v_addr, (u32) il->ucode_code.p_addr);
2002
2003
2004
2005 len = data_size;
2006 D_INFO("Copying (but not loading) uCode data len %zd\n", len);
2007 memcpy(il->ucode_data.v_addr, src, len);
2008 memcpy(il->ucode_data_backup.v_addr, src, len);
2009 src += len;
2010
2011
2012 if (init_size) {
2013 len = init_size;
2014 D_INFO("Copying (but not loading) init instr len %zd\n", len);
2015 memcpy(il->ucode_init.v_addr, src, len);
2016 src += len;
2017 }
2018
2019
2020 if (init_data_size) {
2021 len = init_data_size;
2022 D_INFO("Copying (but not loading) init data len %zd\n", len);
2023 memcpy(il->ucode_init_data.v_addr, src, len);
2024 src += len;
2025 }
2026
2027
2028 len = boot_size;
2029 D_INFO("Copying (but not loading) boot instr len %zd\n", len);
2030 memcpy(il->ucode_boot.v_addr, src, len);
2031
2032
2033 release_firmware(ucode_raw);
2034 return 0;
2035
2036 err_pci_alloc:
2037 IL_ERR("failed to allocate pci memory\n");
2038 ret = -ENOMEM;
2039 il3945_dealloc_ucode_pci(il);
2040
2041 err_release:
2042 release_firmware(ucode_raw);
2043
2044 error:
2045 return ret;
2046 }
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057 static int
2058 il3945_set_ucode_ptrs(struct il_priv *il)
2059 {
2060 dma_addr_t pinst;
2061 dma_addr_t pdata;
2062
2063
2064 pinst = il->ucode_code.p_addr;
2065 pdata = il->ucode_data_backup.p_addr;
2066
2067
2068 il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
2069 il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
2070 il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, il->ucode_data.len);
2071
2072
2073
2074 il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG,
2075 il->ucode_code.len | BSM_DRAM_INST_LOAD);
2076
2077 D_INFO("Runtime uCode pointers are set.\n");
2078
2079 return 0;
2080 }
2081
2082
2083
2084
2085
2086
2087
2088
2089 static void
2090 il3945_init_alive_start(struct il_priv *il)
2091 {
2092
2093 if (il->card_alive_init.is_valid != UCODE_VALID_OK) {
2094
2095
2096 D_INFO("Initialize Alive failed.\n");
2097 goto restart;
2098 }
2099
2100
2101
2102
2103 if (il3945_verify_ucode(il)) {
2104
2105
2106 D_INFO("Bad \"initialize\" uCode load.\n");
2107 goto restart;
2108 }
2109
2110
2111
2112
2113 D_INFO("Initialization Alive received.\n");
2114 if (il3945_set_ucode_ptrs(il)) {
2115
2116
2117 D_INFO("Couldn't set up uCode pointers.\n");
2118 goto restart;
2119 }
2120 return;
2121
2122 restart:
2123 queue_work(il->workqueue, &il->restart);
2124 }
2125
2126
2127
2128
2129
2130
2131 static void
2132 il3945_alive_start(struct il_priv *il)
2133 {
2134 int thermal_spin = 0;
2135 u32 rfkill;
2136
2137 D_INFO("Runtime Alive received.\n");
2138
2139 if (il->card_alive.is_valid != UCODE_VALID_OK) {
2140
2141
2142 D_INFO("Alive failed.\n");
2143 goto restart;
2144 }
2145
2146
2147
2148
2149 if (il3945_verify_ucode(il)) {
2150
2151
2152 D_INFO("Bad runtime uCode load.\n");
2153 goto restart;
2154 }
2155
2156 rfkill = il_rd_prph(il, APMG_RFKILL_REG);
2157 D_INFO("RFKILL status: 0x%x\n", rfkill);
2158
2159 if (rfkill & 0x1) {
2160 clear_bit(S_RFKILL, &il->status);
2161
2162
2163 while (il3945_hw_get_temperature(il) == 0) {
2164 thermal_spin++;
2165 udelay(10);
2166 }
2167
2168 if (thermal_spin)
2169 D_INFO("Thermal calibration took %dus\n",
2170 thermal_spin * 10);
2171 } else
2172 set_bit(S_RFKILL, &il->status);
2173
2174
2175 set_bit(S_ALIVE, &il->status);
2176
2177
2178 il_setup_watchdog(il);
2179
2180 if (il_is_rfkill(il))
2181 return;
2182
2183 ieee80211_wake_queues(il->hw);
2184
2185 il->active_rate = RATES_MASK_3945;
2186
2187 il_power_update_mode(il, true);
2188
2189 if (il_is_associated(il)) {
2190 struct il3945_rxon_cmd *active_rxon =
2191 (struct il3945_rxon_cmd *)(&il->active);
2192
2193 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2194 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2195 } else {
2196
2197 il_connection_init_rx_config(il);
2198 }
2199
2200
2201 il_send_bt_config(il);
2202
2203 set_bit(S_READY, &il->status);
2204
2205
2206 il3945_commit_rxon(il);
2207
2208 il3945_reg_txpower_periodic(il);
2209
2210 D_INFO("ALIVE processing complete.\n");
2211 wake_up(&il->wait_command_queue);
2212
2213 return;
2214
2215 restart:
2216 queue_work(il->workqueue, &il->restart);
2217 }
2218
2219 static void il3945_cancel_deferred_work(struct il_priv *il);
2220
2221 static void
2222 __il3945_down(struct il_priv *il)
2223 {
2224 unsigned long flags;
2225 int exit_pending;
2226
2227 D_INFO(DRV_NAME " is going down\n");
2228
2229 il_scan_cancel_timeout(il, 200);
2230
2231 exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status);
2232
2233
2234
2235 del_timer_sync(&il->watchdog);
2236
2237
2238 il_clear_ucode_stations(il);
2239 il_dealloc_bcast_stations(il);
2240 il_clear_driver_stations(il);
2241
2242
2243 wake_up_all(&il->wait_command_queue);
2244
2245
2246
2247 if (!exit_pending)
2248 clear_bit(S_EXIT_PENDING, &il->status);
2249
2250
2251 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2252
2253
2254 spin_lock_irqsave(&il->lock, flags);
2255 il_disable_interrupts(il);
2256 spin_unlock_irqrestore(&il->lock, flags);
2257 il3945_synchronize_irq(il);
2258
2259 if (il->mac80211_registered)
2260 ieee80211_stop_queues(il->hw);
2261
2262
2263
2264 if (!il_is_init(il)) {
2265 il->status =
2266 test_bit(S_RFKILL, &il->status) << S_RFKILL |
2267 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
2268 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
2269 goto exit;
2270 }
2271
2272
2273
2274 il->status &=
2275 test_bit(S_RFKILL, &il->status) << S_RFKILL |
2276 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
2277 test_bit(S_FW_ERROR, &il->status) << S_FW_ERROR |
2278 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
2279
2280
2281
2282
2283
2284
2285 spin_lock_irq(&il->reg_lock);
2286
2287
2288 il3945_hw_txq_ctx_stop(il);
2289 il3945_hw_rxq_stop(il);
2290
2291 _il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2292 udelay(5);
2293
2294 _il_apm_stop(il);
2295
2296 spin_unlock_irq(&il->reg_lock);
2297
2298 il3945_hw_txq_ctx_free(il);
2299 exit:
2300 memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
2301 dev_kfree_skb(il->beacon_skb);
2302 il->beacon_skb = NULL;
2303
2304
2305 il3945_clear_free_frames(il);
2306 }
2307
2308 static void
2309 il3945_down(struct il_priv *il)
2310 {
2311 mutex_lock(&il->mutex);
2312 __il3945_down(il);
2313 mutex_unlock(&il->mutex);
2314
2315 il3945_cancel_deferred_work(il);
2316 }
2317
2318 #define MAX_HW_RESTARTS 5
2319
2320 static int
2321 il3945_alloc_bcast_station(struct il_priv *il)
2322 {
2323 unsigned long flags;
2324 u8 sta_id;
2325
2326 spin_lock_irqsave(&il->sta_lock, flags);
2327 sta_id = il_prep_station(il, il_bcast_addr, false, NULL);
2328 if (sta_id == IL_INVALID_STATION) {
2329 IL_ERR("Unable to prepare broadcast station\n");
2330 spin_unlock_irqrestore(&il->sta_lock, flags);
2331
2332 return -EINVAL;
2333 }
2334
2335 il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE;
2336 il->stations[sta_id].used |= IL_STA_BCAST;
2337 spin_unlock_irqrestore(&il->sta_lock, flags);
2338
2339 return 0;
2340 }
2341
2342 static int
2343 __il3945_up(struct il_priv *il)
2344 {
2345 int rc, i;
2346
2347 rc = il3945_alloc_bcast_station(il);
2348 if (rc)
2349 return rc;
2350
2351 if (test_bit(S_EXIT_PENDING, &il->status)) {
2352 IL_WARN("Exit pending; will not bring the NIC up\n");
2353 return -EIO;
2354 }
2355
2356 if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
2357 IL_ERR("ucode not available for device bring up\n");
2358 return -EIO;
2359 }
2360
2361
2362 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2363 clear_bit(S_RFKILL, &il->status);
2364 else {
2365 set_bit(S_RFKILL, &il->status);
2366 return -ERFKILL;
2367 }
2368
2369 _il_wr(il, CSR_INT, 0xFFFFFFFF);
2370
2371 rc = il3945_hw_nic_init(il);
2372 if (rc) {
2373 IL_ERR("Unable to int nic\n");
2374 return rc;
2375 }
2376
2377
2378 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2379 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2380
2381
2382 _il_wr(il, CSR_INT, 0xFFFFFFFF);
2383 il_enable_interrupts(il);
2384
2385
2386 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2387 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2388
2389
2390
2391
2392 memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
2393 il->ucode_data.len);
2394
2395
2396 if (test_bit(S_RFKILL, &il->status))
2397 return 0;
2398
2399 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2400
2401
2402
2403
2404 rc = il->ops->load_ucode(il);
2405
2406 if (rc) {
2407 IL_ERR("Unable to set up bootstrap uCode: %d\n", rc);
2408 continue;
2409 }
2410
2411
2412 il3945_nic_start(il);
2413
2414 D_INFO(DRV_NAME " is coming up\n");
2415
2416 return 0;
2417 }
2418
2419 set_bit(S_EXIT_PENDING, &il->status);
2420 __il3945_down(il);
2421 clear_bit(S_EXIT_PENDING, &il->status);
2422
2423
2424
2425 IL_ERR("Unable to initialize device after %d attempts.\n", i);
2426 return -EIO;
2427 }
2428
2429
2430
2431
2432
2433
2434
2435 static void
2436 il3945_bg_init_alive_start(struct work_struct *data)
2437 {
2438 struct il_priv *il =
2439 container_of(data, struct il_priv, init_alive_start.work);
2440
2441 mutex_lock(&il->mutex);
2442 if (test_bit(S_EXIT_PENDING, &il->status))
2443 goto out;
2444
2445 il3945_init_alive_start(il);
2446 out:
2447 mutex_unlock(&il->mutex);
2448 }
2449
2450 static void
2451 il3945_bg_alive_start(struct work_struct *data)
2452 {
2453 struct il_priv *il =
2454 container_of(data, struct il_priv, alive_start.work);
2455
2456 mutex_lock(&il->mutex);
2457 if (test_bit(S_EXIT_PENDING, &il->status) || il->txq == NULL)
2458 goto out;
2459
2460 il3945_alive_start(il);
2461 out:
2462 mutex_unlock(&il->mutex);
2463 }
2464
2465
2466
2467
2468
2469
2470
2471 static void
2472 il3945_rfkill_poll(struct work_struct *data)
2473 {
2474 struct il_priv *il =
2475 container_of(data, struct il_priv, _3945.rfkill_poll.work);
2476 bool old_rfkill = test_bit(S_RFKILL, &il->status);
2477 bool new_rfkill =
2478 !(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
2479
2480 if (new_rfkill != old_rfkill) {
2481 if (new_rfkill)
2482 set_bit(S_RFKILL, &il->status);
2483 else
2484 clear_bit(S_RFKILL, &il->status);
2485
2486 wiphy_rfkill_set_hw_state(il->hw->wiphy, new_rfkill);
2487
2488 D_RF_KILL("RF_KILL bit toggled to %s.\n",
2489 new_rfkill ? "disable radio" : "enable radio");
2490 }
2491
2492
2493
2494 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
2495 round_jiffies_relative(2 * HZ));
2496
2497 }
2498
2499 int
2500 il3945_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
2501 {
2502 struct il_host_cmd cmd = {
2503 .id = C_SCAN,
2504 .len = sizeof(struct il3945_scan_cmd),
2505 .flags = CMD_SIZE_HUGE,
2506 };
2507 struct il3945_scan_cmd *scan;
2508 u8 n_probes = 0;
2509 enum nl80211_band band;
2510 bool is_active = false;
2511 int ret;
2512 u16 len;
2513
2514 lockdep_assert_held(&il->mutex);
2515
2516 if (!il->scan_cmd) {
2517 il->scan_cmd =
2518 kmalloc(sizeof(struct il3945_scan_cmd) + IL_MAX_SCAN_SIZE,
2519 GFP_KERNEL);
2520 if (!il->scan_cmd) {
2521 D_SCAN("Fail to allocate scan memory\n");
2522 return -ENOMEM;
2523 }
2524 }
2525 scan = il->scan_cmd;
2526 memset(scan, 0, sizeof(struct il3945_scan_cmd) + IL_MAX_SCAN_SIZE);
2527
2528 scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH;
2529 scan->quiet_time = IL_ACTIVE_QUIET_TIME;
2530
2531 if (il_is_associated(il)) {
2532 u16 interval;
2533 u32 extra;
2534 u32 suspend_time = 100;
2535 u32 scan_suspend_time = 100;
2536
2537 D_INFO("Scanning while associated...\n");
2538
2539 interval = vif->bss_conf.beacon_int;
2540
2541 scan->suspend_time = 0;
2542 scan->max_out_time = cpu_to_le32(200 * 1024);
2543 if (!interval)
2544 interval = suspend_time;
2545
2546
2547
2548
2549
2550
2551
2552 extra = (suspend_time / interval) << 24;
2553 scan_suspend_time =
2554 0xFF0FFFFF & (extra | ((suspend_time % interval) * 1024));
2555
2556 scan->suspend_time = cpu_to_le32(scan_suspend_time);
2557 D_SCAN("suspend_time 0x%X beacon interval %d\n",
2558 scan_suspend_time, interval);
2559 }
2560
2561 if (il->scan_request->n_ssids) {
2562 int i, p = 0;
2563 D_SCAN("Kicking off active scan\n");
2564 for (i = 0; i < il->scan_request->n_ssids; i++) {
2565
2566 if (!il->scan_request->ssids[i].ssid_len)
2567 continue;
2568 scan->direct_scan[p].id = WLAN_EID_SSID;
2569 scan->direct_scan[p].len =
2570 il->scan_request->ssids[i].ssid_len;
2571 memcpy(scan->direct_scan[p].ssid,
2572 il->scan_request->ssids[i].ssid,
2573 il->scan_request->ssids[i].ssid_len);
2574 n_probes++;
2575 p++;
2576 }
2577 is_active = true;
2578 } else
2579 D_SCAN("Kicking off passive scan.\n");
2580
2581
2582
2583 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
2584 scan->tx_cmd.sta_id = il->hw_params.bcast_id;
2585 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2586
2587
2588
2589 switch (il->scan_band) {
2590 case NL80211_BAND_2GHZ:
2591 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
2592 scan->tx_cmd.rate = RATE_1M_PLCP;
2593 band = NL80211_BAND_2GHZ;
2594 break;
2595 case NL80211_BAND_5GHZ:
2596 scan->tx_cmd.rate = RATE_6M_PLCP;
2597 band = NL80211_BAND_5GHZ;
2598 break;
2599 default:
2600 IL_WARN("Invalid scan band\n");
2601 return -EIO;
2602 }
2603
2604
2605
2606
2607
2608
2609 scan->good_CRC_th =
2610 is_active ? IL_GOOD_CRC_TH_DEFAULT : IL_GOOD_CRC_TH_NEVER;
2611
2612 len =
2613 il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data,
2614 vif->addr, il->scan_request->ie,
2615 il->scan_request->ie_len,
2616 IL_MAX_SCAN_SIZE - sizeof(*scan));
2617 scan->tx_cmd.len = cpu_to_le16(len);
2618
2619
2620 scan->flags |= il3945_get_antenna_flags(il);
2621
2622 scan->channel_count =
2623 il3945_get_channels_for_scan(il, band, is_active, n_probes,
2624 (void *)&scan->data[len], vif);
2625 if (scan->channel_count == 0) {
2626 D_SCAN("channel count %d\n", scan->channel_count);
2627 return -EIO;
2628 }
2629
2630 cmd.len +=
2631 le16_to_cpu(scan->tx_cmd.len) +
2632 scan->channel_count * sizeof(struct il3945_scan_channel);
2633 cmd.data = scan;
2634 scan->len = cpu_to_le16(cmd.len);
2635
2636 set_bit(S_SCAN_HW, &il->status);
2637 ret = il_send_cmd_sync(il, &cmd);
2638 if (ret)
2639 clear_bit(S_SCAN_HW, &il->status);
2640 return ret;
2641 }
2642
2643 void
2644 il3945_post_scan(struct il_priv *il)
2645 {
2646
2647
2648
2649
2650 if (memcmp(&il->staging, &il->active, sizeof(il->staging)))
2651 il3945_commit_rxon(il);
2652 }
2653
2654 static void
2655 il3945_bg_restart(struct work_struct *data)
2656 {
2657 struct il_priv *il = container_of(data, struct il_priv, restart);
2658
2659 if (test_bit(S_EXIT_PENDING, &il->status))
2660 return;
2661
2662 if (test_and_clear_bit(S_FW_ERROR, &il->status)) {
2663 mutex_lock(&il->mutex);
2664 il->is_open = 0;
2665 mutex_unlock(&il->mutex);
2666 il3945_down(il);
2667 ieee80211_restart_hw(il->hw);
2668 } else {
2669 il3945_down(il);
2670
2671 mutex_lock(&il->mutex);
2672 if (test_bit(S_EXIT_PENDING, &il->status)) {
2673 mutex_unlock(&il->mutex);
2674 return;
2675 }
2676
2677 __il3945_up(il);
2678 mutex_unlock(&il->mutex);
2679 }
2680 }
2681
2682 static void
2683 il3945_bg_rx_replenish(struct work_struct *data)
2684 {
2685 struct il_priv *il = container_of(data, struct il_priv, rx_replenish);
2686
2687 mutex_lock(&il->mutex);
2688 if (test_bit(S_EXIT_PENDING, &il->status))
2689 goto out;
2690
2691 il3945_rx_replenish(il);
2692 out:
2693 mutex_unlock(&il->mutex);
2694 }
2695
2696 void
2697 il3945_post_associate(struct il_priv *il)
2698 {
2699 int rc = 0;
2700
2701 if (!il->vif || !il->is_open)
2702 return;
2703
2704 D_ASSOC("Associated as %d to: %pM\n", il->vif->cfg.aid,
2705 il->active.bssid_addr);
2706
2707 if (test_bit(S_EXIT_PENDING, &il->status))
2708 return;
2709
2710 il_scan_cancel_timeout(il, 200);
2711
2712 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2713 il3945_commit_rxon(il);
2714
2715 rc = il_send_rxon_timing(il);
2716 if (rc)
2717 IL_WARN("C_RXON_TIMING failed - " "Attempting to continue.\n");
2718
2719 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2720
2721 il->staging.assoc_id = cpu_to_le16(il->vif->cfg.aid);
2722
2723 D_ASSOC("assoc id %d beacon interval %d\n", il->vif->cfg.aid,
2724 il->vif->bss_conf.beacon_int);
2725
2726 if (il->vif->bss_conf.use_short_preamble)
2727 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2728 else
2729 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2730
2731 if (il->staging.flags & RXON_FLG_BAND_24G_MSK) {
2732 if (il->vif->bss_conf.use_short_slot)
2733 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
2734 else
2735 il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2736 }
2737
2738 il3945_commit_rxon(il);
2739
2740 switch (il->vif->type) {
2741 case NL80211_IFTYPE_STATION:
2742 il3945_rate_scale_init(il->hw, IL_AP_ID);
2743 break;
2744 case NL80211_IFTYPE_ADHOC:
2745 il3945_send_beacon_cmd(il);
2746 break;
2747 default:
2748 IL_ERR("%s Should not be called in %d mode\n", __func__,
2749 il->vif->type);
2750 break;
2751 }
2752 }
2753
2754
2755
2756
2757
2758
2759
2760 #define UCODE_READY_TIMEOUT (2 * HZ)
2761
2762 static int
2763 il3945_mac_start(struct ieee80211_hw *hw)
2764 {
2765 struct il_priv *il = hw->priv;
2766 int ret;
2767
2768
2769 mutex_lock(&il->mutex);
2770 D_MAC80211("enter\n");
2771
2772
2773
2774
2775 if (!il->ucode_code.len) {
2776 ret = il3945_read_ucode(il);
2777 if (ret) {
2778 IL_ERR("Could not read microcode: %d\n", ret);
2779 mutex_unlock(&il->mutex);
2780 goto out_release_irq;
2781 }
2782 }
2783
2784 ret = __il3945_up(il);
2785
2786 mutex_unlock(&il->mutex);
2787
2788 if (ret)
2789 goto out_release_irq;
2790
2791 D_INFO("Start UP work.\n");
2792
2793
2794
2795 ret = wait_event_timeout(il->wait_command_queue,
2796 test_bit(S_READY, &il->status),
2797 UCODE_READY_TIMEOUT);
2798 if (!ret) {
2799 if (!test_bit(S_READY, &il->status)) {
2800 IL_ERR("Wait for START_ALIVE timeout after %dms.\n",
2801 jiffies_to_msecs(UCODE_READY_TIMEOUT));
2802 ret = -ETIMEDOUT;
2803 goto out_release_irq;
2804 }
2805 }
2806
2807
2808
2809 cancel_delayed_work(&il->_3945.rfkill_poll);
2810
2811 il->is_open = 1;
2812 D_MAC80211("leave\n");
2813 return 0;
2814
2815 out_release_irq:
2816 il->is_open = 0;
2817 D_MAC80211("leave - failed\n");
2818 return ret;
2819 }
2820
2821 static void
2822 il3945_mac_stop(struct ieee80211_hw *hw)
2823 {
2824 struct il_priv *il = hw->priv;
2825
2826 D_MAC80211("enter\n");
2827
2828 if (!il->is_open) {
2829 D_MAC80211("leave - skip\n");
2830 return;
2831 }
2832
2833 il->is_open = 0;
2834
2835 il3945_down(il);
2836
2837 flush_workqueue(il->workqueue);
2838
2839
2840 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
2841 round_jiffies_relative(2 * HZ));
2842
2843 D_MAC80211("leave\n");
2844 }
2845
2846 static void
2847 il3945_mac_tx(struct ieee80211_hw *hw,
2848 struct ieee80211_tx_control *control,
2849 struct sk_buff *skb)
2850 {
2851 struct il_priv *il = hw->priv;
2852
2853 D_MAC80211("enter\n");
2854
2855 D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2856 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2857
2858 if (il3945_tx_skb(il, control->sta, skb))
2859 dev_kfree_skb_any(skb);
2860
2861 D_MAC80211("leave\n");
2862 }
2863
2864 void
2865 il3945_config_ap(struct il_priv *il)
2866 {
2867 struct ieee80211_vif *vif = il->vif;
2868 int rc = 0;
2869
2870 if (test_bit(S_EXIT_PENDING, &il->status))
2871 return;
2872
2873
2874 if (!(il_is_associated(il))) {
2875
2876
2877 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2878 il3945_commit_rxon(il);
2879
2880
2881 rc = il_send_rxon_timing(il);
2882 if (rc)
2883 IL_WARN("C_RXON_TIMING failed - "
2884 "Attempting to continue.\n");
2885
2886 il->staging.assoc_id = 0;
2887
2888 if (vif->bss_conf.use_short_preamble)
2889 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2890 else
2891 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2892
2893 if (il->staging.flags & RXON_FLG_BAND_24G_MSK) {
2894 if (vif->bss_conf.use_short_slot)
2895 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
2896 else
2897 il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2898 }
2899
2900 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2901 il3945_commit_rxon(il);
2902 }
2903 il3945_send_beacon_cmd(il);
2904 }
2905
2906 static int
2907 il3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2908 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2909 struct ieee80211_key_conf *key)
2910 {
2911 struct il_priv *il = hw->priv;
2912 int ret = 0;
2913 u8 sta_id = IL_INVALID_STATION;
2914 u8 static_key;
2915
2916 D_MAC80211("enter\n");
2917
2918 if (il3945_mod_params.sw_crypto) {
2919 D_MAC80211("leave - hwcrypto disabled\n");
2920 return -EOPNOTSUPP;
2921 }
2922
2923
2924
2925
2926
2927 if (vif->type == NL80211_IFTYPE_ADHOC &&
2928 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
2929 D_MAC80211("leave - IBSS RSN\n");
2930 return -EOPNOTSUPP;
2931 }
2932
2933 static_key = !il_is_associated(il);
2934
2935 if (!static_key) {
2936 sta_id = il_sta_id_or_broadcast(il, sta);
2937 if (sta_id == IL_INVALID_STATION) {
2938 D_MAC80211("leave - station not found\n");
2939 return -EINVAL;
2940 }
2941 }
2942
2943 mutex_lock(&il->mutex);
2944 il_scan_cancel_timeout(il, 100);
2945
2946 switch (cmd) {
2947 case SET_KEY:
2948 if (static_key)
2949 ret = il3945_set_static_key(il, key);
2950 else
2951 ret = il3945_set_dynamic_key(il, key, sta_id);
2952 D_MAC80211("enable hwcrypto key\n");
2953 break;
2954 case DISABLE_KEY:
2955 if (static_key)
2956 ret = il3945_remove_static_key(il);
2957 else
2958 ret = il3945_clear_sta_key_info(il, sta_id);
2959 D_MAC80211("disable hwcrypto key\n");
2960 break;
2961 default:
2962 ret = -EINVAL;
2963 }
2964
2965 D_MAC80211("leave ret %d\n", ret);
2966 mutex_unlock(&il->mutex);
2967
2968 return ret;
2969 }
2970
2971 static int
2972 il3945_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2973 struct ieee80211_sta *sta)
2974 {
2975 struct il_priv *il = hw->priv;
2976 struct il3945_sta_priv *sta_priv = (void *)sta->drv_priv;
2977 int ret;
2978 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
2979 u8 sta_id;
2980
2981 mutex_lock(&il->mutex);
2982 D_INFO("station %pM\n", sta->addr);
2983 sta_priv->common.sta_id = IL_INVALID_STATION;
2984
2985 ret = il_add_station_common(il, sta->addr, is_ap, sta, &sta_id);
2986 if (ret) {
2987 IL_ERR("Unable to add station %pM (%d)\n", sta->addr, ret);
2988
2989 mutex_unlock(&il->mutex);
2990 return ret;
2991 }
2992
2993 sta_priv->common.sta_id = sta_id;
2994
2995
2996 D_INFO("Initializing rate scaling for station %pM\n", sta->addr);
2997 il3945_rs_rate_init(il, sta, sta_id);
2998 mutex_unlock(&il->mutex);
2999
3000 return 0;
3001 }
3002
3003 static void
3004 il3945_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
3005 unsigned int *total_flags, u64 multicast)
3006 {
3007 struct il_priv *il = hw->priv;
3008 __le32 filter_or = 0, filter_nand = 0;
3009
3010 #define CHK(test, flag) do { \
3011 if (*total_flags & (test)) \
3012 filter_or |= (flag); \
3013 else \
3014 filter_nand |= (flag); \
3015 } while (0)
3016
3017 D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", changed_flags,
3018 *total_flags);
3019
3020 CHK(FIF_OTHER_BSS, RXON_FILTER_PROMISC_MSK);
3021 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3022 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3023
3024 #undef CHK
3025
3026 mutex_lock(&il->mutex);
3027
3028 il->staging.filter_flags &= ~filter_nand;
3029 il->staging.filter_flags |= filter_or;
3030
3031
3032
3033
3034
3035
3036
3037 mutex_unlock(&il->mutex);
3038
3039
3040
3041
3042
3043
3044
3045 *total_flags &=
3046 FIF_OTHER_BSS | FIF_ALLMULTI |
3047 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3048 }
3049
3050
3051
3052
3053
3054
3055
3056 #ifdef CONFIG_IWLEGACY_DEBUG
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069 static ssize_t
3070 il3945_show_debug_level(struct device *d, struct device_attribute *attr,
3071 char *buf)
3072 {
3073 struct il_priv *il = dev_get_drvdata(d);
3074 return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
3075 }
3076
3077 static ssize_t
3078 il3945_store_debug_level(struct device *d, struct device_attribute *attr,
3079 const char *buf, size_t count)
3080 {
3081 struct il_priv *il = dev_get_drvdata(d);
3082 unsigned long val;
3083 int ret;
3084
3085 ret = kstrtoul(buf, 0, &val);
3086 if (ret)
3087 IL_INFO("%s is not in hex or decimal form.\n", buf);
3088 else
3089 il->debug_level = val;
3090
3091 return strnlen(buf, count);
3092 }
3093
3094 static DEVICE_ATTR(debug_level, 0644, il3945_show_debug_level,
3095 il3945_store_debug_level);
3096
3097 #endif
3098
3099 static ssize_t
3100 il3945_show_temperature(struct device *d, struct device_attribute *attr,
3101 char *buf)
3102 {
3103 struct il_priv *il = dev_get_drvdata(d);
3104
3105 if (!il_is_alive(il))
3106 return -EAGAIN;
3107
3108 return sprintf(buf, "%d\n", il3945_hw_get_temperature(il));
3109 }
3110
3111 static DEVICE_ATTR(temperature, 0444, il3945_show_temperature, NULL);
3112
3113 static ssize_t
3114 il3945_show_tx_power(struct device *d, struct device_attribute *attr, char *buf)
3115 {
3116 struct il_priv *il = dev_get_drvdata(d);
3117 return sprintf(buf, "%d\n", il->tx_power_user_lmt);
3118 }
3119
3120 static ssize_t
3121 il3945_store_tx_power(struct device *d, struct device_attribute *attr,
3122 const char *buf, size_t count)
3123 {
3124 struct il_priv *il = dev_get_drvdata(d);
3125 char *p = (char *)buf;
3126 u32 val;
3127
3128 val = simple_strtoul(p, &p, 10);
3129 if (p == buf)
3130 IL_INFO(": %s is not in decimal form.\n", buf);
3131 else
3132 il3945_hw_reg_set_txpower(il, val);
3133
3134 return count;
3135 }
3136
3137 static DEVICE_ATTR(tx_power, 0644, il3945_show_tx_power, il3945_store_tx_power);
3138
3139 static ssize_t
3140 il3945_show_flags(struct device *d, struct device_attribute *attr, char *buf)
3141 {
3142 struct il_priv *il = dev_get_drvdata(d);
3143
3144 return sprintf(buf, "0x%04X\n", il->active.flags);
3145 }
3146
3147 static ssize_t
3148 il3945_store_flags(struct device *d, struct device_attribute *attr,
3149 const char *buf, size_t count)
3150 {
3151 struct il_priv *il = dev_get_drvdata(d);
3152 u32 flags = simple_strtoul(buf, NULL, 0);
3153
3154 mutex_lock(&il->mutex);
3155 if (le32_to_cpu(il->staging.flags) != flags) {
3156
3157 if (il_scan_cancel_timeout(il, 100))
3158 IL_WARN("Could not cancel scan.\n");
3159 else {
3160 D_INFO("Committing rxon.flags = 0x%04X\n", flags);
3161 il->staging.flags = cpu_to_le32(flags);
3162 il3945_commit_rxon(il);
3163 }
3164 }
3165 mutex_unlock(&il->mutex);
3166
3167 return count;
3168 }
3169
3170 static DEVICE_ATTR(flags, 0644, il3945_show_flags, il3945_store_flags);
3171
3172 static ssize_t
3173 il3945_show_filter_flags(struct device *d, struct device_attribute *attr,
3174 char *buf)
3175 {
3176 struct il_priv *il = dev_get_drvdata(d);
3177
3178 return sprintf(buf, "0x%04X\n", le32_to_cpu(il->active.filter_flags));
3179 }
3180
3181 static ssize_t
3182 il3945_store_filter_flags(struct device *d, struct device_attribute *attr,
3183 const char *buf, size_t count)
3184 {
3185 struct il_priv *il = dev_get_drvdata(d);
3186 u32 filter_flags = simple_strtoul(buf, NULL, 0);
3187
3188 mutex_lock(&il->mutex);
3189 if (le32_to_cpu(il->staging.filter_flags) != filter_flags) {
3190
3191 if (il_scan_cancel_timeout(il, 100))
3192 IL_WARN("Could not cancel scan.\n");
3193 else {
3194 D_INFO("Committing rxon.filter_flags = " "0x%04X\n",
3195 filter_flags);
3196 il->staging.filter_flags = cpu_to_le32(filter_flags);
3197 il3945_commit_rxon(il);
3198 }
3199 }
3200 mutex_unlock(&il->mutex);
3201
3202 return count;
3203 }
3204
3205 static DEVICE_ATTR(filter_flags, 0644, il3945_show_filter_flags,
3206 il3945_store_filter_flags);
3207
3208 static ssize_t
3209 il3945_show_measurement(struct device *d, struct device_attribute *attr,
3210 char *buf)
3211 {
3212 struct il_priv *il = dev_get_drvdata(d);
3213 struct il_spectrum_notification measure_report;
3214 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3215 u8 *data = (u8 *) &measure_report;
3216 unsigned long flags;
3217
3218 spin_lock_irqsave(&il->lock, flags);
3219 if (!(il->measurement_status & MEASUREMENT_READY)) {
3220 spin_unlock_irqrestore(&il->lock, flags);
3221 return 0;
3222 }
3223 memcpy(&measure_report, &il->measure_report, size);
3224 il->measurement_status = 0;
3225 spin_unlock_irqrestore(&il->lock, flags);
3226
3227 while (size && PAGE_SIZE - len) {
3228 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3229 PAGE_SIZE - len, true);
3230 len = strlen(buf);
3231 if (PAGE_SIZE - len)
3232 buf[len++] = '\n';
3233
3234 ofs += 16;
3235 size -= min(size, 16U);
3236 }
3237
3238 return len;
3239 }
3240
3241 static ssize_t
3242 il3945_store_measurement(struct device *d, struct device_attribute *attr,
3243 const char *buf, size_t count)
3244 {
3245 struct il_priv *il = dev_get_drvdata(d);
3246 struct ieee80211_measurement_params params = {
3247 .channel = le16_to_cpu(il->active.channel),
3248 .start_time = cpu_to_le64(il->_3945.last_tsf),
3249 .duration = cpu_to_le16(1),
3250 };
3251 u8 type = IL_MEASURE_BASIC;
3252 u8 buffer[32];
3253 u8 channel;
3254
3255 if (count) {
3256 char *p = buffer;
3257 strlcpy(buffer, buf, sizeof(buffer));
3258 channel = simple_strtoul(p, NULL, 0);
3259 if (channel)
3260 params.channel = channel;
3261
3262 p = buffer;
3263 while (*p && *p != ' ')
3264 p++;
3265 if (*p)
3266 type = simple_strtoul(p + 1, NULL, 0);
3267 }
3268
3269 D_INFO("Invoking measurement of type %d on " "channel %d (for '%s')\n",
3270 type, params.channel, buf);
3271 il3945_get_measurement(il, ¶ms, type);
3272
3273 return count;
3274 }
3275
3276 static DEVICE_ATTR(measurement, 0600, il3945_show_measurement,
3277 il3945_store_measurement);
3278
3279 static ssize_t
3280 il3945_store_retry_rate(struct device *d, struct device_attribute *attr,
3281 const char *buf, size_t count)
3282 {
3283 struct il_priv *il = dev_get_drvdata(d);
3284
3285 il->retry_rate = simple_strtoul(buf, NULL, 0);
3286 if (il->retry_rate <= 0)
3287 il->retry_rate = 1;
3288
3289 return count;
3290 }
3291
3292 static ssize_t
3293 il3945_show_retry_rate(struct device *d, struct device_attribute *attr,
3294 char *buf)
3295 {
3296 struct il_priv *il = dev_get_drvdata(d);
3297 return sprintf(buf, "%d", il->retry_rate);
3298 }
3299
3300 static DEVICE_ATTR(retry_rate, 0600, il3945_show_retry_rate,
3301 il3945_store_retry_rate);
3302
3303 static ssize_t
3304 il3945_show_channels(struct device *d, struct device_attribute *attr, char *buf)
3305 {
3306
3307 return 0;
3308 }
3309
3310 static DEVICE_ATTR(channels, 0400, il3945_show_channels, NULL);
3311
3312 static ssize_t
3313 il3945_show_antenna(struct device *d, struct device_attribute *attr, char *buf)
3314 {
3315 struct il_priv *il = dev_get_drvdata(d);
3316
3317 if (!il_is_alive(il))
3318 return -EAGAIN;
3319
3320 return sprintf(buf, "%d\n", il3945_mod_params.antenna);
3321 }
3322
3323 static ssize_t
3324 il3945_store_antenna(struct device *d, struct device_attribute *attr,
3325 const char *buf, size_t count)
3326 {
3327 struct il_priv *il __maybe_unused = dev_get_drvdata(d);
3328 int ant;
3329
3330 if (count == 0)
3331 return 0;
3332
3333 if (sscanf(buf, "%1i", &ant) != 1) {
3334 D_INFO("not in hex or decimal form.\n");
3335 return count;
3336 }
3337
3338 if (ant >= 0 && ant <= 2) {
3339 D_INFO("Setting antenna select to %d.\n", ant);
3340 il3945_mod_params.antenna = (enum il3945_antenna)ant;
3341 } else
3342 D_INFO("Bad antenna select value %d.\n", ant);
3343
3344 return count;
3345 }
3346
3347 static DEVICE_ATTR(antenna, 0644, il3945_show_antenna, il3945_store_antenna);
3348
3349 static ssize_t
3350 il3945_show_status(struct device *d, struct device_attribute *attr, char *buf)
3351 {
3352 struct il_priv *il = dev_get_drvdata(d);
3353 if (!il_is_alive(il))
3354 return -EAGAIN;
3355 return sprintf(buf, "0x%08x\n", (int)il->status);
3356 }
3357
3358 static DEVICE_ATTR(status, 0444, il3945_show_status, NULL);
3359
3360 static ssize_t
3361 il3945_dump_error_log(struct device *d, struct device_attribute *attr,
3362 const char *buf, size_t count)
3363 {
3364 struct il_priv *il = dev_get_drvdata(d);
3365 char *p = (char *)buf;
3366
3367 if (p[0] == '1')
3368 il3945_dump_nic_error_log(il);
3369
3370 return strnlen(buf, count);
3371 }
3372
3373 static DEVICE_ATTR(dump_errors, 0200, NULL, il3945_dump_error_log);
3374
3375
3376
3377
3378
3379
3380
3381 static void
3382 il3945_setup_deferred_work(struct il_priv *il)
3383 {
3384 il->workqueue = create_singlethread_workqueue(DRV_NAME);
3385
3386 init_waitqueue_head(&il->wait_command_queue);
3387
3388 INIT_WORK(&il->restart, il3945_bg_restart);
3389 INIT_WORK(&il->rx_replenish, il3945_bg_rx_replenish);
3390 INIT_DELAYED_WORK(&il->init_alive_start, il3945_bg_init_alive_start);
3391 INIT_DELAYED_WORK(&il->alive_start, il3945_bg_alive_start);
3392 INIT_DELAYED_WORK(&il->_3945.rfkill_poll, il3945_rfkill_poll);
3393
3394 il_setup_scan_deferred_work(il);
3395
3396 il3945_hw_setup_deferred_work(il);
3397
3398 timer_setup(&il->watchdog, il_bg_watchdog, 0);
3399
3400 tasklet_setup(&il->irq_tasklet, il3945_irq_tasklet);
3401 }
3402
3403 static void
3404 il3945_cancel_deferred_work(struct il_priv *il)
3405 {
3406 il3945_hw_cancel_deferred_work(il);
3407
3408 cancel_delayed_work_sync(&il->init_alive_start);
3409 cancel_delayed_work(&il->alive_start);
3410
3411 il_cancel_scan_deferred_work(il);
3412 }
3413
3414 static struct attribute *il3945_sysfs_entries[] = {
3415 &dev_attr_antenna.attr,
3416 &dev_attr_channels.attr,
3417 &dev_attr_dump_errors.attr,
3418 &dev_attr_flags.attr,
3419 &dev_attr_filter_flags.attr,
3420 &dev_attr_measurement.attr,
3421 &dev_attr_retry_rate.attr,
3422 &dev_attr_status.attr,
3423 &dev_attr_temperature.attr,
3424 &dev_attr_tx_power.attr,
3425 #ifdef CONFIG_IWLEGACY_DEBUG
3426 &dev_attr_debug_level.attr,
3427 #endif
3428 NULL
3429 };
3430
3431 static const struct attribute_group il3945_attribute_group = {
3432 .name = NULL,
3433 .attrs = il3945_sysfs_entries,
3434 };
3435
3436 static struct ieee80211_ops il3945_mac_ops __ro_after_init = {
3437 .tx = il3945_mac_tx,
3438 .start = il3945_mac_start,
3439 .stop = il3945_mac_stop,
3440 .add_interface = il_mac_add_interface,
3441 .remove_interface = il_mac_remove_interface,
3442 .change_interface = il_mac_change_interface,
3443 .config = il_mac_config,
3444 .configure_filter = il3945_configure_filter,
3445 .set_key = il3945_mac_set_key,
3446 .conf_tx = il_mac_conf_tx,
3447 .reset_tsf = il_mac_reset_tsf,
3448 .bss_info_changed = il_mac_bss_info_changed,
3449 .hw_scan = il_mac_hw_scan,
3450 .sta_add = il3945_mac_sta_add,
3451 .sta_remove = il_mac_sta_remove,
3452 .tx_last_beacon = il_mac_tx_last_beacon,
3453 .flush = il_mac_flush,
3454 };
3455
3456 static int
3457 il3945_init_drv(struct il_priv *il)
3458 {
3459 int ret;
3460 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
3461
3462 il->retry_rate = 1;
3463 il->beacon_skb = NULL;
3464
3465 spin_lock_init(&il->sta_lock);
3466 spin_lock_init(&il->hcmd_lock);
3467
3468 INIT_LIST_HEAD(&il->free_frames);
3469
3470 mutex_init(&il->mutex);
3471
3472 il->ieee_channels = NULL;
3473 il->ieee_rates = NULL;
3474 il->band = NL80211_BAND_2GHZ;
3475
3476 il->iw_mode = NL80211_IFTYPE_STATION;
3477 il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
3478
3479
3480 il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
3481
3482 if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
3483 IL_WARN("Unsupported EEPROM version: 0x%04X\n",
3484 eeprom->version);
3485 ret = -EINVAL;
3486 goto err;
3487 }
3488 ret = il_init_channel_map(il);
3489 if (ret) {
3490 IL_ERR("initializing regulatory failed: %d\n", ret);
3491 goto err;
3492 }
3493
3494
3495 if (il3945_txpower_set_from_eeprom(il)) {
3496 ret = -EIO;
3497 goto err_free_channel_map;
3498 }
3499
3500 ret = il_init_geos(il);
3501 if (ret) {
3502 IL_ERR("initializing geos failed: %d\n", ret);
3503 goto err_free_channel_map;
3504 }
3505 il3945_init_hw_rates(il, il->ieee_rates);
3506
3507 return 0;
3508
3509 err_free_channel_map:
3510 il_free_channel_map(il);
3511 err:
3512 return ret;
3513 }
3514
3515 #define IL3945_MAX_PROBE_REQUEST 200
3516
3517 static int
3518 il3945_setup_mac(struct il_priv *il)
3519 {
3520 int ret;
3521 struct ieee80211_hw *hw = il->hw;
3522
3523 hw->rate_control_algorithm = "iwl-3945-rs";
3524 hw->sta_data_size = sizeof(struct il3945_sta_priv);
3525 hw->vif_data_size = sizeof(struct il_vif_priv);
3526
3527
3528 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
3529 ieee80211_hw_set(hw, SUPPORTS_PS);
3530 ieee80211_hw_set(hw, SIGNAL_DBM);
3531 ieee80211_hw_set(hw, SPECTRUM_MGMT);
3532
3533 hw->wiphy->interface_modes =
3534 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC);
3535
3536 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
3537 hw->wiphy->regulatory_flags |= REGULATORY_CUSTOM_REG |
3538 REGULATORY_DISABLE_BEACON_HINTS;
3539
3540 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3541
3542 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
3543
3544 hw->wiphy->max_scan_ie_len = IL3945_MAX_PROBE_REQUEST - 24 - 2;
3545
3546
3547 hw->queues = 4;
3548
3549 if (il->bands[NL80211_BAND_2GHZ].n_channels)
3550 il->hw->wiphy->bands[NL80211_BAND_2GHZ] =
3551 &il->bands[NL80211_BAND_2GHZ];
3552
3553 if (il->bands[NL80211_BAND_5GHZ].n_channels)
3554 il->hw->wiphy->bands[NL80211_BAND_5GHZ] =
3555 &il->bands[NL80211_BAND_5GHZ];
3556
3557 il_leds_init(il);
3558
3559 wiphy_ext_feature_set(il->hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
3560
3561 ret = ieee80211_register_hw(il->hw);
3562 if (ret) {
3563 IL_ERR("Failed to register hw (error %d)\n", ret);
3564 return ret;
3565 }
3566 il->mac80211_registered = 1;
3567
3568 return 0;
3569 }
3570
3571 static int
3572 il3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3573 {
3574 int err = 0;
3575 struct il_priv *il;
3576 struct ieee80211_hw *hw;
3577 struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data);
3578 struct il3945_eeprom *eeprom;
3579 unsigned long flags;
3580
3581
3582
3583
3584
3585 hw = ieee80211_alloc_hw(sizeof(struct il_priv), &il3945_mac_ops);
3586 if (!hw) {
3587 err = -ENOMEM;
3588 goto out;
3589 }
3590 il = hw->priv;
3591 il->hw = hw;
3592 SET_IEEE80211_DEV(hw, &pdev->dev);
3593
3594 il->cmd_queue = IL39_CMD_QUEUE_NUM;
3595
3596 D_INFO("*** LOAD DRIVER ***\n");
3597 il->cfg = cfg;
3598 il->ops = &il3945_ops;
3599 #ifdef CONFIG_IWLEGACY_DEBUGFS
3600 il->debugfs_ops = &il3945_debugfs_ops;
3601 #endif
3602 il->pci_dev = pdev;
3603 il->inta_mask = CSR_INI_SET_MASK;
3604
3605
3606
3607
3608 pci_disable_link_state(pdev,
3609 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3610 PCIE_LINK_STATE_CLKPM);
3611
3612 if (pci_enable_device(pdev)) {
3613 err = -ENODEV;
3614 goto out_ieee80211_free_hw;
3615 }
3616
3617 pci_set_master(pdev);
3618
3619 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3620 if (err) {
3621 IL_WARN("No suitable DMA available.\n");
3622 goto out_pci_disable_device;
3623 }
3624
3625 pci_set_drvdata(pdev, il);
3626 err = pci_request_regions(pdev, DRV_NAME);
3627 if (err)
3628 goto out_pci_disable_device;
3629
3630
3631
3632
3633 il->hw_base = pci_ioremap_bar(pdev, 0);
3634 if (!il->hw_base) {
3635 err = -ENODEV;
3636 goto out_pci_release_regions;
3637 }
3638
3639 D_INFO("pci_resource_len = 0x%08llx\n",
3640 (unsigned long long)pci_resource_len(pdev, 0));
3641 D_INFO("pci_resource_base = %p\n", il->hw_base);
3642
3643
3644
3645 pci_write_config_byte(pdev, 0x41, 0x00);
3646
3647
3648
3649
3650 spin_lock_init(&il->reg_lock);
3651 spin_lock_init(&il->lock);
3652
3653
3654
3655
3656
3657
3658 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3659
3660
3661
3662
3663
3664
3665 err = il_eeprom_init(il);
3666 if (err) {
3667 IL_ERR("Unable to init EEPROM\n");
3668 goto out_iounmap;
3669 }
3670
3671 eeprom = (struct il3945_eeprom *)il->eeprom;
3672 D_INFO("MAC address: %pM\n", eeprom->mac_address);
3673 SET_IEEE80211_PERM_ADDR(il->hw, eeprom->mac_address);
3674
3675
3676
3677
3678
3679 err = il3945_hw_set_hw_params(il);
3680 if (err) {
3681 IL_ERR("failed to set hw settings\n");
3682 goto out_eeprom_free;
3683 }
3684
3685
3686
3687
3688
3689 err = il3945_init_drv(il);
3690 if (err) {
3691 IL_ERR("initializing driver failed\n");
3692 goto out_unset_hw_params;
3693 }
3694
3695 IL_INFO("Detected Intel Wireless WiFi Link %s\n", il->cfg->name);
3696
3697
3698
3699
3700
3701 spin_lock_irqsave(&il->lock, flags);
3702 il_disable_interrupts(il);
3703 spin_unlock_irqrestore(&il->lock, flags);
3704
3705 pci_enable_msi(il->pci_dev);
3706
3707 err = request_irq(il->pci_dev->irq, il_isr, IRQF_SHARED, DRV_NAME, il);
3708 if (err) {
3709 IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
3710 goto out_disable_msi;
3711 }
3712
3713 err = sysfs_create_group(&pdev->dev.kobj, &il3945_attribute_group);
3714 if (err) {
3715 IL_ERR("failed to create sysfs device attributes\n");
3716 goto out_release_irq;
3717 }
3718
3719 il_set_rxon_channel(il, &il->bands[NL80211_BAND_2GHZ].channels[5]);
3720 il3945_setup_deferred_work(il);
3721 il3945_setup_handlers(il);
3722 il_power_initialize(il);
3723
3724
3725
3726
3727
3728 il_enable_interrupts(il);
3729
3730 err = il3945_setup_mac(il);
3731 if (err)
3732 goto out_remove_sysfs;
3733
3734 il_dbgfs_register(il, DRV_NAME);
3735
3736
3737 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll, 2 * HZ);
3738
3739 return 0;
3740
3741 out_remove_sysfs:
3742 destroy_workqueue(il->workqueue);
3743 il->workqueue = NULL;
3744 sysfs_remove_group(&pdev->dev.kobj, &il3945_attribute_group);
3745 out_release_irq:
3746 free_irq(il->pci_dev->irq, il);
3747 out_disable_msi:
3748 pci_disable_msi(il->pci_dev);
3749 il_free_geos(il);
3750 il_free_channel_map(il);
3751 out_unset_hw_params:
3752 il3945_unset_hw_params(il);
3753 out_eeprom_free:
3754 il_eeprom_free(il);
3755 out_iounmap:
3756 iounmap(il->hw_base);
3757 out_pci_release_regions:
3758 pci_release_regions(pdev);
3759 out_pci_disable_device:
3760 pci_disable_device(pdev);
3761 out_ieee80211_free_hw:
3762 ieee80211_free_hw(il->hw);
3763 out:
3764 return err;
3765 }
3766
3767 static void
3768 il3945_pci_remove(struct pci_dev *pdev)
3769 {
3770 struct il_priv *il = pci_get_drvdata(pdev);
3771 unsigned long flags;
3772
3773 if (!il)
3774 return;
3775
3776 D_INFO("*** UNLOAD DRIVER ***\n");
3777
3778 il_dbgfs_unregister(il);
3779
3780 set_bit(S_EXIT_PENDING, &il->status);
3781
3782 il_leds_exit(il);
3783
3784 if (il->mac80211_registered) {
3785 ieee80211_unregister_hw(il->hw);
3786 il->mac80211_registered = 0;
3787 } else {
3788 il3945_down(il);
3789 }
3790
3791
3792
3793
3794
3795
3796
3797
3798 il_apm_stop(il);
3799
3800
3801
3802
3803 spin_lock_irqsave(&il->lock, flags);
3804 il_disable_interrupts(il);
3805 spin_unlock_irqrestore(&il->lock, flags);
3806
3807 il3945_synchronize_irq(il);
3808
3809 sysfs_remove_group(&pdev->dev.kobj, &il3945_attribute_group);
3810
3811 cancel_delayed_work_sync(&il->_3945.rfkill_poll);
3812
3813 il3945_dealloc_ucode_pci(il);
3814
3815 if (il->rxq.bd)
3816 il3945_rx_queue_free(il, &il->rxq);
3817 il3945_hw_txq_ctx_free(il);
3818
3819 il3945_unset_hw_params(il);
3820
3821
3822
3823
3824
3825
3826 destroy_workqueue(il->workqueue);
3827 il->workqueue = NULL;
3828
3829 free_irq(pdev->irq, il);
3830 pci_disable_msi(pdev);
3831
3832 iounmap(il->hw_base);
3833 pci_release_regions(pdev);
3834 pci_disable_device(pdev);
3835
3836 il_free_channel_map(il);
3837 il_free_geos(il);
3838 kfree(il->scan_cmd);
3839 dev_kfree_skb(il->beacon_skb);
3840 ieee80211_free_hw(il->hw);
3841 }
3842
3843
3844
3845
3846
3847
3848
3849 static struct pci_driver il3945_driver = {
3850 .name = DRV_NAME,
3851 .id_table = il3945_hw_card_ids,
3852 .probe = il3945_pci_probe,
3853 .remove = il3945_pci_remove,
3854 .driver.pm = IL_LEGACY_PM_OPS,
3855 };
3856
3857 static int __init
3858 il3945_init(void)
3859 {
3860
3861 int ret;
3862 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
3863 pr_info(DRV_COPYRIGHT "\n");
3864
3865
3866
3867
3868
3869 if (il3945_mod_params.disable_hw_scan) {
3870 pr_info("hw_scan is disabled\n");
3871 il3945_mac_ops.hw_scan = NULL;
3872 }
3873
3874 ret = il3945_rate_control_register();
3875 if (ret) {
3876 pr_err("Unable to register rate control algorithm: %d\n", ret);
3877 return ret;
3878 }
3879
3880 ret = pci_register_driver(&il3945_driver);
3881 if (ret) {
3882 pr_err("Unable to initialize PCI module\n");
3883 goto error_register;
3884 }
3885
3886 return ret;
3887
3888 error_register:
3889 il3945_rate_control_unregister();
3890 return ret;
3891 }
3892
3893 static void __exit
3894 il3945_exit(void)
3895 {
3896 pci_unregister_driver(&il3945_driver);
3897 il3945_rate_control_unregister();
3898 }
3899
3900 MODULE_FIRMWARE(IL3945_MODULE_FIRMWARE(IL3945_UCODE_API_MAX));
3901
3902 module_param_named(antenna, il3945_mod_params.antenna, int, 0444);
3903 MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
3904 module_param_named(swcrypto, il3945_mod_params.sw_crypto, int, 0444);
3905 MODULE_PARM_DESC(swcrypto, "using software crypto (default 1 [software])");
3906 module_param_named(disable_hw_scan, il3945_mod_params.disable_hw_scan, int,
3907 0444);
3908 MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 1)");
3909 #ifdef CONFIG_IWLEGACY_DEBUG
3910 module_param_named(debug, il_debug_level, uint, 0644);
3911 MODULE_PARM_DESC(debug, "debug output mask");
3912 #endif
3913 module_param_named(fw_restart, il3945_mod_params.restart_fw, int, 0444);
3914 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
3915
3916 module_exit(il3945_exit);
3917 module_init(il3945_init);