brcm80211/include/chipcommon.h

0001 // SPDX-License-Identifier: ISC
0002 /*
0003  * Copyright (c) 2010 Broadcom Corporation
0004  */
0005
0006 #ifndef _SBCHIPC_H
0007 #define _SBCHIPC_H
0008
0009 #include "defs.h"       /* for PAD macro */
0010
0011 #define CHIPCREGOFFS(field) offsetof(struct chipcregs, field)
0012
0013 struct chipcregs {
0014     u32 chipid;     /* 0x0 */
0015     u32 capabilities;
0016     u32 corecontrol;    /* corerev >= 1 */
0017     u32 bist;
0018
0019     /* OTP */
0020     u32 otpstatus;  /* 0x10, corerev >= 10 */
0021     u32 otpcontrol;
0022     u32 otpprog;
0023     u32 otplayout;  /* corerev >= 23 */
0024
0025     /* Interrupt control */
0026     u32 intstatus;  /* 0x20 */
0027     u32 intmask;
0028
0029     /* Chip specific regs */
0030     u32 chipcontrol;    /* 0x28, rev >= 11 */
0031     u32 chipstatus; /* 0x2c, rev >= 11 */
0032
0033     /* Jtag Master */
0034     u32 jtagcmd;        /* 0x30, rev >= 10 */
0035     u32 jtagir;
0036     u32 jtagdr;
0037     u32 jtagctrl;
0038
0039     /* serial flash interface registers */
0040     u32 flashcontrol;   /* 0x40 */
0041     u32 flashaddress;
0042     u32 flashdata;
0043     u32 PAD[1];
0044
0045     /* Silicon backplane configuration broadcast control */
0046     u32 broadcastaddress;   /* 0x50 */
0047     u32 broadcastdata;
0048
0049     /* gpio - cleared only by power-on-reset */
0050     u32 gpiopullup; /* 0x58, corerev >= 20 */
0051     u32 gpiopulldown;   /* 0x5c, corerev >= 20 */
0052     u32 gpioin;     /* 0x60 */
0053     u32 gpioout;        /* 0x64 */
0054     u32 gpioouten;  /* 0x68 */
0055     u32 gpiocontrol;    /* 0x6C */
0056     u32 gpiointpolarity;    /* 0x70 */
0057     u32 gpiointmask;    /* 0x74 */
0058
0059     /* GPIO events corerev >= 11 */
0060     u32 gpioevent;
0061     u32 gpioeventintmask;
0062
0063     /* Watchdog timer */
0064     u32 watchdog;   /* 0x80 */
0065
0066     /* GPIO events corerev >= 11 */
0067     u32 gpioeventintpolarity;
0068
0069     /* GPIO based LED powersave registers corerev >= 16 */
0070     u32 gpiotimerval;   /* 0x88 */
0071     u32 gpiotimeroutmask;
0072
0073     /* clock control */
0074     u32 clockcontrol_n; /* 0x90 */
0075     u32 clockcontrol_sb;    /* aka m0 */
0076     u32 clockcontrol_pci;   /* aka m1 */
0077     u32 clockcontrol_m2;    /* mii/uart/mipsref */
0078     u32 clockcontrol_m3;    /* cpu */
0079     u32 clkdiv;     /* corerev >= 3 */
0080     u32 gpiodebugsel;   /* corerev >= 28 */
0081     u32 capabilities_ext;   /* 0xac  */
0082
0083     /* pll delay registers (corerev >= 4) */
0084     u32 pll_on_delay;   /* 0xb0 */
0085     u32 fref_sel_delay;
0086     u32 slow_clk_ctl;   /* 5 < corerev < 10 */
0087     u32 PAD;
0088
0089     /* Instaclock registers (corerev >= 10) */
0090     u32 system_clk_ctl; /* 0xc0 */
0091     u32 clkstatestretch;
0092     u32 PAD[2];
0093
0094     /* Indirect backplane access (corerev >= 22) */
0095     u32 bp_addrlow; /* 0xd0 */
0096     u32 bp_addrhigh;
0097     u32 bp_data;
0098     u32 PAD;
0099     u32 bp_indaccess;
0100     u32 PAD[3];
0101
0102     /* More clock dividers (corerev >= 32) */
0103     u32 clkdiv2;
0104     u32 PAD[2];
0105
0106     /* In AI chips, pointer to erom */
0107     u32 eromptr;        /* 0xfc */
0108
0109     /* ExtBus control registers (corerev >= 3) */
0110     u32 pcmcia_config;  /* 0x100 */
0111     u32 pcmcia_memwait;
0112     u32 pcmcia_attrwait;
0113     u32 pcmcia_iowait;
0114     u32 ide_config;
0115     u32 ide_memwait;
0116     u32 ide_attrwait;
0117     u32 ide_iowait;
0118     u32 prog_config;
0119     u32 prog_waitcount;
0120     u32 flash_config;
0121     u32 flash_waitcount;
0122     u32 SECI_config;    /* 0x130 SECI configuration */
0123     u32 PAD[3];
0124
0125     /* Enhanced Coexistence Interface (ECI) registers (corerev >= 21) */
0126     u32 eci_output; /* 0x140 */
0127     u32 eci_control;
0128     u32 eci_inputlo;
0129     u32 eci_inputmi;
0130     u32 eci_inputhi;
0131     u32 eci_inputintpolaritylo;
0132     u32 eci_inputintpolaritymi;
0133     u32 eci_inputintpolarityhi;
0134     u32 eci_intmasklo;
0135     u32 eci_intmaskmi;
0136     u32 eci_intmaskhi;
0137     u32 eci_eventlo;
0138     u32 eci_eventmi;
0139     u32 eci_eventhi;
0140     u32 eci_eventmasklo;
0141     u32 eci_eventmaskmi;
0142     u32 eci_eventmaskhi;
0143     u32 PAD[3];
0144
0145     /* SROM interface (corerev >= 32) */
0146     u32 sromcontrol;    /* 0x190 */
0147     u32 sromaddress;
0148     u32 sromdata;
0149     u32 PAD[17];
0150
0151     /* Clock control and hardware workarounds (corerev >= 20) */
0152     u32 clk_ctl_st; /* 0x1e0 */
0153     u32 hw_war;
0154     u32 PAD[70];
0155
0156     /* UARTs */
0157     u8 uart0data;   /* 0x300 */
0158     u8 uart0imr;
0159     u8 uart0fcr;
0160     u8 uart0lcr;
0161     u8 uart0mcr;
0162     u8 uart0lsr;
0163     u8 uart0msr;
0164     u8 uart0scratch;
0165     u8 PAD[248];        /* corerev >= 1 */
0166
0167     u8 uart1data;   /* 0x400 */
0168     u8 uart1imr;
0169     u8 uart1fcr;
0170     u8 uart1lcr;
0171     u8 uart1mcr;
0172     u8 uart1lsr;
0173     u8 uart1msr;
0174     u8 uart1scratch;
0175     u32 PAD[62];
0176
0177     /* save/restore, corerev >= 48 */
0178     u32 sr_capability;          /* 0x500 */
0179     u32 sr_control0;            /* 0x504 */
0180     u32 sr_control1;            /* 0x508 */
0181     u32 gpio_control;           /* 0x50C */
0182     u32 PAD[60];
0183
0184     /* PMU registers (corerev >= 20) */
0185     u32 pmucontrol; /* 0x600 */
0186     u32 pmucapabilities;
0187     u32 pmustatus;
0188     u32 res_state;
0189     u32 res_pending;
0190     u32 pmutimer;
0191     u32 min_res_mask;
0192     u32 max_res_mask;
0193     u32 res_table_sel;
0194     u32 res_dep_mask;
0195     u32 res_updn_timer;
0196     u32 res_timer;
0197     u32 clkstretch;
0198     u32 pmuwatchdog;
0199     u32 gpiosel;        /* 0x638, rev >= 1 */
0200     u32 gpioenable; /* 0x63c, rev >= 1 */
0201     u32 res_req_timer_sel;
0202     u32 res_req_timer;
0203     u32 res_req_mask;
0204     u32 pmucapabilities_ext; /* 0x64c, pmurev >=15 */
0205     u32 chipcontrol_addr;   /* 0x650 */
0206     u32 chipcontrol_data;   /* 0x654 */
0207     u32 regcontrol_addr;
0208     u32 regcontrol_data;
0209     u32 pllcontrol_addr;
0210     u32 pllcontrol_data;
0211     u32 pmustrapopt;    /* 0x668, corerev >= 28 */
0212     u32 pmu_xtalfreq;   /* 0x66C, pmurev >= 10 */
0213     u32 retention_ctl;          /* 0x670, pmurev >= 15 */
0214     u32 PAD[3];
0215     u32 retention_grpidx;       /* 0x680 */
0216     u32 retention_grpctl;       /* 0x684 */
0217     u32 PAD[94];
0218     u16 sromotp[768];
0219 };
0220
0221 /* chipid */
0222 #define CID_ID_MASK     0x0000ffff  /* Chip Id mask */
0223 #define CID_REV_MASK        0x000f0000  /* Chip Revision mask */
0224 #define CID_REV_SHIFT       16  /* Chip Revision shift */
0225 #define CID_PKG_MASK        0x00f00000  /* Package Option mask */
0226 #define CID_PKG_SHIFT       20  /* Package Option shift */
0227 #define CID_CC_MASK     0x0f000000  /* CoreCount (corerev >= 4) */
0228 #define CID_CC_SHIFT        24
0229 #define CID_TYPE_MASK       0xf0000000  /* Chip Type */
0230 #define CID_TYPE_SHIFT      28
0231
0232 /* capabilities */
0233 #define CC_CAP_UARTS_MASK   0x00000003  /* Number of UARTs */
0234 #define CC_CAP_MIPSEB       0x00000004  /* MIPS is in big-endian mode */
0235 #define CC_CAP_UCLKSEL      0x00000018  /* UARTs clock select */
0236 /* UARTs are driven by internal divided clock */
0237 #define CC_CAP_UINTCLK      0x00000008
0238 #define CC_CAP_UARTGPIO     0x00000020  /* UARTs own GPIOs 15:12 */
0239 #define CC_CAP_EXTBUS_MASK  0x000000c0  /* External bus mask */
0240 #define CC_CAP_EXTBUS_NONE  0x00000000  /* No ExtBus present */
0241 #define CC_CAP_EXTBUS_FULL  0x00000040  /* ExtBus: PCMCIA, IDE & Prog */
0242 #define CC_CAP_EXTBUS_PROG  0x00000080  /* ExtBus: ProgIf only */
0243 #define CC_CAP_FLASH_MASK   0x00000700  /* Type of flash */
0244 #define CC_CAP_PLL_MASK     0x00038000  /* Type of PLL */
0245 #define CC_CAP_PWR_CTL      0x00040000  /* Power control */
0246 #define CC_CAP_OTPSIZE      0x00380000  /* OTP Size (0 = none) */
0247 #define CC_CAP_OTPSIZE_SHIFT    19  /* OTP Size shift */
0248 #define CC_CAP_OTPSIZE_BASE 5   /* OTP Size base */
0249 #define CC_CAP_JTAGP        0x00400000  /* JTAG Master Present */
0250 #define CC_CAP_ROM      0x00800000  /* Internal boot rom active */
0251 #define CC_CAP_BKPLN64      0x08000000  /* 64-bit backplane */
0252 #define CC_CAP_PMU      0x10000000  /* PMU Present, rev >= 20 */
0253 #define CC_CAP_SROM     0x40000000  /* Srom Present, rev >= 32 */
0254 /* Nand flash present, rev >= 35 */
0255 #define CC_CAP_NFLASH       0x80000000
0256
0257 #define CC_CAP2_SECI        0x00000001  /* SECI Present, rev >= 36 */
0258 /* GSIO (spi/i2c) present, rev >= 37 */
0259 #define CC_CAP2_GSIO        0x00000002
0260
0261 /* sr_control0, rev >= 48 */
0262 #define CC_SR_CTL0_ENABLE_MASK          BIT(0)
0263 #define CC_SR_CTL0_ENABLE_SHIFT     0
0264 #define CC_SR_CTL0_EN_SR_ENG_CLK_SHIFT  1 /* sr_clk to sr_memory enable */
0265 #define CC_SR_CTL0_RSRC_TRIGGER_SHIFT   2 /* Rising edge resource trigger 0 to
0266                        * sr_engine
0267                        */
0268 #define CC_SR_CTL0_MIN_DIV_SHIFT    6 /* Min division value for fast clk
0269                        * in sr_engine
0270                        */
0271 #define CC_SR_CTL0_EN_SBC_STBY_SHIFT        16
0272 #define CC_SR_CTL0_EN_SR_ALP_CLK_MASK_SHIFT 18
0273 #define CC_SR_CTL0_EN_SR_HT_CLK_SHIFT       19
0274 #define CC_SR_CTL0_ALLOW_PIC_SHIFT  20 /* Allow pic to separate power
0275                         * domains
0276                         */
0277 #define CC_SR_CTL0_MAX_SR_LQ_CLK_CNT_SHIFT  25
0278 #define CC_SR_CTL0_EN_MEM_DISABLE_FOR_SLEEP 30
0279
0280 /* pmucapabilities */
0281 #define PCAP_REV_MASK   0x000000ff
0282 #define PCAP_RC_MASK    0x00001f00
0283 #define PCAP_RC_SHIFT   8
0284 #define PCAP_TC_MASK    0x0001e000
0285 #define PCAP_TC_SHIFT   13
0286 #define PCAP_PC_MASK    0x001e0000
0287 #define PCAP_PC_SHIFT   17
0288 #define PCAP_VC_MASK    0x01e00000
0289 #define PCAP_VC_SHIFT   21
0290 #define PCAP_CC_MASK    0x1e000000
0291 #define PCAP_CC_SHIFT   25
0292 #define PCAP5_PC_MASK   0x003e0000  /* PMU corerev >= 5 */
0293 #define PCAP5_PC_SHIFT  17
0294 #define PCAP5_VC_MASK   0x07c00000
0295 #define PCAP5_VC_SHIFT  22
0296 #define PCAP5_CC_MASK   0xf8000000
0297 #define PCAP5_CC_SHIFT  27
0298 /* pmucapabilites_ext PMU rev >= 15 */
0299 #define PCAPEXT_SR_SUPPORTED_MASK   (1 << 1)
0300 /* retention_ctl PMU rev >= 15 */
0301 #define PMU_RCTL_MACPHY_DISABLE_MASK        (1 << 26)
0302 #define PMU_RCTL_LOGIC_DISABLE_MASK         (1 << 27)
0303
0304
0305 /*
0306 * Maximum delay for the PMU state transition in us.
0307 * This is an upper bound intended for spinwaits etc.
0308 */
0309 #define PMU_MAX_TRANSITION_DLY  15000
0310
0311 #endif              /* _SBCHIPC_H */