brcm80211/brcmsmac/phy_shim.h

0001 /*
0002  * Copyright (c) 2010 Broadcom Corporation
0003  *
0004  * Permission to use, copy, modify, and/or distribute this software for any
0005  * purpose with or without fee is hereby granted, provided that the above
0006  * copyright notice and this permission notice appear in all copies.
0007  *
0008  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0009  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0010  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
0011  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0012  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
0013  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
0014  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0015  */
0016
0017 /*
0018  * phy_shim.h: stuff defined in phy_shim.c and included only by the phy
0019  */
0020
0021 #ifndef _BRCM_PHY_SHIM_H_
0022 #define _BRCM_PHY_SHIM_H_
0023
0024 #include "types.h"
0025
0026 #define RADAR_TYPE_NONE     0   /* Radar type None */
0027 #define RADAR_TYPE_ETSI_1   1   /* ETSI 1 Radar type */
0028 #define RADAR_TYPE_ETSI_2   2   /* ETSI 2 Radar type */
0029 #define RADAR_TYPE_ETSI_3   3   /* ETSI 3 Radar type */
0030 #define RADAR_TYPE_ITU_E    4   /* ITU E Radar type */
0031 #define RADAR_TYPE_ITU_K    5   /* ITU K Radar type */
0032 #define RADAR_TYPE_UNCLASSIFIED 6   /* Unclassified Radar type  */
0033 #define RADAR_TYPE_BIN5     7   /* long pulse radar type */
0034 #define RADAR_TYPE_STG2     8   /* staggered-2 radar */
0035 #define RADAR_TYPE_STG3     9   /* staggered-3 radar */
0036 #define RADAR_TYPE_FRA      10  /* French radar */
0037
0038 /* French radar pulse widths */
0039 #define FRA_T1_20MHZ    52770
0040 #define FRA_T2_20MHZ    61538
0041 #define FRA_T3_20MHZ    66002
0042 #define FRA_T1_40MHZ    105541
0043 #define FRA_T2_40MHZ    123077
0044 #define FRA_T3_40MHZ    132004
0045 #define FRA_ERR_20MHZ   60
0046 #define FRA_ERR_40MHZ   120
0047
0048 #define ANTSEL_NA       0 /* No boardlevel selection available */
0049 #define ANTSEL_2x4      1 /* 2x4 boardlevel selection available */
0050 #define ANTSEL_2x3      2 /* 2x3 CB2 boardlevel selection available */
0051
0052 /* Rx Antenna diversity control values */
0053 #define ANT_RX_DIV_FORCE_0  0   /* Use antenna 0 */
0054 #define ANT_RX_DIV_FORCE_1  1   /* Use antenna 1 */
0055 #define ANT_RX_DIV_START_1  2   /* Choose starting with 1 */
0056 #define ANT_RX_DIV_START_0  3   /* Choose starting with 0 */
0057 #define ANT_RX_DIV_ENABLE   3   /* APHY bbConfig Enable RX Diversity */
0058 #define ANT_RX_DIV_DEF      ANT_RX_DIV_START_0 /* default antdiv setting */
0059
0060 #define WL_ANT_RX_MAX       2   /* max 2 receive antennas */
0061 #define WL_ANT_HT_RX_MAX    3   /* max 3 receive antennas/cores */
0062 #define WL_ANT_IDX_1        0   /* antenna index 1 */
0063 #define WL_ANT_IDX_2        1   /* antenna index 2 */
0064
0065 /* values for n_preamble_type */
0066 #define BRCMS_N_PREAMBLE_MIXEDMODE  0
0067 #define BRCMS_N_PREAMBLE_GF     1
0068 #define BRCMS_N_PREAMBLE_GF_BRCM          2
0069
0070 #define WL_TX_POWER_RATES_LEGACY    45
0071 #define WL_TX_POWER_MCS20_FIRST         12
0072 #define WL_TX_POWER_MCS20_NUM           16
0073 #define WL_TX_POWER_MCS40_FIRST         28
0074 #define WL_TX_POWER_MCS40_NUM           17
0075
0076
0077 #define WL_TX_POWER_RATES          101
0078 #define WL_TX_POWER_CCK_FIRST          0
0079 #define WL_TX_POWER_CCK_NUM        4
0080 /* Index for first 20MHz OFDM SISO rate */
0081 #define WL_TX_POWER_OFDM_FIRST         4
0082 /* Index for first 20MHz OFDM CDD rate */
0083 #define WL_TX_POWER_OFDM20_CDD_FIRST   12
0084 /* Index for first 40MHz OFDM SISO rate */
0085 #define WL_TX_POWER_OFDM40_SISO_FIRST  52
0086 /* Index for first 40MHz OFDM CDD rate */
0087 #define WL_TX_POWER_OFDM40_CDD_FIRST   60
0088 #define WL_TX_POWER_OFDM_NUM           8
0089 /* Index for first 20MHz MCS SISO rate */
0090 #define WL_TX_POWER_MCS20_SISO_FIRST   20
0091 /* Index for first 20MHz MCS CDD rate */
0092 #define WL_TX_POWER_MCS20_CDD_FIRST    28
0093 /* Index for first 20MHz MCS STBC rate */
0094 #define WL_TX_POWER_MCS20_STBC_FIRST   36
0095 /* Index for first 20MHz MCS SDM rate */
0096 #define WL_TX_POWER_MCS20_SDM_FIRST    44
0097 /* Index for first 40MHz MCS SISO rate */
0098 #define WL_TX_POWER_MCS40_SISO_FIRST   68
0099 /* Index for first 40MHz MCS CDD rate */
0100 #define WL_TX_POWER_MCS40_CDD_FIRST    76
0101 /* Index for first 40MHz MCS STBC rate */
0102 #define WL_TX_POWER_MCS40_STBC_FIRST   84
0103 /* Index for first 40MHz MCS SDM rate */
0104 #define WL_TX_POWER_MCS40_SDM_FIRST    92
0105 #define WL_TX_POWER_MCS_1_STREAM_NUM   8
0106 #define WL_TX_POWER_MCS_2_STREAM_NUM   8
0107 /* Index for 40MHz rate MCS 32 */
0108 #define WL_TX_POWER_MCS_32         100
0109 #define WL_TX_POWER_MCS_32_NUM         1
0110
0111 /* sslpnphy specifics */
0112 /* Index for first 20MHz MCS SISO rate */
0113 #define WL_TX_POWER_MCS20_SISO_FIRST_SSN   12
0114
0115 /* struct tx_power::flags bits */
0116 #define WL_TX_POWER_F_ENABLED   1
0117 #define WL_TX_POWER_F_HW    2
0118 #define WL_TX_POWER_F_MIMO  4
0119 #define WL_TX_POWER_F_SISO  8
0120
0121 /* values to force tx/rx chain */
0122 #define BRCMS_N_TXRX_CHAIN0     0
0123 #define BRCMS_N_TXRX_CHAIN1     1
0124
0125 struct brcms_phy;
0126
0127 struct phy_shim_info *wlc_phy_shim_attach(struct brcms_hardware *wlc_hw,
0128                       struct brcms_info *wl,
0129                       struct brcms_c_info *wlc);
0130 void wlc_phy_shim_detach(struct phy_shim_info *physhim);
0131
0132 /* PHY to WL utility functions */
0133 struct wlapi_timer *wlapi_init_timer(struct phy_shim_info *physhim,
0134                      void (*fn)(struct brcms_phy *pi),
0135                      void *arg, const char *name);
0136 void wlapi_free_timer(struct wlapi_timer *t);
0137 void wlapi_add_timer(struct wlapi_timer *t, uint ms, int periodic);
0138 bool wlapi_del_timer(struct wlapi_timer *t);
0139 void wlapi_intrson(struct phy_shim_info *physhim);
0140 u32 wlapi_intrsoff(struct phy_shim_info *physhim);
0141 void wlapi_intrsrestore(struct phy_shim_info *physhim, u32 macintmask);
0142
0143 void wlapi_bmac_write_shm(struct phy_shim_info *physhim, uint offset, u16 v);
0144 u16 wlapi_bmac_read_shm(struct phy_shim_info *physhim, uint offset);
0145 void wlapi_bmac_mhf(struct phy_shim_info *physhim, u8 idx, u16 mask, u16 val,
0146             int bands);
0147 void wlapi_bmac_corereset(struct phy_shim_info *physhim, u32 flags);
0148 void wlapi_suspend_mac_and_wait(struct phy_shim_info *physhim);
0149 void wlapi_switch_macfreq(struct phy_shim_info *physhim, u8 spurmode);
0150 void wlapi_enable_mac(struct phy_shim_info *physhim);
0151 void wlapi_bmac_mctrl(struct phy_shim_info *physhim, u32 mask, u32 val);
0152 void wlapi_bmac_phy_reset(struct phy_shim_info *physhim);
0153 void wlapi_bmac_bw_set(struct phy_shim_info *physhim, u16 bw);
0154 void wlapi_bmac_phyclk_fgc(struct phy_shim_info *physhim, bool clk);
0155 void wlapi_bmac_macphyclk_set(struct phy_shim_info *physhim, bool clk);
0156 void wlapi_bmac_core_phypll_ctl(struct phy_shim_info *physhim, bool on);
0157 void wlapi_bmac_core_phypll_reset(struct phy_shim_info *physhim);
0158 void wlapi_bmac_ucode_wake_override_phyreg_set(struct phy_shim_info *physhim);
0159 void wlapi_bmac_ucode_wake_override_phyreg_clear(struct phy_shim_info *physhim);
0160 void wlapi_bmac_write_template_ram(struct phy_shim_info *physhim, int o,
0161                    int len, void *buf);
0162 u16 wlapi_bmac_rate_shm_offset(struct phy_shim_info *physhim, u8 rate);
0163 void wlapi_ucode_sample_init(struct phy_shim_info *physhim);
0164 void wlapi_copyfrom_objmem(struct phy_shim_info *physhim, uint, void *buf,
0165                int, u32 sel);
0166 void wlapi_copyto_objmem(struct phy_shim_info *physhim, uint, const void *buf,
0167              int, u32);
0168
0169 void wlapi_high_update_phy_mode(struct phy_shim_info *physhim, u32 phy_mode);
0170 u16 wlapi_bmac_get_txant(struct phy_shim_info *physhim);
0171
0172 #endif              /* _BRCM_PHY_SHIM_H_ */