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0006 #ifndef _BRCM_PHY_LCN_H_
0007 #define _BRCM_PHY_LCN_H_
0008
0009 #include <types.h>
0010
0011 struct brcms_phy_lcnphy {
0012 int lcnphy_txrf_sp_9_override;
0013 u8 lcnphy_full_cal_channel;
0014 u8 lcnphy_cal_counter;
0015 u16 lcnphy_cal_temper;
0016 bool lcnphy_recal;
0017
0018 u8 lcnphy_rc_cap;
0019 u32 lcnphy_mcs20_po;
0020
0021 u8 lcnphy_tr_isolation_mid;
0022 u8 lcnphy_tr_isolation_low;
0023 u8 lcnphy_tr_isolation_hi;
0024
0025 u8 lcnphy_bx_arch;
0026 u8 lcnphy_rx_power_offset;
0027 u8 lcnphy_rssi_vf;
0028 u8 lcnphy_rssi_vc;
0029 u8 lcnphy_rssi_gs;
0030 u8 lcnphy_tssi_val;
0031 u8 lcnphy_rssi_vf_lowtemp;
0032 u8 lcnphy_rssi_vc_lowtemp;
0033 u8 lcnphy_rssi_gs_lowtemp;
0034
0035 u8 lcnphy_rssi_vf_hightemp;
0036 u8 lcnphy_rssi_vc_hightemp;
0037 u8 lcnphy_rssi_gs_hightemp;
0038
0039 s16 lcnphy_pa0b0;
0040 s16 lcnphy_pa0b1;
0041 s16 lcnphy_pa0b2;
0042
0043 u16 lcnphy_rawtempsense;
0044 u8 lcnphy_measPower;
0045 u8 lcnphy_tempsense_slope;
0046 u8 lcnphy_freqoffset_corr;
0047 u8 lcnphy_tempsense_option;
0048 u8 lcnphy_tempcorrx;
0049 bool lcnphy_iqcal_swp_dis;
0050 bool lcnphy_hw_iqcal_en;
0051 uint lcnphy_bandedge_corr;
0052 bool lcnphy_spurmod;
0053 u16 lcnphy_tssi_tx_cnt;
0054 u16 lcnphy_tssi_idx;
0055 u16 lcnphy_tssi_npt;
0056
0057 u16 lcnphy_target_tx_freq;
0058 s8 lcnphy_tx_power_idx_override;
0059 u16 lcnphy_noise_samples;
0060
0061 u32 lcnphy_papdRxGnIdx;
0062 u32 lcnphy_papd_rxGnCtrl_init;
0063
0064 u32 lcnphy_gain_idx_14_lowword;
0065 u32 lcnphy_gain_idx_14_hiword;
0066 u32 lcnphy_gain_idx_27_lowword;
0067 u32 lcnphy_gain_idx_27_hiword;
0068 s16 lcnphy_ofdmgainidxtableoffset;
0069 s16 lcnphy_dsssgainidxtableoffset;
0070 u32 lcnphy_tr_R_gain_val;
0071 u32 lcnphy_tr_T_gain_val;
0072 s8 lcnphy_input_pwr_offset_db;
0073 u16 lcnphy_Med_Low_Gain_db;
0074 u16 lcnphy_Very_Low_Gain_db;
0075 s8 lcnphy_lastsensed_temperature;
0076 s8 lcnphy_pkteng_rssi_slope;
0077 u8 lcnphy_saved_tx_user_target[TXP_NUM_RATES];
0078 u8 lcnphy_volt_winner;
0079 u8 lcnphy_volt_low;
0080 u8 lcnphy_54_48_36_24mbps_backoff;
0081 u8 lcnphy_11n_backoff;
0082 u8 lcnphy_lowerofdm;
0083 u8 lcnphy_cck;
0084 u8 lcnphy_psat_2pt3_detected;
0085 s32 lcnphy_lowest_Re_div_Im;
0086 s8 lcnphy_final_papd_cal_idx;
0087 u16 lcnphy_extstxctrl4;
0088 u16 lcnphy_extstxctrl0;
0089 u16 lcnphy_extstxctrl1;
0090 s16 lcnphy_cck_dig_filt_type;
0091 s16 lcnphy_ofdm_dig_filt_type;
0092 struct lcnphy_cal_results lcnphy_cal_results;
0093
0094 u8 lcnphy_psat_pwr;
0095 u8 lcnphy_psat_indx;
0096 s32 lcnphy_min_phase;
0097 u8 lcnphy_final_idx;
0098 u8 lcnphy_start_idx;
0099 u8 lcnphy_current_index;
0100 u16 lcnphy_logen_buf_1;
0101 u16 lcnphy_local_ovr_2;
0102 u16 lcnphy_local_oval_6;
0103 u16 lcnphy_local_oval_5;
0104 u16 lcnphy_logen_mixer_1;
0105
0106 u8 lcnphy_aci_stat;
0107 uint lcnphy_aci_start_time;
0108 s8 lcnphy_tx_power_offset[TXP_NUM_RATES];
0109 };
0110 #endif