0001
0002
0003
0004
0005
0006 #ifndef _BRCM_PHY_INT_H_
0007 #define _BRCM_PHY_INT_H_
0008
0009 #include <types.h>
0010 #include <brcmu_utils.h>
0011 #include <brcmu_wifi.h>
0012
0013 #define PHY_VERSION { 1, 82, 8, 0 }
0014
0015 #define LCNXN_BASEREV 16
0016
0017 struct phy_shim_info;
0018
0019 struct brcms_phy_srom_fem {
0020
0021 u8 tssipos;
0022
0023 u8 extpagain;
0024
0025 u8 pdetrange;
0026
0027 u8 triso;
0028
0029 u8 antswctrllut;
0030 };
0031
0032 #define ISNPHY(pi) PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_N)
0033 #define ISLCNPHY(pi) PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_LCN)
0034
0035 #define PHY_GET_RFATTN(rfgain) ((rfgain) & 0x0f)
0036 #define PHY_GET_PADMIX(rfgain) (((rfgain) & 0x10) >> 4)
0037 #define PHY_GET_RFGAINID(rfattn, padmix, width) ((rfattn) + ((padmix)*(width)))
0038 #define PHY_SAT(x, n) ((x) > ((1<<((n)-1))-1) ? ((1<<((n)-1))-1) : \
0039 ((x) < -(1<<((n)-1)) ? -(1<<((n)-1)) : (x)))
0040 #define PHY_SHIFT_ROUND(x, n) ((x) >= 0 ? ((x)+(1<<((n)-1)))>>(n) : (x)>>(n))
0041 #define PHY_HW_ROUND(x, s) ((x >> s) + ((x >> (s-1)) & (s != 0)))
0042
0043 #define CH_5G_GROUP 3
0044 #define A_LOW_CHANS 0
0045 #define A_MID_CHANS 1
0046 #define A_HIGH_CHANS 2
0047 #define CH_2G_GROUP 1
0048 #define G_ALL_CHANS 0
0049
0050 #define FIRST_REF5_CHANNUM 149
0051 #define LAST_REF5_CHANNUM 165
0052 #define FIRST_5G_CHAN 14
0053 #define LAST_5G_CHAN 50
0054 #define FIRST_MID_5G_CHAN 14
0055 #define LAST_MID_5G_CHAN 35
0056 #define FIRST_HIGH_5G_CHAN 36
0057 #define LAST_HIGH_5G_CHAN 41
0058 #define FIRST_LOW_5G_CHAN 42
0059 #define LAST_LOW_5G_CHAN 50
0060
0061 #define BASE_LOW_5G_CHAN 4900
0062 #define BASE_MID_5G_CHAN 5100
0063 #define BASE_HIGH_5G_CHAN 5500
0064
0065 #define CHAN5G_FREQ(chan) (5000 + chan*5)
0066 #define CHAN2G_FREQ(chan) (2407 + chan*5)
0067
0068 #define TXP_FIRST_CCK 0
0069 #define TXP_LAST_CCK 3
0070 #define TXP_FIRST_OFDM 4
0071 #define TXP_LAST_OFDM 11
0072 #define TXP_FIRST_OFDM_20_CDD 12
0073 #define TXP_LAST_OFDM_20_CDD 19
0074 #define TXP_FIRST_MCS_20_SISO 20
0075 #define TXP_LAST_MCS_20_SISO 27
0076 #define TXP_FIRST_MCS_20_CDD 28
0077 #define TXP_LAST_MCS_20_CDD 35
0078 #define TXP_FIRST_MCS_20_STBC 36
0079 #define TXP_LAST_MCS_20_STBC 43
0080 #define TXP_FIRST_MCS_20_SDM 44
0081 #define TXP_LAST_MCS_20_SDM 51
0082 #define TXP_FIRST_OFDM_40_SISO 52
0083 #define TXP_LAST_OFDM_40_SISO 59
0084 #define TXP_FIRST_OFDM_40_CDD 60
0085 #define TXP_LAST_OFDM_40_CDD 67
0086 #define TXP_FIRST_MCS_40_SISO 68
0087 #define TXP_LAST_MCS_40_SISO 75
0088 #define TXP_FIRST_MCS_40_CDD 76
0089 #define TXP_LAST_MCS_40_CDD 83
0090 #define TXP_FIRST_MCS_40_STBC 84
0091 #define TXP_LAST_MCS_40_STBC 91
0092 #define TXP_FIRST_MCS_40_SDM 92
0093 #define TXP_LAST_MCS_40_SDM 99
0094 #define TXP_MCS_32 100
0095 #define TXP_NUM_RATES 101
0096 #define ADJ_PWR_TBL_LEN 84
0097
0098 #define TXP_FIRST_SISO_MCS_20 20
0099 #define TXP_LAST_SISO_MCS_20 27
0100
0101 #define PHY_CORE_NUM_1 1
0102 #define PHY_CORE_NUM_2 2
0103 #define PHY_CORE_NUM_3 3
0104 #define PHY_CORE_NUM_4 4
0105 #define PHY_CORE_MAX PHY_CORE_NUM_4
0106 #define PHY_CORE_0 0
0107 #define PHY_CORE_1 1
0108 #define PHY_CORE_2 2
0109 #define PHY_CORE_3 3
0110
0111 #define MA_WINDOW_SZ 8
0112
0113 #define PHY_NOISE_SAMPLE_MON 1
0114 #define PHY_NOISE_SAMPLE_EXTERNAL 2
0115 #define PHY_NOISE_WINDOW_SZ 16
0116 #define PHY_NOISE_GLITCH_INIT_MA 10
0117 #define PHY_NOISE_GLITCH_INIT_MA_BADPlCP 10
0118 #define PHY_NOISE_STATE_MON 0x1
0119 #define PHY_NOISE_STATE_EXTERNAL 0x2
0120 #define PHY_NOISE_SAMPLE_LOG_NUM_NPHY 10
0121 #define PHY_NOISE_SAMPLE_LOG_NUM_UCODE 9
0122
0123 #define PHY_NOISE_OFFSETFACT_4322 (-103)
0124 #define PHY_NOISE_MA_WINDOW_SZ 2
0125
0126 #define PHY_RSSI_TABLE_SIZE 64
0127 #define RSSI_ANT_MERGE_MAX 0
0128 #define RSSI_ANT_MERGE_MIN 1
0129 #define RSSI_ANT_MERGE_AVG 2
0130
0131 #define PHY_TSSI_TABLE_SIZE 64
0132 #define APHY_TSSI_TABLE_SIZE 256
0133 #define TX_GAIN_TABLE_LENGTH 64
0134 #define DEFAULT_11A_TXP_IDX 24
0135 #define NUM_TSSI_FRAMES 4
0136 #define NULL_TSSI 0x7f
0137 #define NULL_TSSI_W 0x7f7f
0138
0139 #define PHY_PAPD_EPS_TBL_SIZE_LCNPHY 64
0140
0141 #define LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL 9
0142
0143 #define PHY_TXPWR_MIN 10
0144 #define PHY_TXPWR_MIN_NPHY 8
0145 #define RADIOPWR_OVERRIDE_DEF (-1)
0146
0147 #define PWRTBL_NUM_COEFF 3
0148
0149 #define SPURAVOID_DISABLE 0
0150 #define SPURAVOID_AUTO 1
0151 #define SPURAVOID_FORCEON 2
0152 #define SPURAVOID_FORCEON2 3
0153
0154 #define PHY_SW_TIMER_FAST 15
0155 #define PHY_SW_TIMER_SLOW 60
0156 #define PHY_SW_TIMER_GLACIAL 120
0157
0158 #define PHY_PERICAL_AUTO 0
0159 #define PHY_PERICAL_FULL 1
0160 #define PHY_PERICAL_PARTIAL 2
0161
0162 #define PHY_PERICAL_NODELAY 0
0163 #define PHY_PERICAL_INIT_DELAY 5
0164 #define PHY_PERICAL_ASSOC_DELAY 5
0165 #define PHY_PERICAL_WDOG_DELAY 5
0166
0167 #define MPHASE_TXCAL_NUMCMDS 2
0168
0169 #define PHY_PERICAL_MPHASE_PENDING(pi) \
0170 (pi->mphase_cal_phase_id > MPHASE_CAL_STATE_IDLE)
0171
0172 enum {
0173 MPHASE_CAL_STATE_IDLE = 0,
0174 MPHASE_CAL_STATE_INIT = 1,
0175 MPHASE_CAL_STATE_TXPHASE0,
0176 MPHASE_CAL_STATE_TXPHASE1,
0177 MPHASE_CAL_STATE_TXPHASE2,
0178 MPHASE_CAL_STATE_TXPHASE3,
0179 MPHASE_CAL_STATE_TXPHASE4,
0180 MPHASE_CAL_STATE_TXPHASE5,
0181 MPHASE_CAL_STATE_PAPDCAL,
0182 MPHASE_CAL_STATE_RXCAL,
0183 MPHASE_CAL_STATE_RSSICAL,
0184 MPHASE_CAL_STATE_IDLETSSI
0185 };
0186
0187 enum phy_cal_mode {
0188 CAL_FULL,
0189 CAL_RECAL,
0190 CAL_CURRECAL,
0191 CAL_DIGCAL,
0192 CAL_GCTRL,
0193 CAL_SOFT,
0194 CAL_DIGLO
0195 };
0196
0197 #define RDR_NTIERS 1
0198 #define RDR_TIER_SIZE 64
0199 #define RDR_LIST_SIZE (512/3)
0200 #define RDR_EPOCH_SIZE 40
0201 #define RDR_NANTENNAS 2
0202 #define RDR_NTIER_SIZE RDR_LIST_SIZE
0203 #define RDR_LP_BUFFER_SIZE 64
0204 #define LP_LEN_HIS_SIZE 10
0205
0206 #define STATIC_NUM_RF 32
0207 #define STATIC_NUM_BB 9
0208
0209 #define BB_MULT_MASK 0x0000ffff
0210 #define BB_MULT_VALID_MASK 0x80000000
0211
0212 #define PHY_CHAIN_TX_DISABLE_TEMP 115
0213 #define PHY_HYSTERESIS_DELTATEMP 5
0214
0215 #define SCAN_INPROG_PHY(pi) \
0216 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN))
0217
0218 #define PLT_INPROG_PHY(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_PLT))
0219
0220 #define ASSOC_INPROG_PHY(pi) \
0221 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_ASSOC))
0222
0223 #define SCAN_RM_IN_PROGRESS(pi) \
0224 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN | PHY_HOLD_FOR_RM))
0225
0226 #define PHY_MUTED(pi) \
0227 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_MUTE))
0228
0229 #define PUB_NOT_ASSOC(pi) \
0230 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_NOT_ASSOC))
0231
0232 struct phy_table_info {
0233 uint table;
0234 int q;
0235 uint max;
0236 };
0237
0238 struct phytbl_info {
0239 const void *tbl_ptr;
0240 u32 tbl_len;
0241 u32 tbl_id;
0242 u32 tbl_offset;
0243 u32 tbl_width;
0244 };
0245
0246 struct interference_info {
0247 u8 curr_home_channel;
0248 u16 crsminpwrthld_40_stored;
0249 u16 crsminpwrthld_20L_stored;
0250 u16 crsminpwrthld_20U_stored;
0251 u16 init_gain_code_core1_stored;
0252 u16 init_gain_code_core2_stored;
0253 u16 init_gain_codeb_core1_stored;
0254 u16 init_gain_codeb_core2_stored;
0255 u16 init_gain_table_stored[4];
0256
0257 u16 clip1_hi_gain_code_core1_stored;
0258 u16 clip1_hi_gain_code_core2_stored;
0259 u16 clip1_hi_gain_codeb_core1_stored;
0260 u16 clip1_hi_gain_codeb_core2_stored;
0261 u16 nb_clip_thresh_core1_stored;
0262 u16 nb_clip_thresh_core2_stored;
0263 u16 init_ofdmlna2gainchange_stored[4];
0264 u16 init_ccklna2gainchange_stored[4];
0265 u16 clip1_lo_gain_code_core1_stored;
0266 u16 clip1_lo_gain_code_core2_stored;
0267 u16 clip1_lo_gain_codeb_core1_stored;
0268 u16 clip1_lo_gain_codeb_core2_stored;
0269 u16 w1_clip_thresh_core1_stored;
0270 u16 w1_clip_thresh_core2_stored;
0271 u16 radio_2056_core1_rssi_gain_stored;
0272 u16 radio_2056_core2_rssi_gain_stored;
0273 u16 energy_drop_timeout_len_stored;
0274
0275 u16 ed_crs40_assertthld0_stored;
0276 u16 ed_crs40_assertthld1_stored;
0277 u16 ed_crs40_deassertthld0_stored;
0278 u16 ed_crs40_deassertthld1_stored;
0279 u16 ed_crs20L_assertthld0_stored;
0280 u16 ed_crs20L_assertthld1_stored;
0281 u16 ed_crs20L_deassertthld0_stored;
0282 u16 ed_crs20L_deassertthld1_stored;
0283 u16 ed_crs20U_assertthld0_stored;
0284 u16 ed_crs20U_assertthld1_stored;
0285 u16 ed_crs20U_deassertthld0_stored;
0286 u16 ed_crs20U_deassertthld1_stored;
0287
0288 u16 badplcp_ma;
0289 u16 badplcp_ma_previous;
0290 u16 badplcp_ma_total;
0291 u16 badplcp_ma_list[MA_WINDOW_SZ];
0292 int badplcp_ma_index;
0293 s16 pre_badplcp_cnt;
0294 s16 bphy_pre_badplcp_cnt;
0295
0296 u16 init_gain_core1;
0297 u16 init_gain_core2;
0298 u16 init_gainb_core1;
0299 u16 init_gainb_core2;
0300 u16 init_gain_rfseq[4];
0301
0302 u16 crsminpwr0;
0303 u16 crsminpwrl0;
0304 u16 crsminpwru0;
0305
0306 s16 crsminpwr_index;
0307
0308 u16 radio_2057_core1_rssi_wb1a_gc_stored;
0309 u16 radio_2057_core2_rssi_wb1a_gc_stored;
0310 u16 radio_2057_core1_rssi_wb1g_gc_stored;
0311 u16 radio_2057_core2_rssi_wb1g_gc_stored;
0312 u16 radio_2057_core1_rssi_wb2_gc_stored;
0313 u16 radio_2057_core2_rssi_wb2_gc_stored;
0314 u16 radio_2057_core1_rssi_nb_gc_stored;
0315 u16 radio_2057_core2_rssi_nb_gc_stored;
0316 };
0317
0318 struct aci_save_gphy {
0319 u16 rc_cal_ovr;
0320 u16 phycrsth1;
0321 u16 phycrsth2;
0322 u16 init_n1p1_gain;
0323 u16 p1_p2_gain;
0324 u16 n1_n2_gain;
0325 u16 n1_p1_gain;
0326 u16 div_search_gain;
0327 u16 div_p1_p2_gain;
0328 u16 div_search_gn_change;
0329 u16 table_7_2;
0330 u16 table_7_3;
0331 u16 cckshbits_gnref;
0332 u16 clip_thresh;
0333 u16 clip2_thresh;
0334 u16 clip3_thresh;
0335 u16 clip_p2_thresh;
0336 u16 clip_pwdn_thresh;
0337 u16 clip_n1p1_thresh;
0338 u16 clip_n1_pwdn_thresh;
0339 u16 bbconfig;
0340 u16 cthr_sthr_shdin;
0341 u16 energy;
0342 u16 clip_p1_p2_thresh;
0343 u16 threshold;
0344 u16 reg15;
0345 u16 reg16;
0346 u16 reg17;
0347 u16 div_srch_idx;
0348 u16 div_srch_p1_p2;
0349 u16 div_srch_gn_back;
0350 u16 ant_dwell;
0351 u16 ant_wr_settle;
0352 };
0353
0354 struct lo_complex_abgphy_info {
0355 s8 i;
0356 s8 q;
0357 };
0358
0359 struct nphy_iq_comp {
0360 s16 a0;
0361 s16 b0;
0362 s16 a1;
0363 s16 b1;
0364 };
0365
0366 struct nphy_txpwrindex {
0367 s8 index;
0368 s8 index_internal;
0369 s8 index_internal_save;
0370 u16 AfectrlOverride;
0371 u16 AfeCtrlDacGain;
0372 u16 rad_gain;
0373 u8 bbmult;
0374 u16 iqcomp_a;
0375 u16 iqcomp_b;
0376 u16 locomp;
0377 };
0378
0379 struct txiqcal_cache {
0380
0381 u16 txcal_coeffs_2G[8];
0382 u16 txcal_radio_regs_2G[8];
0383 struct nphy_iq_comp rxcal_coeffs_2G;
0384
0385 u16 txcal_coeffs_5G[8];
0386 u16 txcal_radio_regs_5G[8];
0387 struct nphy_iq_comp rxcal_coeffs_5G;
0388 };
0389
0390 struct nphy_pwrctrl {
0391 s8 max_pwr_2g;
0392 s8 idle_targ_2g;
0393 s16 pwrdet_2g_a1;
0394 s16 pwrdet_2g_b0;
0395 s16 pwrdet_2g_b1;
0396 s8 max_pwr_5gm;
0397 s8 idle_targ_5gm;
0398 s8 max_pwr_5gh;
0399 s8 max_pwr_5gl;
0400 s16 pwrdet_5gm_a1;
0401 s16 pwrdet_5gm_b0;
0402 s16 pwrdet_5gm_b1;
0403 s16 pwrdet_5gl_a1;
0404 s16 pwrdet_5gl_b0;
0405 s16 pwrdet_5gl_b1;
0406 s16 pwrdet_5gh_a1;
0407 s16 pwrdet_5gh_b0;
0408 s16 pwrdet_5gh_b1;
0409 s8 idle_targ_5gl;
0410 s8 idle_targ_5gh;
0411 s8 idle_tssi_2g;
0412 s8 idle_tssi_5g;
0413 s8 idle_tssi;
0414 s16 a1;
0415 s16 b0;
0416 s16 b1;
0417 };
0418
0419 struct nphy_txgains {
0420 u16 txlpf[2];
0421 u16 txgm[2];
0422 u16 pga[2];
0423 u16 pad[2];
0424 u16 ipa[2];
0425 };
0426
0427 #define PHY_NOISEVAR_BUFSIZE 10
0428
0429 struct nphy_noisevar_buf {
0430 int bufcount;
0431 int tone_id[PHY_NOISEVAR_BUFSIZE];
0432 u32 noise_vars[PHY_NOISEVAR_BUFSIZE];
0433 u32 min_noise_vars[PHY_NOISEVAR_BUFSIZE];
0434 };
0435
0436 struct rssical_cache {
0437 u16 rssical_radio_regs_2G[2];
0438 u16 rssical_phyregs_2G[12];
0439
0440 u16 rssical_radio_regs_5G[2];
0441 u16 rssical_phyregs_5G[12];
0442 };
0443
0444 struct lcnphy_cal_results {
0445
0446 u16 txiqlocal_a;
0447 u16 txiqlocal_b;
0448 u16 txiqlocal_didq;
0449 u8 txiqlocal_ei0;
0450 u8 txiqlocal_eq0;
0451 u8 txiqlocal_fi0;
0452 u8 txiqlocal_fq0;
0453
0454 u16 txiqlocal_bestcoeffs[11];
0455 u16 txiqlocal_bestcoeffs_valid;
0456
0457 u32 papd_eps_tbl[PHY_PAPD_EPS_TBL_SIZE_LCNPHY];
0458 u16 analog_gain_ref;
0459 u16 lut_begin;
0460 u16 lut_end;
0461 u16 lut_step;
0462 u16 rxcompdbm;
0463 u16 papdctrl;
0464 u16 sslpnCalibClkEnCtrl;
0465
0466 u16 rxiqcal_coeff_a0;
0467 u16 rxiqcal_coeff_b0;
0468 };
0469
0470 struct shared_phy {
0471 struct brcms_phy *phy_head;
0472 uint unit;
0473 struct phy_shim_info *physhim;
0474 uint corerev;
0475 u32 machwcap;
0476 bool up;
0477 bool clk;
0478 uint now;
0479 u16 vid;
0480 u16 did;
0481 uint chip;
0482 uint chiprev;
0483 uint chippkg;
0484 uint sromrev;
0485 uint boardtype;
0486 uint boardrev;
0487 u32 boardflags;
0488 u32 boardflags2;
0489 uint fast_timer;
0490 uint slow_timer;
0491 uint glacial_timer;
0492 u8 rx_antdiv;
0493 s8 phy_noise_window[MA_WINDOW_SZ];
0494 uint phy_noise_index;
0495 u8 hw_phytxchain;
0496 u8 hw_phyrxchain;
0497 u8 phytxchain;
0498 u8 phyrxchain;
0499 u8 rssi_mode;
0500 bool _rifs_phy;
0501 };
0502
0503 struct brcms_phy_pub {
0504 uint phy_type;
0505 uint phy_rev;
0506 u8 phy_corenum;
0507 u16 radioid;
0508 u8 radiorev;
0509 u8 radiover;
0510
0511 uint coreflags;
0512 uint ana_rev;
0513 bool abgphy_encore;
0514 };
0515
0516 struct phy_func_ptr {
0517 void (*init)(struct brcms_phy *);
0518 void (*calinit)(struct brcms_phy *);
0519 void (*chanset)(struct brcms_phy *, u16 chanspec);
0520 void (*txpwrrecalc)(struct brcms_phy *);
0521 int (*longtrn)(struct brcms_phy *, int);
0522 void (*txiqccget)(struct brcms_phy *, u16 *, u16 *);
0523 void (*txiqccset)(struct brcms_phy *, u16, u16);
0524 u16 (*txloccget)(struct brcms_phy *);
0525 void (*radioloftget)(struct brcms_phy *, u8 *, u8 *, u8 *, u8 *);
0526 void (*carrsuppr)(struct brcms_phy *);
0527 s32 (*rxsigpwr)(struct brcms_phy *, s32);
0528 void (*detach)(struct brcms_phy *);
0529 };
0530
0531 struct brcms_phy {
0532 struct brcms_phy_pub pubpi_ro;
0533 struct shared_phy *sh;
0534 struct phy_func_ptr pi_fptr;
0535
0536 union {
0537 struct brcms_phy_lcnphy *pi_lcnphy;
0538 } u;
0539 bool user_txpwr_at_rfport;
0540
0541 struct bcma_device *d11core;
0542 struct brcms_phy *next;
0543 struct brcms_phy_pub pubpi;
0544
0545 bool do_initcal;
0546 bool phytest_on;
0547 bool ofdm_rateset_war;
0548 bool bf_preempt_4306;
0549 u16 radio_chanspec;
0550 u8 antsel_type;
0551 u16 bw;
0552 u8 txpwr_percent;
0553 bool phy_init_por;
0554
0555 bool init_in_progress;
0556 bool initialized;
0557 bool sbtml_gm;
0558 uint refcnt;
0559 bool watchdog_override;
0560 u8 phynoise_state;
0561 uint phynoise_now;
0562 int phynoise_chan_watchdog;
0563 bool phynoise_polling;
0564 bool disable_percal;
0565 u32 measure_hold;
0566
0567 s16 txpa_2g[PWRTBL_NUM_COEFF];
0568 s16 txpa_2g_low_temp[PWRTBL_NUM_COEFF];
0569 s16 txpa_2g_high_temp[PWRTBL_NUM_COEFF];
0570 s16 txpa_5g_low[PWRTBL_NUM_COEFF];
0571 s16 txpa_5g_mid[PWRTBL_NUM_COEFF];
0572 s16 txpa_5g_hi[PWRTBL_NUM_COEFF];
0573
0574 u8 tx_srom_max_2g;
0575 u8 tx_srom_max_5g_low;
0576 u8 tx_srom_max_5g_mid;
0577 u8 tx_srom_max_5g_hi;
0578 u8 tx_srom_max_rate_2g[TXP_NUM_RATES];
0579 u8 tx_srom_max_rate_5g_low[TXP_NUM_RATES];
0580 u8 tx_srom_max_rate_5g_mid[TXP_NUM_RATES];
0581 u8 tx_srom_max_rate_5g_hi[TXP_NUM_RATES];
0582 u8 tx_user_target[TXP_NUM_RATES];
0583 s8 tx_power_offset[TXP_NUM_RATES];
0584 u8 tx_power_target[TXP_NUM_RATES];
0585
0586 struct brcms_phy_srom_fem srom_fem2g;
0587 struct brcms_phy_srom_fem srom_fem5g;
0588
0589 u8 tx_power_max;
0590 u8 tx_power_max_rate_ind;
0591 bool hwpwrctrl;
0592 u8 nphy_txpwrctrl;
0593 s8 nphy_txrx_chain;
0594 bool phy_5g_pwrgain;
0595
0596 u16 phy_wreg;
0597 u16 phy_wreg_limit;
0598
0599 s8 n_preamble_override;
0600 u8 antswitch;
0601 u8 aa2g, aa5g;
0602
0603 s8 idle_tssi[CH_5G_GROUP];
0604 s8 target_idle_tssi;
0605 s8 txpwr_est_Pout;
0606 u8 tx_power_min;
0607 u8 txpwr_limit[TXP_NUM_RATES];
0608 u8 txpwr_env_limit[TXP_NUM_RATES];
0609 u8 adj_pwr_tbl_nphy[ADJ_PWR_TBL_LEN];
0610
0611 bool channel_14_wide_filter;
0612
0613 bool txpwroverride;
0614 bool txpwridx_override_aphy;
0615 s16 radiopwr_override;
0616 u16 hwpwr_txcur;
0617 u8 saved_txpwr_idx;
0618
0619 bool edcrs_threshold_lock;
0620
0621 u32 tr_R_gain_val;
0622 u32 tr_T_gain_val;
0623
0624 s16 ofdm_analog_filt_bw_override;
0625 s16 cck_analog_filt_bw_override;
0626 s16 ofdm_rccal_override;
0627 s16 cck_rccal_override;
0628 u16 extlna_type;
0629
0630 uint interference_mode_crs_time;
0631 u16 crsglitch_prev;
0632 bool interference_mode_crs;
0633
0634 u32 phy_tx_tone_freq;
0635 uint phy_lastcal;
0636 bool phy_forcecal;
0637 bool phy_fixed_noise;
0638 u32 xtalfreq;
0639 u8 pdiv;
0640 s8 carrier_suppr_disable;
0641
0642 bool phy_bphy_evm;
0643 bool phy_bphy_rfcs;
0644 s8 phy_scraminit;
0645 u8 phy_gpiosel;
0646
0647 s16 phy_txcore_disable_temp;
0648 s16 phy_txcore_enable_temp;
0649 s8 phy_tempsense_offset;
0650 bool phy_txcore_heatedup;
0651
0652 u16 radiopwr;
0653 u16 bb_atten;
0654 u16 txctl1;
0655
0656 u16 mintxbias;
0657 u16 mintxmag;
0658 struct lo_complex_abgphy_info gphy_locomp_iq
0659 [STATIC_NUM_RF][STATIC_NUM_BB];
0660 s8 stats_11b_txpower[STATIC_NUM_RF][STATIC_NUM_BB];
0661 u16 gain_table[TX_GAIN_TABLE_LENGTH];
0662 bool loopback_gain;
0663 s16 max_lpback_gain_hdB;
0664 s16 trsw_rx_gain_hdB;
0665 u8 power_vec[8];
0666
0667 u16 rc_cal;
0668 int nrssi_table_delta;
0669 int nrssi_slope_scale;
0670 int nrssi_slope_offset;
0671 int min_rssi;
0672 int max_rssi;
0673
0674 s8 txpwridx;
0675 u8 min_txpower;
0676
0677 u8 a_band_high_disable;
0678
0679 u16 tx_vos;
0680 u16 global_tx_bb_dc_bias_loft;
0681
0682 int rf_max;
0683 int bb_max;
0684 int rf_list_size;
0685 int bb_list_size;
0686 u16 *rf_attn_list;
0687 u16 *bb_attn_list;
0688 u16 padmix_mask;
0689 u16 padmix_reg;
0690 u16 *txmag_list;
0691 uint txmag_len;
0692 bool txmag_enable;
0693
0694 s8 *a_tssi_to_dbm;
0695 s8 *m_tssi_to_dbm;
0696 s8 *l_tssi_to_dbm;
0697 s8 *h_tssi_to_dbm;
0698 u8 *hwtxpwr;
0699
0700 u16 freqtrack_saved_regs[2];
0701 int cur_interference_mode;
0702 bool hwpwrctrl_capable;
0703 bool temppwrctrl_capable;
0704
0705 uint phycal_nslope;
0706 uint phycal_noffset;
0707 uint phycal_mlo;
0708 uint phycal_txpower;
0709
0710 u8 phy_aa2g;
0711
0712 bool nphy_tableloaded;
0713 s8 nphy_rssisel;
0714 u32 nphy_bb_mult_save;
0715 u16 nphy_txiqlocal_bestc[11];
0716 bool nphy_txiqlocal_coeffsvalid;
0717 struct nphy_txpwrindex nphy_txpwrindex[PHY_CORE_NUM_2];
0718 struct nphy_pwrctrl nphy_pwrctrl_info[PHY_CORE_NUM_2];
0719 u16 cck2gpo;
0720 u32 ofdm2gpo;
0721 u32 ofdm5gpo;
0722 u32 ofdm5glpo;
0723 u32 ofdm5ghpo;
0724 u8 bw402gpo;
0725 u8 bw405gpo;
0726 u8 bw405glpo;
0727 u8 bw405ghpo;
0728 u8 cdd2gpo;
0729 u8 cdd5gpo;
0730 u8 cdd5glpo;
0731 u8 cdd5ghpo;
0732 u8 stbc2gpo;
0733 u8 stbc5gpo;
0734 u8 stbc5glpo;
0735 u8 stbc5ghpo;
0736 u8 bwdup2gpo;
0737 u8 bwdup5gpo;
0738 u8 bwdup5glpo;
0739 u8 bwdup5ghpo;
0740 u16 mcs2gpo[8];
0741 u16 mcs5gpo[8];
0742 u16 mcs5glpo[8];
0743 u16 mcs5ghpo[8];
0744 u32 nphy_rxcalparams;
0745
0746 u8 phy_spuravoid;
0747 bool phy_isspuravoid;
0748
0749 u8 phy_pabias;
0750 u8 nphy_papd_skip;
0751 u8 nphy_tssi_slope;
0752
0753 s16 nphy_noise_win[PHY_CORE_MAX][PHY_NOISE_WINDOW_SZ];
0754 u8 nphy_noise_index;
0755
0756 bool nphy_gain_boost;
0757 bool nphy_elna_gain_config;
0758 u16 old_bphy_test;
0759 u16 old_bphy_testcontrol;
0760
0761 bool phyhang_avoid;
0762
0763 bool rssical_nphy;
0764 u8 nphy_perical;
0765 uint nphy_perical_last;
0766 u8 cal_type_override;
0767 u8 mphase_cal_phase_id;
0768 u8 mphase_txcal_cmdidx;
0769 u8 mphase_txcal_numcmds;
0770 u16 mphase_txcal_bestcoeffs[11];
0771 u16 nphy_txiqlocal_chanspec;
0772 u16 nphy_iqcal_chanspec_2G;
0773 u16 nphy_iqcal_chanspec_5G;
0774 u16 nphy_rssical_chanspec_2G;
0775 u16 nphy_rssical_chanspec_5G;
0776 struct wlapi_timer *phycal_timer;
0777 bool use_int_tx_iqlo_cal_nphy;
0778 bool internal_tx_iqlo_cal_tapoff_intpa_nphy;
0779 s16 nphy_lastcal_temp;
0780
0781 struct txiqcal_cache calibration_cache;
0782 struct rssical_cache rssical_cache;
0783
0784 u8 nphy_txpwr_idx[2];
0785 u8 nphy_papd_cal_type;
0786 uint nphy_papd_last_cal;
0787 u16 nphy_papd_tx_gain_at_last_cal[2];
0788 u8 nphy_papd_cal_gain_index[2];
0789 s16 nphy_papd_epsilon_offset[2];
0790 bool nphy_papd_recal_enable;
0791 u32 nphy_papd_recal_counter;
0792 bool nphy_force_papd_cal;
0793 bool nphy_papdcomp;
0794 bool ipa2g_on;
0795 bool ipa5g_on;
0796
0797 u16 classifier_state;
0798 u16 clip_state[2];
0799 uint nphy_deaf_count;
0800 u8 rxiq_samps;
0801 u8 rxiq_antsel;
0802
0803 u16 rfctrlIntc1_save;
0804 u16 rfctrlIntc2_save;
0805 bool first_cal_after_assoc;
0806 u16 tx_rx_cal_radio_saveregs[22];
0807 u16 tx_rx_cal_phy_saveregs[15];
0808
0809 u8 nphy_cal_orig_pwr_idx[2];
0810 u8 nphy_txcal_pwr_idx[2];
0811 u8 nphy_rxcal_pwr_idx[2];
0812 u16 nphy_cal_orig_tx_gain[2];
0813 struct nphy_txgains nphy_cal_target_gain;
0814 u16 nphy_txcal_bbmult;
0815 u16 nphy_gmval;
0816
0817 u16 nphy_saved_bbconf;
0818
0819 bool nphy_gband_spurwar_en;
0820 bool nphy_gband_spurwar2_en;
0821 bool nphy_aband_spurwar_en;
0822 u16 nphy_rccal_value;
0823 u16 nphy_crsminpwr[3];
0824 struct nphy_noisevar_buf nphy_saved_noisevars;
0825 bool nphy_anarxlpf_adjusted;
0826 bool nphy_crsminpwr_adjusted;
0827 bool nphy_noisevars_adjusted;
0828
0829 bool nphy_rxcal_active;
0830 u16 radar_percal_mask;
0831 bool dfs_lp_buffer_nphy;
0832
0833 u16 nphy_fineclockgatecontrol;
0834
0835 s8 rx2tx_biasentry;
0836
0837 u16 crsminpwr0;
0838 u16 crsminpwrl0;
0839 u16 crsminpwru0;
0840 s16 noise_crsminpwr_index;
0841 u16 init_gain_core1;
0842 u16 init_gain_core2;
0843 u16 init_gainb_core1;
0844 u16 init_gainb_core2;
0845 u8 aci_noise_curr_channel;
0846 u16 init_gain_rfseq[4];
0847
0848 bool radio_is_on;
0849
0850 bool nphy_sample_play_lpf_bw_ctl_ovr;
0851
0852 u16 tbl_data_hi;
0853 u16 tbl_data_lo;
0854 u16 tbl_addr;
0855
0856 uint tbl_save_id;
0857 uint tbl_save_offset;
0858
0859 u8 txpwrctrl;
0860 s8 txpwrindex[PHY_CORE_MAX];
0861
0862 u8 phycal_tempdelta;
0863 u32 mcs20_po;
0864 u32 mcs40_po;
0865 struct wiphy *wiphy;
0866 };
0867
0868 struct cs32 {
0869 s32 q;
0870 s32 i;
0871 };
0872
0873 struct radio_regs {
0874 u16 address;
0875 u32 init_a;
0876 u32 init_g;
0877 u8 do_init_a;
0878 u8 do_init_g;
0879 };
0880
0881 struct radio_20xx_regs {
0882 u16 address;
0883 u8 init;
0884 u8 do_init;
0885 };
0886
0887 struct lcnphy_radio_regs {
0888 u16 address;
0889 u8 init_a;
0890 u8 init_g;
0891 u8 do_init_a;
0892 u8 do_init_g;
0893 };
0894
0895 u16 read_phy_reg(struct brcms_phy *pi, u16 addr);
0896 void write_phy_reg(struct brcms_phy *pi, u16 addr, u16 val);
0897 void and_phy_reg(struct brcms_phy *pi, u16 addr, u16 val);
0898 void or_phy_reg(struct brcms_phy *pi, u16 addr, u16 val);
0899 void mod_phy_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val);
0900
0901 u16 read_radio_reg(struct brcms_phy *pi, u16 addr);
0902 void or_radio_reg(struct brcms_phy *pi, u16 addr, u16 val);
0903 void and_radio_reg(struct brcms_phy *pi, u16 addr, u16 val);
0904 void mod_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val);
0905 void xor_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask);
0906
0907 void write_radio_reg(struct brcms_phy *pi, u16 addr, u16 val);
0908
0909 void wlc_phyreg_enter(struct brcms_phy_pub *pih);
0910 void wlc_phyreg_exit(struct brcms_phy_pub *pih);
0911 void wlc_radioreg_enter(struct brcms_phy_pub *pih);
0912 void wlc_radioreg_exit(struct brcms_phy_pub *pih);
0913
0914 void wlc_phy_read_table(struct brcms_phy *pi,
0915 const struct phytbl_info *ptbl_info,
0916 u16 tblAddr, u16 tblDataHi, u16 tblDatalo);
0917 void wlc_phy_write_table(struct brcms_phy *pi,
0918 const struct phytbl_info *ptbl_info,
0919 u16 tblAddr, u16 tblDataHi, u16 tblDatalo);
0920 void wlc_phy_table_addr(struct brcms_phy *pi, uint tbl_id, uint tbl_offset,
0921 u16 tblAddr, u16 tblDataHi, u16 tblDataLo);
0922 void wlc_phy_table_data_write(struct brcms_phy *pi, uint width, u32 val);
0923
0924 void write_phy_channel_reg(struct brcms_phy *pi, uint val);
0925 void wlc_phy_txpower_update_shm(struct brcms_phy *pi);
0926
0927 u8 wlc_phy_nbits(s32 value);
0928 void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_dB, u8 core);
0929
0930 uint wlc_phy_init_radio_regs_allbands(struct brcms_phy *pi,
0931 struct radio_20xx_regs *radioregs);
0932 uint wlc_phy_init_radio_regs(struct brcms_phy *pi,
0933 const struct radio_regs *radioregs,
0934 u16 core_offset);
0935
0936 void wlc_phy_txpower_ipa_upd(struct brcms_phy *pi);
0937
0938 void wlc_phy_do_dummy_tx(struct brcms_phy *pi, bool ofdm, bool pa_on);
0939 void wlc_phy_papd_decode_epsilon(u32 epsilon, s32 *eps_real, s32 *eps_imag);
0940
0941 void wlc_phy_cal_perical_mphase_reset(struct brcms_phy *pi);
0942 void wlc_phy_cal_perical_mphase_restart(struct brcms_phy *pi);
0943
0944 bool wlc_phy_attach_nphy(struct brcms_phy *pi);
0945 bool wlc_phy_attach_lcnphy(struct brcms_phy *pi);
0946
0947 void wlc_phy_detach_lcnphy(struct brcms_phy *pi);
0948
0949 void wlc_phy_init_nphy(struct brcms_phy *pi);
0950 void wlc_phy_init_lcnphy(struct brcms_phy *pi);
0951
0952 void wlc_phy_cal_init_nphy(struct brcms_phy *pi);
0953 void wlc_phy_cal_init_lcnphy(struct brcms_phy *pi);
0954
0955 void wlc_phy_chanspec_set_nphy(struct brcms_phy *pi, u16 chanspec);
0956 void wlc_phy_chanspec_set_lcnphy(struct brcms_phy *pi, u16 chanspec);
0957 void wlc_phy_chanspec_set_fixup_lcnphy(struct brcms_phy *pi, u16 chanspec);
0958 int wlc_phy_channel2freq(uint channel);
0959 int wlc_phy_chanspec_freq2bandrange_lpssn(uint);
0960 int wlc_phy_chanspec_bandrange_get(struct brcms_phy *, u16 chanspec);
0961
0962 void wlc_lcnphy_set_tx_pwr_ctrl(struct brcms_phy *pi, u16 mode);
0963 s8 wlc_lcnphy_get_current_tx_pwr_idx(struct brcms_phy *pi);
0964
0965 void wlc_phy_txpower_recalc_target_nphy(struct brcms_phy *pi);
0966 void wlc_lcnphy_txpower_recalc_target(struct brcms_phy *pi);
0967 void wlc_phy_txpower_recalc_target_lcnphy(struct brcms_phy *pi);
0968
0969 void wlc_lcnphy_set_tx_pwr_by_index(struct brcms_phy *pi, int index);
0970 void wlc_lcnphy_tx_pu(struct brcms_phy *pi, bool bEnable);
0971 void wlc_lcnphy_stop_tx_tone(struct brcms_phy *pi);
0972 void wlc_lcnphy_start_tx_tone(struct brcms_phy *pi, s32 f_kHz, u16 max_val,
0973 bool iqcalmode);
0974
0975 void wlc_phy_txpower_sromlimit_get_nphy(struct brcms_phy *pi, uint chan,
0976 u8 *max_pwr, u8 rate_id);
0977 void wlc_phy_ofdm_to_mcs_powers_nphy(u8 *power, u8 rate_mcs_start,
0978 u8 rate_mcs_end, u8 rate_ofdm_start);
0979 void wlc_phy_mcs_to_ofdm_powers_nphy(u8 *power, u8 rate_ofdm_start,
0980 u8 rate_ofdm_end, u8 rate_mcs_start);
0981
0982 u16 wlc_lcnphy_tempsense(struct brcms_phy *pi, bool mode);
0983 s16 wlc_lcnphy_tempsense_new(struct brcms_phy *pi, bool mode);
0984 s8 wlc_lcnphy_tempsense_degree(struct brcms_phy *pi, bool mode);
0985 s8 wlc_lcnphy_vbatsense(struct brcms_phy *pi, bool mode);
0986 void wlc_phy_carrier_suppress_lcnphy(struct brcms_phy *pi);
0987 void wlc_lcnphy_crsuprs(struct brcms_phy *pi, int channel);
0988 void wlc_lcnphy_epa_switch(struct brcms_phy *pi, bool mode);
0989 void wlc_2064_vco_cal(struct brcms_phy *pi);
0990
0991 void wlc_phy_txpower_recalc_target(struct brcms_phy *pi);
0992
0993 #define LCNPHY_TBL_ID_PAPDCOMPDELTATBL 0x18
0994 #define LCNPHY_TX_POWER_TABLE_SIZE 128
0995 #define LCNPHY_MAX_TX_POWER_INDEX (LCNPHY_TX_POWER_TABLE_SIZE - 1)
0996 #define LCNPHY_TBL_ID_TXPWRCTL 0x07
0997 #define LCNPHY_TX_PWR_CTRL_OFF 0
0998 #define LCNPHY_TX_PWR_CTRL_SW (0x1 << 15)
0999 #define LCNPHY_TX_PWR_CTRL_HW ((0x1 << 15) | \
1000 (0x1 << 14) | \
1001 (0x1 << 13))
1002
1003 #define LCNPHY_TX_PWR_CTRL_TEMPBASED 0xE001
1004
1005 void wlc_lcnphy_write_table(struct brcms_phy *pi,
1006 const struct phytbl_info *pti);
1007 void wlc_lcnphy_read_table(struct brcms_phy *pi, struct phytbl_info *pti);
1008 void wlc_lcnphy_set_tx_iqcc(struct brcms_phy *pi, u16 a, u16 b);
1009 void wlc_lcnphy_set_tx_locc(struct brcms_phy *pi, u16 didq);
1010 void wlc_lcnphy_get_tx_iqcc(struct brcms_phy *pi, u16 *a, u16 *b);
1011 u16 wlc_lcnphy_get_tx_locc(struct brcms_phy *pi);
1012 void wlc_lcnphy_get_radio_loft(struct brcms_phy *pi, u8 *ei0, u8 *eq0, u8 *fi0,
1013 u8 *fq0);
1014 void wlc_lcnphy_calib_modes(struct brcms_phy *pi, uint mode);
1015 void wlc_lcnphy_deaf_mode(struct brcms_phy *pi, bool mode);
1016 bool wlc_phy_tpc_isenabled_lcnphy(struct brcms_phy *pi);
1017 void wlc_lcnphy_tx_pwr_update_npt(struct brcms_phy *pi);
1018 s32 wlc_lcnphy_tssi2dbm(s32 tssi, s32 a1, s32 b0, s32 b1);
1019 void wlc_lcnphy_get_tssi(struct brcms_phy *pi, s8 *ofdm_pwr, s8 *cck_pwr);
1020 void wlc_lcnphy_tx_power_adjustment(struct brcms_phy_pub *ppi);
1021
1022 s32 wlc_lcnphy_rx_signal_power(struct brcms_phy *pi, s32 gain_index);
1023
1024 #define NPHY_MAX_HPVGA1_INDEX 10
1025 #define NPHY_DEF_HPVGA1_INDEXLIMIT 7
1026
1027 struct phy_iq_est {
1028 s32 iq_prod;
1029 u32 i_pwr;
1030 u32 q_pwr;
1031 };
1032
1033 void wlc_phy_stay_in_carriersearch_nphy(struct brcms_phy *pi, bool enable);
1034 void wlc_nphy_deaf_mode(struct brcms_phy *pi, bool mode);
1035
1036 #define wlc_phy_write_table_nphy(pi, pti) \
1037 wlc_phy_write_table(pi, pti, 0x72, 0x74, 0x73)
1038
1039 #define wlc_phy_read_table_nphy(pi, pti) \
1040 wlc_phy_read_table(pi, pti, 0x72, 0x74, 0x73)
1041
1042 #define wlc_nphy_table_addr(pi, id, off) \
1043 wlc_phy_table_addr((pi), (id), (off), 0x72, 0x74, 0x73)
1044
1045 #define wlc_nphy_table_data_write(pi, w, v) \
1046 wlc_phy_table_data_write((pi), (w), (v))
1047
1048 void wlc_phy_table_read_nphy(struct brcms_phy *pi, u32, u32 l, u32 o, u32 w,
1049 void *d);
1050 void wlc_phy_table_write_nphy(struct brcms_phy *pi, u32, u32, u32, u32,
1051 const void *);
1052
1053 #define PHY_IPA(pi) \
1054 ((pi->ipa2g_on && CHSPEC_IS2G(pi->radio_chanspec)) || \
1055 (pi->ipa5g_on && CHSPEC_IS5G(pi->radio_chanspec)))
1056
1057 #define BRCMS_PHY_WAR_PR51571(pi) \
1058 if (NREV_LT((pi)->pubpi.phy_rev, 3)) \
1059 (void)bcma_read32(pi->d11core, D11REGOFFS(maccontrol))
1060
1061 void wlc_phy_cal_perical_nphy_run(struct brcms_phy *pi, u8 caltype);
1062 void wlc_phy_aci_reset_nphy(struct brcms_phy *pi);
1063 void wlc_phy_pa_override_nphy(struct brcms_phy *pi, bool en);
1064
1065 u8 wlc_phy_get_chan_freq_range_nphy(struct brcms_phy *pi, uint chan);
1066 void wlc_phy_switch_radio_nphy(struct brcms_phy *pi, bool on);
1067
1068 void wlc_phy_stf_chain_upd_nphy(struct brcms_phy *pi);
1069
1070 void wlc_phy_force_rfseq_nphy(struct brcms_phy *pi, u8 cmd);
1071 s16 wlc_phy_tempsense_nphy(struct brcms_phy *pi);
1072
1073 u16 wlc_phy_classifier_nphy(struct brcms_phy *pi, u16 mask, u16 val);
1074
1075 void wlc_phy_rx_iq_est_nphy(struct brcms_phy *pi, struct phy_iq_est *est,
1076 u16 num_samps, u8 wait_time, u8 wait_for_crs);
1077
1078 void wlc_phy_rx_iq_coeffs_nphy(struct brcms_phy *pi, u8 write,
1079 struct nphy_iq_comp *comp);
1080 void wlc_phy_aci_and_noise_reduction_nphy(struct brcms_phy *pi);
1081
1082 void wlc_phy_rxcore_setstate_nphy(struct brcms_phy_pub *pih, u8 rxcore_bitmask);
1083 u8 wlc_phy_rxcore_getstate_nphy(struct brcms_phy_pub *pih);
1084
1085 void wlc_phy_txpwrctrl_enable_nphy(struct brcms_phy *pi, u8 ctrl_type);
1086 void wlc_phy_txpwr_fixpower_nphy(struct brcms_phy *pi);
1087 void wlc_phy_txpwr_apply_nphy(struct brcms_phy *pi);
1088 void wlc_phy_txpwr_papd_cal_nphy(struct brcms_phy *pi);
1089 u16 wlc_phy_txpwr_idx_get_nphy(struct brcms_phy *pi);
1090
1091 struct nphy_txgains wlc_phy_get_tx_gain_nphy(struct brcms_phy *pi);
1092 int wlc_phy_cal_txiqlo_nphy(struct brcms_phy *pi,
1093 struct nphy_txgains target_gain, bool full, bool m);
1094 int wlc_phy_cal_rxiq_nphy(struct brcms_phy *pi, struct nphy_txgains target_gain,
1095 u8 type, bool d);
1096 void wlc_phy_txpwr_index_nphy(struct brcms_phy *pi, u8 core_mask,
1097 s8 txpwrindex, bool res);
1098 void wlc_phy_rssisel_nphy(struct brcms_phy *pi, u8 core, u8 rssi_type);
1099 int wlc_phy_poll_rssi_nphy(struct brcms_phy *pi, u8 rssi_type,
1100 s32 *rssi_buf, u8 nsamps);
1101 void wlc_phy_rssi_cal_nphy(struct brcms_phy *pi);
1102 int wlc_phy_aci_scan_nphy(struct brcms_phy *pi);
1103 void wlc_phy_cal_txgainctrl_nphy(struct brcms_phy *pi, s32 dBm_targetpower,
1104 bool debug);
1105 int wlc_phy_tx_tone_nphy(struct brcms_phy *pi, u32 f_kHz, u16 max_val, u8 mode,
1106 u8, bool);
1107 void wlc_phy_stopplayback_nphy(struct brcms_phy *pi);
1108 void wlc_phy_est_tonepwr_nphy(struct brcms_phy *pi, s32 *qdBm_pwrbuf,
1109 u8 num_samps);
1110 void wlc_phy_radio205x_vcocal_nphy(struct brcms_phy *pi);
1111
1112 int wlc_phy_rssi_compute_nphy(struct brcms_phy *pi, struct d11rxhdr *rxh);
1113
1114 #define NPHY_TESTPATTERN_BPHY_EVM 0
1115 #define NPHY_TESTPATTERN_BPHY_RFCS 1
1116
1117 void wlc_phy_nphy_tkip_rifs_war(struct brcms_phy *pi, u8 rifs);
1118
1119 void wlc_phy_get_pwrdet_offsets(struct brcms_phy *pi, s8 *cckoffset,
1120 s8 *ofdmoffset);
1121 s8 wlc_phy_upd_rssi_offset(struct brcms_phy *pi, s8 rssi, u16 chanspec);
1122
1123 bool wlc_phy_n_txpower_ipa_ison(struct brcms_phy *pih);
1124 #endif
