brcm80211/brcmsmac/aiutils.h

0001 /*
0002  * Copyright (c) 2011 Broadcom Corporation
0003  *
0004  * Permission to use, copy, modify, and/or distribute this software for any
0005  * purpose with or without fee is hereby granted, provided that the above
0006  * copyright notice and this permission notice appear in all copies.
0007  *
0008  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0009  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0010  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
0011  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0012  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
0013  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
0014  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0015  */
0016
0017 #ifndef _BRCM_AIUTILS_H_
0018 #define _BRCM_AIUTILS_H_
0019
0020 #include <linux/bcma/bcma.h>
0021
0022 #include "types.h"
0023
0024 /*
0025  * SOC Interconnect Address Map.
0026  * All regions may not exist on all chips.
0027  */
0028 /* each core gets 4Kbytes for registers */
0029 #define SI_CORE_SIZE        0x1000
0030 /*
0031  * Max cores (this is arbitrary, for software
0032  * convenience and could be changed if we
0033  * make any larger chips
0034  */
0035 #define SI_MAXCORES     16
0036
0037 /* Client Mode sb2pcitranslation2 size in bytes */
0038 #define SI_PCI_DMA_SZ       0x40000000
0039
0040 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
0041 #define SI_PCIE_DMA_H32     0x80000000
0042
0043 /* chipcommon being the first core: */
0044 #define SI_CC_IDX       0
0045
0046 /* SOC Interconnect types (aka chip types) */
0047 #define SOCI_AI         1
0048
0049 /* A register that is common to all cores to
0050  * communicate w/PMU regarding clock control.
0051  */
0052 #define SI_CLK_CTL_ST       0x1e0   /* clock control and status */
0053
0054 /* clk_ctl_st register */
0055 #define CCS_FORCEALP        0x00000001  /* force ALP request */
0056 #define CCS_FORCEHT     0x00000002  /* force HT request */
0057 #define CCS_FORCEILP        0x00000004  /* force ILP request */
0058 #define CCS_ALPAREQ     0x00000008  /* ALP Avail Request */
0059 #define CCS_HTAREQ      0x00000010  /* HT Avail Request */
0060 #define CCS_FORCEHWREQOFF   0x00000020  /* Force HW Clock Request Off */
0061 #define CCS_ERSRC_REQ_MASK  0x00000700  /* external resource requests */
0062 #define CCS_ERSRC_REQ_SHIFT 8
0063 #define CCS_ALPAVAIL        0x00010000  /* ALP is available */
0064 #define CCS_HTAVAIL     0x00020000  /* HT is available */
0065 #define CCS_BP_ON_APL       0x00040000  /* RO: running on ALP clock */
0066 #define CCS_BP_ON_HT        0x00080000  /* RO: running on HT clock */
0067 #define CCS_ERSRC_STS_MASK  0x07000000  /* external resource status */
0068 #define CCS_ERSRC_STS_SHIFT 24
0069
0070 /* HT avail in chipc and pcmcia on 4328a0 */
0071 #define CCS0_HTAVAIL        0x00010000
0072 /* ALP avail in chipc and pcmcia on 4328a0 */
0073 #define CCS0_ALPAVAIL       0x00020000
0074
0075 /* Not really related to SOC Interconnect, but a couple of software
0076  * conventions for the use the flash space:
0077  */
0078
0079 /* Minumum amount of flash we support */
0080 #define FLASH_MIN       0x00020000  /* Minimum flash size */
0081
0082 #define CC_SROM_OTP     0x800   /* SROM/OTP address space */
0083
0084 /* gpiotimerval */
0085 #define GPIO_ONTIME_SHIFT   16
0086
0087 /* Fields in clkdiv */
0088 #define CLKD_OTP        0x000f0000
0089 #define CLKD_OTP_SHIFT      16
0090
0091 /* dynamic clock control defines */
0092 #define LPOMINFREQ      25000   /* low power oscillator min */
0093 #define LPOMAXFREQ      43000   /* low power oscillator max */
0094 #define XTALMINFREQ     19800000    /* 20 MHz - 1% */
0095 #define XTALMAXFREQ     20200000    /* 20 MHz + 1% */
0096 #define PCIMINFREQ      25000000    /* 25 MHz */
0097 #define PCIMAXFREQ      34000000    /* 33 MHz + fudge */
0098
0099 #define ILP_DIV_5MHZ        0   /* ILP = 5 MHz */
0100 #define ILP_DIV_1MHZ        4   /* ILP = 1 MHz */
0101
0102 /* clkctl xtal what flags */
0103 #define XTAL            0x1 /* primary crystal oscillator (2050) */
0104 #define PLL         0x2 /* main chip pll */
0105
0106 /* GPIO usage priorities */
0107 #define GPIO_DRV_PRIORITY   0   /* Driver */
0108 #define GPIO_APP_PRIORITY   1   /* Application */
0109 #define GPIO_HI_PRIORITY    2   /* Highest priority. Ignore GPIO
0110                      * reservation
0111                      */
0112
0113 /* GPIO pull up/down */
0114 #define GPIO_PULLUP     0
0115 #define GPIO_PULLDN     1
0116
0117 /* GPIO event regtype */
0118 #define GPIO_REGEVT     0   /* GPIO register event */
0119 #define GPIO_REGEVT_INTMSK  1   /* GPIO register event int mask */
0120 #define GPIO_REGEVT_INTPOL  2   /* GPIO register event int polarity */
0121
0122 /* device path */
0123 #define SI_DEVPATH_BUFSZ    16  /* min buffer size in bytes */
0124
0125 /* SI routine enumeration: to be used by update function with multiple hooks */
0126 #define SI_DOATTACH 1
0127 #define SI_PCIDOWN  2
0128 #define SI_PCIUP    3
0129
0130 /*
0131  * Data structure to export all chip specific common variables
0132  *   public (read-only) portion of aiutils handle returned by si_attach()
0133  */
0134 struct si_pub {
0135     int ccrev;      /* chip common core rev */
0136     u32 cccaps;     /* chip common capabilities */
0137     int pmurev;     /* pmu core rev */
0138     u32 pmucaps;        /* pmu capabilities */
0139     uint boardtype;     /* board type */
0140     uint boardvendor;   /* board vendor */
0141     uint chip;      /* chip number */
0142     uint chiprev;       /* chip revision */
0143     uint chippkg;       /* chip package option */
0144 };
0145
0146 struct pci_dev;
0147
0148 struct gpioh_item {
0149     void *arg;
0150     bool level;
0151     void (*handler) (u32 stat, void *arg);
0152     u32 event;
0153     struct gpioh_item *next;
0154 };
0155
0156 /* misc si info needed by some of the routines */
0157 struct si_info {
0158     struct si_pub pub;  /* back plane public state (must be first) */
0159     struct bcma_bus *icbus; /* handle to soc interconnect bus */
0160     struct pci_dev *pcibus; /* handle to pci bus */
0161
0162     u32 chipst;     /* chip status */
0163 };
0164
0165 /*
0166  * Many of the routines below take an 'sih' handle as their first arg.
0167  * Allocate this by calling si_attach().  Free it by calling si_detach().
0168  * At any one time, the sih is logically focused on one particular si core
0169  * (the "current core").
0170  * Use si_setcore() or si_setcoreidx() to change the association to another core
0171  */
0172
0173
0174 /* AMBA Interconnect exported externs */
0175 u32 ai_core_cflags(struct bcma_device *core, u32 mask, u32 val);
0176
0177 /* === exported functions === */
0178 struct si_pub *ai_attach(struct bcma_bus *pbus);
0179 void ai_detach(struct si_pub *sih);
0180 uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val);
0181 void ai_clkctl_init(struct si_pub *sih);
0182 u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih);
0183 bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode);
0184 bool ai_deviceremoved(struct si_pub *sih);
0185
0186 /* Enable Ex-PA for 4313 */
0187 void ai_epa_4313war(struct si_pub *sih);
0188
0189 static inline u32 ai_get_cccaps(struct si_pub *sih)
0190 {
0191     return sih->cccaps;
0192 }
0193
0194 static inline int ai_get_pmurev(struct si_pub *sih)
0195 {
0196     return sih->pmurev;
0197 }
0198
0199 static inline u32 ai_get_pmucaps(struct si_pub *sih)
0200 {
0201     return sih->pmucaps;
0202 }
0203
0204 static inline uint ai_get_boardtype(struct si_pub *sih)
0205 {
0206     return sih->boardtype;
0207 }
0208
0209 static inline uint ai_get_boardvendor(struct si_pub *sih)
0210 {
0211     return sih->boardvendor;
0212 }
0213
0214 static inline uint ai_get_chip_id(struct si_pub *sih)
0215 {
0216     return sih->chip;
0217 }
0218
0219 static inline uint ai_get_chiprev(struct si_pub *sih)
0220 {
0221     return sih->chiprev;
0222 }
0223
0224 static inline uint ai_get_chippkg(struct si_pub *sih)
0225 {
0226     return sih->chippkg;
0227 }
0228
0229 #endif              /* _BRCM_AIUTILS_H_ */