brcm80211/brcmfmac/sdio.h

0001 // SPDX-License-Identifier: ISC
0002 /*
0003  * Copyright (c) 2010 Broadcom Corporation
0004  */
0005
0006 #ifndef BRCMFMAC_SDIO_H
0007 #define BRCMFMAC_SDIO_H
0008
0009 #include <linux/skbuff.h>
0010 #include <linux/firmware.h>
0011 #include "firmware.h"
0012
0013 #define SDIOD_FBR_SIZE      0x100
0014
0015 /* io_en */
0016 #define SDIO_FUNC_ENABLE_1  0x02
0017 #define SDIO_FUNC_ENABLE_2  0x04
0018
0019 /* io_rdys */
0020 #define SDIO_FUNC_READY_1   0x02
0021 #define SDIO_FUNC_READY_2   0x04
0022
0023 /* intr_status */
0024 #define INTR_STATUS_FUNC1   0x2
0025 #define INTR_STATUS_FUNC2   0x4
0026
0027 /* mask of register map */
0028 #define REG_F0_REG_MASK     0x7FF
0029 #define REG_F1_MISC_MASK    0x1FFFF
0030
0031 /* function 0 vendor specific CCCR registers */
0032
0033 #define SDIO_CCCR_BRCM_CARDCAP          0xf0
0034 #define SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT    BIT(1)
0035 #define SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT    BIT(2)
0036 #define SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC    BIT(3)
0037
0038 /* Interrupt enable bits for each function */
0039 #define SDIO_CCCR_IEN_FUNC0         BIT(0)
0040 #define SDIO_CCCR_IEN_FUNC1         BIT(1)
0041 #define SDIO_CCCR_IEN_FUNC2         BIT(2)
0042
0043 #define SDIO_CCCR_BRCM_CARDCTRL         0xf1
0044 #define SDIO_CCCR_BRCM_CARDCTRL_WLANRESET   BIT(1)
0045
0046 #define SDIO_CCCR_BRCM_SEPINT           0xf2
0047 #define SDIO_CCCR_BRCM_SEPINT_MASK      BIT(0)
0048 #define SDIO_CCCR_BRCM_SEPINT_OE        BIT(1)
0049 #define SDIO_CCCR_BRCM_SEPINT_ACT_HI        BIT(2)
0050
0051 /* function 1 miscellaneous registers */
0052
0053 /* sprom command and status */
0054 #define SBSDIO_SPROM_CS         0x10000
0055 /* sprom info register */
0056 #define SBSDIO_SPROM_INFO       0x10001
0057 /* sprom indirect access data byte 0 */
0058 #define SBSDIO_SPROM_DATA_LOW       0x10002
0059 /* sprom indirect access data byte 1 */
0060 #define SBSDIO_SPROM_DATA_HIGH      0x10003
0061 /* sprom indirect access addr byte 0 */
0062 #define SBSDIO_SPROM_ADDR_LOW       0x10004
0063 /* gpio select */
0064 #define SBSDIO_GPIO_SELECT      0x10005
0065 /* gpio output */
0066 #define SBSDIO_GPIO_OUT         0x10006
0067 /* gpio enable */
0068 #define SBSDIO_GPIO_EN          0x10007
0069 /* rev < 7, watermark for sdio device TX path */
0070 #define SBSDIO_WATERMARK        0x10008
0071 /* control busy signal generation */
0072 #define SBSDIO_DEVICE_CTL       0x10009
0073
0074 /* SB Address Window Low (b15) */
0075 #define SBSDIO_FUNC1_SBADDRLOW      0x1000A
0076 /* SB Address Window Mid (b23:b16) */
0077 #define SBSDIO_FUNC1_SBADDRMID      0x1000B
0078 /* SB Address Window High (b31:b24)    */
0079 #define SBSDIO_FUNC1_SBADDRHIGH     0x1000C
0080 /* Frame Control (frame term/abort) */
0081 #define SBSDIO_FUNC1_FRAMECTRL      0x1000D
0082 /* ChipClockCSR (ALP/HT ctl/status) */
0083 #define SBSDIO_FUNC1_CHIPCLKCSR     0x1000E
0084 /* SdioPullUp (on cmd, d0-d2) */
0085 #define SBSDIO_FUNC1_SDIOPULLUP     0x1000F
0086 /* Write Frame Byte Count Low */
0087 #define SBSDIO_FUNC1_WFRAMEBCLO     0x10019
0088 /* Write Frame Byte Count High */
0089 #define SBSDIO_FUNC1_WFRAMEBCHI     0x1001A
0090 /* Read Frame Byte Count Low */
0091 #define SBSDIO_FUNC1_RFRAMEBCLO     0x1001B
0092 /* Read Frame Byte Count High */
0093 #define SBSDIO_FUNC1_RFRAMEBCHI     0x1001C
0094 /* MesBusyCtl (rev 11) */
0095 #define SBSDIO_FUNC1_MESBUSYCTRL    0x1001D
0096 /* Watermark for sdio device RX path */
0097 #define SBSDIO_MESBUSY_RXFIFO_WM_MASK   0x7F
0098 #define SBSDIO_MESBUSY_RXFIFO_WM_SHIFT  0
0099 /* Enable busy capability for MES access */
0100 #define SBSDIO_MESBUSYCTRL_ENAB     0x80
0101 #define SBSDIO_MESBUSYCTRL_ENAB_SHIFT   7
0102
0103 /* Sdio Core Rev 12 */
0104 #define SBSDIO_FUNC1_WAKEUPCTRL     0x1001E
0105 #define SBSDIO_FUNC1_WCTRL_ALPWAIT_MASK     0x1
0106 #define SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT    0
0107 #define SBSDIO_FUNC1_WCTRL_HTWAIT_MASK      0x2
0108 #define SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT     1
0109 #define SBSDIO_FUNC1_SLEEPCSR       0x1001F
0110 #define SBSDIO_FUNC1_SLEEPCSR_KSO_MASK      0x1
0111 #define SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT     0
0112 #define SBSDIO_FUNC1_SLEEPCSR_KSO_EN        1
0113 #define SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK    0x2
0114 #define SBSDIO_FUNC1_SLEEPCSR_DEVON_SHIFT   1
0115
0116 #define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */
0117 #define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001F /* f1 misc register end */
0118
0119 /* function 1 OCP space */
0120
0121 /* sb offset addr is <= 15 bits, 32k */
0122 #define SBSDIO_SB_OFT_ADDR_MASK     0x07FFF
0123 #define SBSDIO_SB_OFT_ADDR_LIMIT    0x08000
0124 /* with b15, maps to 32-bit SB access */
0125 #define SBSDIO_SB_ACCESS_2_4B_FLAG  0x08000
0126
0127 /* Address bits from SBADDR regs */
0128 #define SBSDIO_SBWINDOW_MASK        0xffff8000
0129
0130 #define SDIOH_READ              0   /* Read request */
0131 #define SDIOH_WRITE             1   /* Write request */
0132
0133 #define SDIOH_DATA_FIX          0   /* Fixed addressing */
0134 #define SDIOH_DATA_INC          1   /* Incremental addressing */
0135
0136 /* internal return code */
0137 #define SUCCESS 0
0138 #define ERROR   1
0139
0140 /* Packet alignment for most efficient SDIO (can change based on platform) */
0141 #define BRCMF_SDALIGN   (1 << 6)
0142
0143 /* watchdog polling interval */
0144 #define BRCMF_WD_POLL   msecs_to_jiffies(10)
0145
0146 /**
0147  * enum brcmf_sdiod_state - the state of the bus.
0148  *
0149  * @BRCMF_SDIOD_DOWN: Device can be accessed, no DPC.
0150  * @BRCMF_SDIOD_DATA: Ready for data transfers, DPC enabled.
0151  * @BRCMF_SDIOD_NOMEDIUM: No medium access to dongle possible.
0152  */
0153 enum brcmf_sdiod_state {
0154     BRCMF_SDIOD_DOWN,
0155     BRCMF_SDIOD_DATA,
0156     BRCMF_SDIOD_NOMEDIUM
0157 };
0158
0159 struct brcmf_sdreg {
0160     int func;
0161     int offset;
0162     int value;
0163 };
0164
0165 struct brcmf_sdio;
0166 struct brcmf_sdiod_freezer;
0167
0168 struct brcmf_sdio_dev {
0169     struct sdio_func *func1;
0170     struct sdio_func *func2;
0171     u32 sbwad;          /* Save backplane window address */
0172     struct brcmf_core *cc_core; /* chipcommon core info struct */
0173     struct brcmf_sdio *bus;
0174     struct device *dev;
0175     struct brcmf_bus *bus_if;
0176     struct brcmf_mp_device *settings;
0177     bool oob_irq_requested;
0178     bool sd_irq_requested;
0179     bool irq_en;            /* irq enable flags */
0180     spinlock_t irq_en_lock;
0181     bool sg_support;
0182     uint max_request_size;
0183     ushort max_segment_count;
0184     uint max_segment_size;
0185     uint txglomsz;
0186     struct sg_table sgtable;
0187     char fw_name[BRCMF_FW_NAME_LEN];
0188     char nvram_name[BRCMF_FW_NAME_LEN];
0189     bool wowl_enabled;
0190     enum brcmf_sdiod_state state;
0191     struct brcmf_sdiod_freezer *freezer;
0192 };
0193
0194 /* sdio core registers */
0195 struct sdpcmd_regs {
0196     u32 corecontrol;        /* 0x00, rev8 */
0197     u32 corestatus;         /* rev8 */
0198     u32 PAD[1];
0199     u32 biststatus;         /* rev8 */
0200
0201     /* PCMCIA access */
0202     u16 pcmciamesportaladdr;    /* 0x010, rev8 */
0203     u16 PAD[1];
0204     u16 pcmciamesportalmask;    /* rev8 */
0205     u16 PAD[1];
0206     u16 pcmciawrframebc;        /* rev8 */
0207     u16 PAD[1];
0208     u16 pcmciaunderflowtimer;   /* rev8 */
0209     u16 PAD[1];
0210
0211     /* interrupt */
0212     u32 intstatus;          /* 0x020, rev8 */
0213     u32 hostintmask;        /* rev8 */
0214     u32 intmask;            /* rev8 */
0215     u32 sbintstatus;        /* rev8 */
0216     u32 sbintmask;          /* rev8 */
0217     u32 funcintmask;        /* rev4 */
0218     u32 PAD[2];
0219     u32 tosbmailbox;        /* 0x040, rev8 */
0220     u32 tohostmailbox;      /* rev8 */
0221     u32 tosbmailboxdata;        /* rev8 */
0222     u32 tohostmailboxdata;      /* rev8 */
0223
0224     /* synchronized access to registers in SDIO clock domain */
0225     u32 sdioaccess;         /* 0x050, rev8 */
0226     u32 PAD[3];
0227
0228     /* PCMCIA frame control */
0229     u8 pcmciaframectrl;     /* 0x060, rev8 */
0230     u8 PAD[3];
0231     u8 pcmciawatermark;     /* rev8 */
0232     u8 PAD[155];
0233
0234     /* interrupt batching control */
0235     u32 intrcvlazy;         /* 0x100, rev8 */
0236     u32 PAD[3];
0237
0238     /* counters */
0239     u32 cmd52rd;            /* 0x110, rev8 */
0240     u32 cmd52wr;            /* rev8 */
0241     u32 cmd53rd;            /* rev8 */
0242     u32 cmd53wr;            /* rev8 */
0243     u32 abort;          /* rev8 */
0244     u32 datacrcerror;       /* rev8 */
0245     u32 rdoutofsync;        /* rev8 */
0246     u32 wroutofsync;        /* rev8 */
0247     u32 writebusy;          /* rev8 */
0248     u32 readwait;           /* rev8 */
0249     u32 readterm;           /* rev8 */
0250     u32 writeterm;          /* rev8 */
0251     u32 PAD[40];
0252     u32 clockctlstatus;     /* rev8 */
0253     u32 PAD[7];
0254
0255     u32 PAD[128];           /* DMA engines */
0256
0257     /* SDIO/PCMCIA CIS region */
0258     char cis[512];          /* 0x400-0x5ff, rev6 */
0259
0260     /* PCMCIA function control registers */
0261     char pcmciafcr[256];        /* 0x600-6ff, rev6 */
0262     u16 PAD[55];
0263
0264     /* PCMCIA backplane access */
0265     u16 backplanecsr;       /* 0x76E, rev6 */
0266     u16 backplaneaddr0;     /* rev6 */
0267     u16 backplaneaddr1;     /* rev6 */
0268     u16 backplaneaddr2;     /* rev6 */
0269     u16 backplaneaddr3;     /* rev6 */
0270     u16 backplanedata0;     /* rev6 */
0271     u16 backplanedata1;     /* rev6 */
0272     u16 backplanedata2;     /* rev6 */
0273     u16 backplanedata3;     /* rev6 */
0274     u16 PAD[31];
0275
0276     /* sprom "size" & "blank" info */
0277     u16 spromstatus;        /* 0x7BE, rev2 */
0278     u32 PAD[464];
0279
0280     u16 PAD[0x80];
0281 };
0282
0283 /* Register/deregister interrupt handler. */
0284 int brcmf_sdiod_intr_register(struct brcmf_sdio_dev *sdiodev);
0285 void brcmf_sdiod_intr_unregister(struct brcmf_sdio_dev *sdiodev);
0286
0287 /* SDIO device register access interface */
0288 /* Accessors for SDIO Function 0 */
0289 #define brcmf_sdiod_func0_rb(sdiodev, addr, r) \
0290     sdio_f0_readb((sdiodev)->func1, (addr), (r))
0291
0292 #define brcmf_sdiod_func0_wb(sdiodev, addr, v, ret) \
0293     sdio_f0_writeb((sdiodev)->func1, (v), (addr), (ret))
0294
0295 /* Accessors for SDIO Function 1 */
0296 #define brcmf_sdiod_readb(sdiodev, addr, r) \
0297     sdio_readb((sdiodev)->func1, (addr), (r))
0298
0299 #define brcmf_sdiod_writeb(sdiodev, addr, v, ret) \
0300     sdio_writeb((sdiodev)->func1, (v), (addr), (ret))
0301
0302 u32 brcmf_sdiod_readl(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret);
0303 void brcmf_sdiod_writel(struct brcmf_sdio_dev *sdiodev, u32 addr, u32 data,
0304             int *ret);
0305
0306 /* Buffer transfer to/from device (client) core via cmd53.
0307  *   fn:       function number
0308  *   flags:    backplane width, address increment, sync/async
0309  *   buf:      pointer to memory data buffer
0310  *   nbytes:   number of bytes to transfer to/from buf
0311  *   pkt:      pointer to packet associated with buf (if any)
0312  *   complete: callback function for command completion (async only)
0313  *   handle:   handle for completion callback (first arg in callback)
0314  * Returns 0 or error code.
0315  * NOTE: Async operation is not currently supported.
0316  */
0317 int brcmf_sdiod_send_pkt(struct brcmf_sdio_dev *sdiodev,
0318              struct sk_buff_head *pktq);
0319 int brcmf_sdiod_send_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes);
0320
0321 int brcmf_sdiod_recv_pkt(struct brcmf_sdio_dev *sdiodev, struct sk_buff *pkt);
0322 int brcmf_sdiod_recv_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes);
0323 int brcmf_sdiod_recv_chain(struct brcmf_sdio_dev *sdiodev,
0324                struct sk_buff_head *pktq, uint totlen);
0325
0326 /* Flags bits */
0327
0328 /* Four-byte target (backplane) width (vs. two-byte) */
0329 #define SDIO_REQ_4BYTE  0x1
0330 /* Fixed address (FIFO) (vs. incrementing address) */
0331 #define SDIO_REQ_FIXED  0x2
0332
0333 /* Read/write to memory block (F1, no FIFO) via CMD53 (sync only).
0334  *   rw:       read or write (0/1)
0335  *   addr:     direct SDIO address
0336  *   buf:      pointer to memory data buffer
0337  *   nbytes:   number of bytes to transfer to/from buf
0338  * Returns 0 or error code.
0339  */
0340 int brcmf_sdiod_ramrw(struct brcmf_sdio_dev *sdiodev, bool write, u32 address,
0341               u8 *data, uint size);
0342
0343 /* Issue an abort to the specified function */
0344 int brcmf_sdiod_abort(struct brcmf_sdio_dev *sdiodev, struct sdio_func *func);
0345
0346 void brcmf_sdiod_sgtable_alloc(struct brcmf_sdio_dev *sdiodev);
0347 void brcmf_sdiod_change_state(struct brcmf_sdio_dev *sdiodev,
0348                   enum brcmf_sdiod_state state);
0349 bool brcmf_sdiod_freezing(struct brcmf_sdio_dev *sdiodev);
0350 void brcmf_sdiod_try_freeze(struct brcmf_sdio_dev *sdiodev);
0351 void brcmf_sdiod_freezer_count(struct brcmf_sdio_dev *sdiodev);
0352 void brcmf_sdiod_freezer_uncount(struct brcmf_sdio_dev *sdiodev);
0353
0354 int brcmf_sdiod_probe(struct brcmf_sdio_dev *sdiodev);
0355 int brcmf_sdiod_remove(struct brcmf_sdio_dev *sdiodev);
0356
0357 struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev);
0358 void brcmf_sdio_remove(struct brcmf_sdio *bus);
0359 void brcmf_sdio_isr(struct brcmf_sdio *bus, bool in_isr);
0360
0361 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active);
0362 void brcmf_sdio_wowl_config(struct device *dev, bool enabled);
0363 int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep);
0364 void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus);
0365
0366 #endif /* BRCMFMAC_SDIO_H */