brcm80211/brcmfmac/chip.h

0001 // SPDX-License-Identifier: ISC
0002 /*
0003  * Copyright (c) 2014 Broadcom Corporation
0004  */
0005 #ifndef BRCMF_CHIP_H
0006 #define BRCMF_CHIP_H
0007
0008 #include <linux/types.h>
0009
0010 #define CORE_CC_REG(base, field) \
0011         (base + offsetof(struct chipcregs, field))
0012
0013 /**
0014  * struct brcmf_chip - chip level information.
0015  *
0016  * @chip: chip identifier.
0017  * @chiprev: chip revision.
0018  * @enum_base: base address of core enumeration space.
0019  * @cc_caps: chipcommon core capabilities.
0020  * @cc_caps_ext: chipcommon core extended capabilities.
0021  * @pmucaps: PMU capabilities.
0022  * @pmurev: PMU revision.
0023  * @rambase: RAM base address (only applicable for ARM CR4 chips).
0024  * @ramsize: amount of RAM on chip including retention.
0025  * @srsize: amount of retention RAM on chip.
0026  * @name: string representation of the chip identifier.
0027  */
0028 struct brcmf_chip {
0029     u32 chip;
0030     u32 chiprev;
0031     u32 enum_base;
0032     u32 cc_caps;
0033     u32 cc_caps_ext;
0034     u32 pmucaps;
0035     u32 pmurev;
0036     u32 rambase;
0037     u32 ramsize;
0038     u32 srsize;
0039     char name[12];
0040 };
0041
0042 /**
0043  * struct brcmf_core - core related information.
0044  *
0045  * @id: core identifier.
0046  * @rev: core revision.
0047  * @base: base address of core register space.
0048  */
0049 struct brcmf_core {
0050     u16 id;
0051     u16 rev;
0052     u32 base;
0053 };
0054
0055 /**
0056  * struct brcmf_buscore_ops - buscore specific callbacks.
0057  *
0058  * @read32: read 32-bit value over bus.
0059  * @write32: write 32-bit value over bus.
0060  * @prepare: prepare bus for core configuration.
0061  * @setup: bus-specific core setup.
0062  * @active: chip becomes active.
0063  *  The callback should use the provided @rstvec when non-zero.
0064  */
0065 struct brcmf_buscore_ops {
0066     u32 (*read32)(void *ctx, u32 addr);
0067     void (*write32)(void *ctx, u32 addr, u32 value);
0068     int (*prepare)(void *ctx);
0069     int (*reset)(void *ctx, struct brcmf_chip *chip);
0070     int (*setup)(void *ctx, struct brcmf_chip *chip);
0071     void (*activate)(void *ctx, struct brcmf_chip *chip, u32 rstvec);
0072 };
0073
0074 int brcmf_chip_get_raminfo(struct brcmf_chip *pub);
0075 struct brcmf_chip *brcmf_chip_attach(void *ctx, u16 devid,
0076                      const struct brcmf_buscore_ops *ops);
0077 void brcmf_chip_detach(struct brcmf_chip *chip);
0078 struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *chip, u16 coreid);
0079 struct brcmf_core *brcmf_chip_get_d11core(struct brcmf_chip *pub, u8 unit);
0080 struct brcmf_core *brcmf_chip_get_chipcommon(struct brcmf_chip *chip);
0081 struct brcmf_core *brcmf_chip_get_pmu(struct brcmf_chip *pub);
0082 bool brcmf_chip_iscoreup(struct brcmf_core *core);
0083 void brcmf_chip_coredisable(struct brcmf_core *core, u32 prereset, u32 reset);
0084 void brcmf_chip_resetcore(struct brcmf_core *core, u32 prereset, u32 reset,
0085               u32 postreset);
0086 void brcmf_chip_set_passive(struct brcmf_chip *ci);
0087 bool brcmf_chip_set_active(struct brcmf_chip *ci, u32 rstvec);
0088 bool brcmf_chip_sr_capable(struct brcmf_chip *pub);
0089 char *brcmf_chip_name(u32 chipid, u32 chiprev, char *buf, uint len);
0090 u32 brcmf_chip_enum_base(u16 devid);
0091
0092 #endif /* BRCMF_AXIDMP_H */