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0001 // SPDX-License-Identifier: ISC
0002 /*
0003  * Copyright (c) 2014 Broadcom Corporation
0004  */
0005 #include <linux/kernel.h>
0006 #include <linux/delay.h>
0007 #include <linux/list.h>
0008 #include <linux/ssb/ssb_regs.h>
0009 #include <linux/bcma/bcma.h>
0010 #include <linux/bcma/bcma_regs.h>
0011 
0012 #include <defs.h>
0013 #include <soc.h>
0014 #include <brcm_hw_ids.h>
0015 #include <brcmu_utils.h>
0016 #include <chipcommon.h>
0017 #include "debug.h"
0018 #include "chip.h"
0019 
0020 /* SOC Interconnect types (aka chip types) */
0021 #define SOCI_SB     0
0022 #define SOCI_AI     1
0023 
0024 /* PL-368 DMP definitions */
0025 #define DMP_DESC_TYPE_MSK   0x0000000F
0026 #define  DMP_DESC_EMPTY     0x00000000
0027 #define  DMP_DESC_VALID     0x00000001
0028 #define  DMP_DESC_COMPONENT 0x00000001
0029 #define  DMP_DESC_MASTER_PORT   0x00000003
0030 #define  DMP_DESC_ADDRESS   0x00000005
0031 #define  DMP_DESC_ADDRSIZE_GT32 0x00000008
0032 #define  DMP_DESC_EOT       0x0000000F
0033 
0034 #define DMP_COMP_DESIGNER   0xFFF00000
0035 #define DMP_COMP_DESIGNER_S 20
0036 #define DMP_COMP_PARTNUM    0x000FFF00
0037 #define DMP_COMP_PARTNUM_S  8
0038 #define DMP_COMP_CLASS      0x000000F0
0039 #define DMP_COMP_CLASS_S    4
0040 #define DMP_COMP_REVISION   0xFF000000
0041 #define DMP_COMP_REVISION_S 24
0042 #define DMP_COMP_NUM_SWRAP  0x00F80000
0043 #define DMP_COMP_NUM_SWRAP_S    19
0044 #define DMP_COMP_NUM_MWRAP  0x0007C000
0045 #define DMP_COMP_NUM_MWRAP_S    14
0046 #define DMP_COMP_NUM_SPORT  0x00003E00
0047 #define DMP_COMP_NUM_SPORT_S    9
0048 #define DMP_COMP_NUM_MPORT  0x000001F0
0049 #define DMP_COMP_NUM_MPORT_S    4
0050 
0051 #define DMP_MASTER_PORT_UID 0x0000FF00
0052 #define DMP_MASTER_PORT_UID_S   8
0053 #define DMP_MASTER_PORT_NUM 0x000000F0
0054 #define DMP_MASTER_PORT_NUM_S   4
0055 
0056 #define DMP_SLAVE_ADDR_BASE 0xFFFFF000
0057 #define DMP_SLAVE_ADDR_BASE_S   12
0058 #define DMP_SLAVE_PORT_NUM  0x00000F00
0059 #define DMP_SLAVE_PORT_NUM_S    8
0060 #define DMP_SLAVE_TYPE      0x000000C0
0061 #define DMP_SLAVE_TYPE_S    6
0062 #define  DMP_SLAVE_TYPE_SLAVE   0
0063 #define  DMP_SLAVE_TYPE_BRIDGE  1
0064 #define  DMP_SLAVE_TYPE_SWRAP   2
0065 #define  DMP_SLAVE_TYPE_MWRAP   3
0066 #define DMP_SLAVE_SIZE_TYPE 0x00000030
0067 #define DMP_SLAVE_SIZE_TYPE_S   4
0068 #define  DMP_SLAVE_SIZE_4K  0
0069 #define  DMP_SLAVE_SIZE_8K  1
0070 #define  DMP_SLAVE_SIZE_16K 2
0071 #define  DMP_SLAVE_SIZE_DESC    3
0072 
0073 /* EROM CompIdentB */
0074 #define CIB_REV_MASK        0xff000000
0075 #define CIB_REV_SHIFT       24
0076 
0077 /* ARM CR4 core specific control flag bits */
0078 #define ARMCR4_BCMA_IOCTL_CPUHALT   0x0020
0079 
0080 /* D11 core specific control flag bits */
0081 #define D11_BCMA_IOCTL_PHYCLOCKEN   0x0004
0082 #define D11_BCMA_IOCTL_PHYRESET     0x0008
0083 
0084 /* chip core base & ramsize */
0085 /* bcm4329 */
0086 /* SDIO device core, ID 0x829 */
0087 #define BCM4329_CORE_BUS_BASE       0x18011000
0088 /* internal memory core, ID 0x80e */
0089 #define BCM4329_CORE_SOCRAM_BASE    0x18003000
0090 /* ARM Cortex M3 core, ID 0x82a */
0091 #define BCM4329_CORE_ARM_BASE       0x18002000
0092 
0093 /* Max possibly supported memory size (limited by IO mapped memory) */
0094 #define BRCMF_CHIP_MAX_MEMSIZE      (4 * 1024 * 1024)
0095 
0096 #define CORE_SB(base, field) \
0097         (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
0098 #define SBCOREREV(sbidh) \
0099     ((((sbidh) & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT) | \
0100       ((sbidh) & SSB_IDHIGH_RCLO))
0101 
0102 struct sbconfig {
0103     u32 PAD[2];
0104     u32 sbipsflag;  /* initiator port ocp slave flag */
0105     u32 PAD[3];
0106     u32 sbtpsflag;  /* target port ocp slave flag */
0107     u32 PAD[11];
0108     u32 sbtmerrloga;    /* (sonics >= 2.3) */
0109     u32 PAD;
0110     u32 sbtmerrlog; /* (sonics >= 2.3) */
0111     u32 PAD[3];
0112     u32 sbadmatch3; /* address match3 */
0113     u32 PAD;
0114     u32 sbadmatch2; /* address match2 */
0115     u32 PAD;
0116     u32 sbadmatch1; /* address match1 */
0117     u32 PAD[7];
0118     u32 sbimstate;  /* initiator agent state */
0119     u32 sbintvec;   /* interrupt mask */
0120     u32 sbtmstatelow;   /* target state */
0121     u32 sbtmstatehigh;  /* target state */
0122     u32 sbbwa0;     /* bandwidth allocation table0 */
0123     u32 PAD;
0124     u32 sbimconfiglow;  /* initiator configuration */
0125     u32 sbimconfighigh; /* initiator configuration */
0126     u32 sbadmatch0; /* address match0 */
0127     u32 PAD;
0128     u32 sbtmconfiglow;  /* target configuration */
0129     u32 sbtmconfighigh; /* target configuration */
0130     u32 sbbconfig;  /* broadcast configuration */
0131     u32 PAD;
0132     u32 sbbstate;   /* broadcast state */
0133     u32 PAD[3];
0134     u32 sbactcnfg;  /* activate configuration */
0135     u32 PAD[3];
0136     u32 sbflagst;   /* current sbflags */
0137     u32 PAD[3];
0138     u32 sbidlow;        /* identification */
0139     u32 sbidhigh;   /* identification */
0140 };
0141 
0142 #define INVALID_RAMBASE         ((u32)(~0))
0143 
0144 /* bankidx and bankinfo reg defines corerev >= 8 */
0145 #define SOCRAM_BANKINFO_RETNTRAM_MASK   0x00010000
0146 #define SOCRAM_BANKINFO_SZMASK      0x0000007f
0147 #define SOCRAM_BANKIDX_ROM_MASK     0x00000100
0148 
0149 #define SOCRAM_BANKIDX_MEMTYPE_SHIFT    8
0150 /* socram bankinfo memtype */
0151 #define SOCRAM_MEMTYPE_RAM      0
0152 #define SOCRAM_MEMTYPE_R0M      1
0153 #define SOCRAM_MEMTYPE_DEVRAM       2
0154 
0155 #define SOCRAM_BANKINFO_SZBASE      8192
0156 #define SRCI_LSS_MASK       0x00f00000
0157 #define SRCI_LSS_SHIFT      20
0158 #define SRCI_SRNB_MASK      0xf0
0159 #define SRCI_SRNB_MASK_EXT  0x100
0160 #define SRCI_SRNB_SHIFT     4
0161 #define SRCI_SRBSZ_MASK     0xf
0162 #define SRCI_SRBSZ_SHIFT    0
0163 #define SR_BSZ_BASE     14
0164 
0165 struct sbsocramregs {
0166     u32 coreinfo;
0167     u32 bwalloc;
0168     u32 extracoreinfo;
0169     u32 biststat;
0170     u32 bankidx;
0171     u32 standbyctrl;
0172 
0173     u32 errlogstatus;   /* rev 6 */
0174     u32 errlogaddr; /* rev 6 */
0175     /* used for patching rev 3 & 5 */
0176     u32 cambankidx;
0177     u32 cambankstandbyctrl;
0178     u32 cambankpatchctrl;
0179     u32 cambankpatchtblbaseaddr;
0180     u32 cambankcmdreg;
0181     u32 cambankdatareg;
0182     u32 cambankmaskreg;
0183     u32 PAD[1];
0184     u32 bankinfo;   /* corev 8 */
0185     u32 bankpda;
0186     u32 PAD[14];
0187     u32 extmemconfig;
0188     u32 extmemparitycsr;
0189     u32 extmemparityerrdata;
0190     u32 extmemparityerrcnt;
0191     u32 extmemwrctrlandsize;
0192     u32 PAD[84];
0193     u32 workaround;
0194     u32 pwrctl;     /* corerev >= 2 */
0195     u32 PAD[133];
0196     u32 sr_control;     /* corerev >= 15 */
0197     u32 sr_status;      /* corerev >= 15 */
0198     u32 sr_address;     /* corerev >= 15 */
0199     u32 sr_data;        /* corerev >= 15 */
0200 };
0201 
0202 #define SOCRAMREGOFFS(_f)   offsetof(struct sbsocramregs, _f)
0203 #define SYSMEMREGOFFS(_f)   offsetof(struct sbsocramregs, _f)
0204 
0205 #define ARMCR4_CAP      (0x04)
0206 #define ARMCR4_BANKIDX      (0x40)
0207 #define ARMCR4_BANKINFO     (0x44)
0208 #define ARMCR4_BANKPDA      (0x4C)
0209 
0210 #define ARMCR4_TCBBNB_MASK  0xf0
0211 #define ARMCR4_TCBBNB_SHIFT 4
0212 #define ARMCR4_TCBANB_MASK  0xf
0213 #define ARMCR4_TCBANB_SHIFT 0
0214 
0215 #define ARMCR4_BSZ_MASK     0x3f
0216 #define ARMCR4_BSZ_MULT     8192
0217 
0218 struct brcmf_core_priv {
0219     struct brcmf_core pub;
0220     u32 wrapbase;
0221     struct list_head list;
0222     struct brcmf_chip_priv *chip;
0223 };
0224 
0225 struct brcmf_chip_priv {
0226     struct brcmf_chip pub;
0227     const struct brcmf_buscore_ops *ops;
0228     void *ctx;
0229     /* assured first core is chipcommon, second core is buscore */
0230     struct list_head cores;
0231     u16 num_cores;
0232 
0233     bool (*iscoreup)(struct brcmf_core_priv *core);
0234     void (*coredisable)(struct brcmf_core_priv *core, u32 prereset,
0235                 u32 reset);
0236     void (*resetcore)(struct brcmf_core_priv *core, u32 prereset, u32 reset,
0237               u32 postreset);
0238 };
0239 
0240 static void brcmf_chip_sb_corerev(struct brcmf_chip_priv *ci,
0241                   struct brcmf_core *core)
0242 {
0243     u32 regdata;
0244 
0245     regdata = ci->ops->read32(ci->ctx, CORE_SB(core->base, sbidhigh));
0246     core->rev = SBCOREREV(regdata);
0247 }
0248 
0249 static bool brcmf_chip_sb_iscoreup(struct brcmf_core_priv *core)
0250 {
0251     struct brcmf_chip_priv *ci;
0252     u32 regdata;
0253     u32 address;
0254 
0255     ci = core->chip;
0256     address = CORE_SB(core->pub.base, sbtmstatelow);
0257     regdata = ci->ops->read32(ci->ctx, address);
0258     regdata &= (SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT |
0259             SSB_IMSTATE_REJECT | SSB_TMSLOW_CLOCK);
0260     return SSB_TMSLOW_CLOCK == regdata;
0261 }
0262 
0263 static bool brcmf_chip_ai_iscoreup(struct brcmf_core_priv *core)
0264 {
0265     struct brcmf_chip_priv *ci;
0266     u32 regdata;
0267     bool ret;
0268 
0269     ci = core->chip;
0270     regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
0271     ret = (regdata & (BCMA_IOCTL_FGC | BCMA_IOCTL_CLK)) == BCMA_IOCTL_CLK;
0272 
0273     regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
0274     ret = ret && ((regdata & BCMA_RESET_CTL_RESET) == 0);
0275 
0276     return ret;
0277 }
0278 
0279 static void brcmf_chip_sb_coredisable(struct brcmf_core_priv *core,
0280                       u32 prereset, u32 reset)
0281 {
0282     struct brcmf_chip_priv *ci;
0283     u32 val, base;
0284 
0285     ci = core->chip;
0286     base = core->pub.base;
0287     val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
0288     if (val & SSB_TMSLOW_RESET)
0289         return;
0290 
0291     val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
0292     if ((val & SSB_TMSLOW_CLOCK) != 0) {
0293         /*
0294          * set target reject and spin until busy is clear
0295          * (preserve core-specific bits)
0296          */
0297         val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
0298         ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
0299                      val | SSB_TMSLOW_REJECT);
0300 
0301         val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
0302         udelay(1);
0303         SPINWAIT((ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh))
0304               & SSB_TMSHIGH_BUSY), 100000);
0305 
0306         val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
0307         if (val & SSB_TMSHIGH_BUSY)
0308             brcmf_err("core state still busy\n");
0309 
0310         val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
0311         if (val & SSB_IDLOW_INITIATOR) {
0312             val = ci->ops->read32(ci->ctx,
0313                           CORE_SB(base, sbimstate));
0314             val |= SSB_IMSTATE_REJECT;
0315             ci->ops->write32(ci->ctx,
0316                      CORE_SB(base, sbimstate), val);
0317             val = ci->ops->read32(ci->ctx,
0318                           CORE_SB(base, sbimstate));
0319             udelay(1);
0320             SPINWAIT((ci->ops->read32(ci->ctx,
0321                           CORE_SB(base, sbimstate)) &
0322                   SSB_IMSTATE_BUSY), 100000);
0323         }
0324 
0325         /* set reset and reject while enabling the clocks */
0326         val = SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
0327               SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET;
0328         ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), val);
0329         val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
0330         udelay(10);
0331 
0332         /* clear the initiator reject bit */
0333         val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
0334         if (val & SSB_IDLOW_INITIATOR) {
0335             val = ci->ops->read32(ci->ctx,
0336                           CORE_SB(base, sbimstate));
0337             val &= ~SSB_IMSTATE_REJECT;
0338             ci->ops->write32(ci->ctx,
0339                      CORE_SB(base, sbimstate), val);
0340         }
0341     }
0342 
0343     /* leave reset and reject asserted */
0344     ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
0345              (SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET));
0346     udelay(1);
0347 }
0348 
0349 static void brcmf_chip_ai_coredisable(struct brcmf_core_priv *core,
0350                       u32 prereset, u32 reset)
0351 {
0352     struct brcmf_chip_priv *ci;
0353     u32 regdata;
0354 
0355     ci = core->chip;
0356 
0357     /* if core is already in reset, skip reset */
0358     regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
0359     if ((regdata & BCMA_RESET_CTL_RESET) != 0)
0360         goto in_reset_configure;
0361 
0362     /* configure reset */
0363     ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
0364              prereset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
0365     ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
0366 
0367     /* put in reset */
0368     ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL,
0369              BCMA_RESET_CTL_RESET);
0370     usleep_range(10, 20);
0371 
0372     /* wait till reset is 1 */
0373     SPINWAIT(ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) !=
0374          BCMA_RESET_CTL_RESET, 300);
0375 
0376 in_reset_configure:
0377     /* in-reset configure */
0378     ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
0379              reset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
0380     ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
0381 }
0382 
0383 static void brcmf_chip_sb_resetcore(struct brcmf_core_priv *core, u32 prereset,
0384                     u32 reset, u32 postreset)
0385 {
0386     struct brcmf_chip_priv *ci;
0387     u32 regdata;
0388     u32 base;
0389 
0390     ci = core->chip;
0391     base = core->pub.base;
0392     /*
0393      * Must do the disable sequence first to work for
0394      * arbitrary current core state.
0395      */
0396     brcmf_chip_sb_coredisable(core, 0, 0);
0397 
0398     /*
0399      * Now do the initialization sequence.
0400      * set reset while enabling the clock and
0401      * forcing them on throughout the core
0402      */
0403     ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
0404              SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
0405              SSB_TMSLOW_RESET);
0406     regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
0407     udelay(1);
0408 
0409     /* clear any serror */
0410     regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
0411     if (regdata & SSB_TMSHIGH_SERR)
0412         ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatehigh), 0);
0413 
0414     regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbimstate));
0415     if (regdata & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
0416         regdata &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
0417         ci->ops->write32(ci->ctx, CORE_SB(base, sbimstate), regdata);
0418     }
0419 
0420     /* clear reset and allow it to propagate throughout the core */
0421     ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
0422              SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK);
0423     regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
0424     udelay(1);
0425 
0426     /* leave clock enabled */
0427     ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
0428              SSB_TMSLOW_CLOCK);
0429     regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
0430     udelay(1);
0431 }
0432 
0433 static void brcmf_chip_ai_resetcore(struct brcmf_core_priv *core, u32 prereset,
0434                     u32 reset, u32 postreset)
0435 {
0436     struct brcmf_chip_priv *ci;
0437     int count;
0438     struct brcmf_core *d11core2 = NULL;
0439     struct brcmf_core_priv *d11priv2 = NULL;
0440 
0441     ci = core->chip;
0442 
0443     /* special handle two D11 cores reset */
0444     if (core->pub.id == BCMA_CORE_80211) {
0445         d11core2 = brcmf_chip_get_d11core(&ci->pub, 1);
0446         if (d11core2) {
0447             brcmf_dbg(INFO, "found two d11 cores, reset both\n");
0448             d11priv2 = container_of(d11core2,
0449                         struct brcmf_core_priv, pub);
0450         }
0451     }
0452 
0453     /* must disable first to work for arbitrary current core state */
0454     brcmf_chip_ai_coredisable(core, prereset, reset);
0455     if (d11priv2)
0456         brcmf_chip_ai_coredisable(d11priv2, prereset, reset);
0457 
0458     count = 0;
0459     while (ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) &
0460            BCMA_RESET_CTL_RESET) {
0461         ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL, 0);
0462         count++;
0463         if (count > 50)
0464             break;
0465         usleep_range(40, 60);
0466     }
0467 
0468     if (d11priv2) {
0469         count = 0;
0470         while (ci->ops->read32(ci->ctx,
0471                        d11priv2->wrapbase + BCMA_RESET_CTL) &
0472                        BCMA_RESET_CTL_RESET) {
0473             ci->ops->write32(ci->ctx,
0474                      d11priv2->wrapbase + BCMA_RESET_CTL,
0475                      0);
0476             count++;
0477             if (count > 50)
0478                 break;
0479             usleep_range(40, 60);
0480         }
0481     }
0482 
0483     ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
0484              postreset | BCMA_IOCTL_CLK);
0485     ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
0486 
0487     if (d11priv2) {
0488         ci->ops->write32(ci->ctx, d11priv2->wrapbase + BCMA_IOCTL,
0489                  postreset | BCMA_IOCTL_CLK);
0490         ci->ops->read32(ci->ctx, d11priv2->wrapbase + BCMA_IOCTL);
0491     }
0492 }
0493 
0494 char *brcmf_chip_name(u32 id, u32 rev, char *buf, uint len)
0495 {
0496     const char *fmt;
0497 
0498     fmt = ((id > 0xa000) || (id < 0x4000)) ? "BCM%d/%u" : "BCM%x/%u";
0499     snprintf(buf, len, fmt, id, rev);
0500     return buf;
0501 }
0502 
0503 static struct brcmf_core *brcmf_chip_add_core(struct brcmf_chip_priv *ci,
0504                           u16 coreid, u32 base,
0505                           u32 wrapbase)
0506 {
0507     struct brcmf_core_priv *core;
0508 
0509     core = kzalloc(sizeof(*core), GFP_KERNEL);
0510     if (!core)
0511         return ERR_PTR(-ENOMEM);
0512 
0513     core->pub.id = coreid;
0514     core->pub.base = base;
0515     core->chip = ci;
0516     core->wrapbase = wrapbase;
0517 
0518     list_add_tail(&core->list, &ci->cores);
0519     return &core->pub;
0520 }
0521 
0522 /* safety check for chipinfo */
0523 static int brcmf_chip_cores_check(struct brcmf_chip_priv *ci)
0524 {
0525     struct brcmf_core_priv *core;
0526     bool need_socram = false;
0527     bool has_socram = false;
0528     bool cpu_found = false;
0529     int idx = 1;
0530 
0531     list_for_each_entry(core, &ci->cores, list) {
0532         brcmf_dbg(INFO, " [%-2d] core 0x%x:%-3d base 0x%08x wrap 0x%08x\n",
0533               idx++, core->pub.id, core->pub.rev, core->pub.base,
0534               core->wrapbase);
0535 
0536         switch (core->pub.id) {
0537         case BCMA_CORE_ARM_CM3:
0538             cpu_found = true;
0539             need_socram = true;
0540             break;
0541         case BCMA_CORE_INTERNAL_MEM:
0542             has_socram = true;
0543             break;
0544         case BCMA_CORE_ARM_CR4:
0545             cpu_found = true;
0546             break;
0547         case BCMA_CORE_ARM_CA7:
0548             cpu_found = true;
0549             break;
0550         default:
0551             break;
0552         }
0553     }
0554 
0555     if (!cpu_found) {
0556         brcmf_err("CPU core not detected\n");
0557         return -ENXIO;
0558     }
0559     /* check RAM core presence for ARM CM3 core */
0560     if (need_socram && !has_socram) {
0561         brcmf_err("RAM core not provided with ARM CM3 core\n");
0562         return -ENODEV;
0563     }
0564     return 0;
0565 }
0566 
0567 static u32 brcmf_chip_core_read32(struct brcmf_core_priv *core, u16 reg)
0568 {
0569     return core->chip->ops->read32(core->chip->ctx, core->pub.base + reg);
0570 }
0571 
0572 static void brcmf_chip_core_write32(struct brcmf_core_priv *core,
0573                     u16 reg, u32 val)
0574 {
0575     core->chip->ops->write32(core->chip->ctx, core->pub.base + reg, val);
0576 }
0577 
0578 static bool brcmf_chip_socram_banksize(struct brcmf_core_priv *core, u8 idx,
0579                        u32 *banksize)
0580 {
0581     u32 bankinfo;
0582     u32 bankidx = (SOCRAM_MEMTYPE_RAM << SOCRAM_BANKIDX_MEMTYPE_SHIFT);
0583 
0584     bankidx |= idx;
0585     brcmf_chip_core_write32(core, SOCRAMREGOFFS(bankidx), bankidx);
0586     bankinfo = brcmf_chip_core_read32(core, SOCRAMREGOFFS(bankinfo));
0587     *banksize = (bankinfo & SOCRAM_BANKINFO_SZMASK) + 1;
0588     *banksize *= SOCRAM_BANKINFO_SZBASE;
0589     return !!(bankinfo & SOCRAM_BANKINFO_RETNTRAM_MASK);
0590 }
0591 
0592 static void brcmf_chip_socram_ramsize(struct brcmf_core_priv *sr, u32 *ramsize,
0593                       u32 *srsize)
0594 {
0595     u32 coreinfo;
0596     uint nb, banksize, lss;
0597     bool retent;
0598     int i;
0599 
0600     *ramsize = 0;
0601     *srsize = 0;
0602 
0603     if (WARN_ON(sr->pub.rev < 4))
0604         return;
0605 
0606     if (!brcmf_chip_iscoreup(&sr->pub))
0607         brcmf_chip_resetcore(&sr->pub, 0, 0, 0);
0608 
0609     /* Get info for determining size */
0610     coreinfo = brcmf_chip_core_read32(sr, SOCRAMREGOFFS(coreinfo));
0611     nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
0612 
0613     if ((sr->pub.rev <= 7) || (sr->pub.rev == 12)) {
0614         banksize = (coreinfo & SRCI_SRBSZ_MASK);
0615         lss = (coreinfo & SRCI_LSS_MASK) >> SRCI_LSS_SHIFT;
0616         if (lss != 0)
0617             nb--;
0618         *ramsize = nb * (1 << (banksize + SR_BSZ_BASE));
0619         if (lss != 0)
0620             *ramsize += (1 << ((lss - 1) + SR_BSZ_BASE));
0621     } else {
0622         /* length of SRAM Banks increased for corerev greater than 23 */
0623         if (sr->pub.rev >= 23) {
0624             nb = (coreinfo & (SRCI_SRNB_MASK | SRCI_SRNB_MASK_EXT))
0625                 >> SRCI_SRNB_SHIFT;
0626         } else {
0627             nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
0628         }
0629         for (i = 0; i < nb; i++) {
0630             retent = brcmf_chip_socram_banksize(sr, i, &banksize);
0631             *ramsize += banksize;
0632             if (retent)
0633                 *srsize += banksize;
0634         }
0635     }
0636 
0637     /* hardcoded save&restore memory sizes */
0638     switch (sr->chip->pub.chip) {
0639     case BRCM_CC_4334_CHIP_ID:
0640         if (sr->chip->pub.chiprev < 2)
0641             *srsize = (32 * 1024);
0642         break;
0643     case BRCM_CC_43430_CHIP_ID:
0644         /* assume sr for now as we can not check
0645          * firmware sr capability at this point.
0646          */
0647         *srsize = (64 * 1024);
0648         break;
0649     default:
0650         break;
0651     }
0652 }
0653 
0654 /** Return the SYS MEM size */
0655 static u32 brcmf_chip_sysmem_ramsize(struct brcmf_core_priv *sysmem)
0656 {
0657     u32 memsize = 0;
0658     u32 coreinfo;
0659     u32 idx;
0660     u32 nb;
0661     u32 banksize;
0662 
0663     if (!brcmf_chip_iscoreup(&sysmem->pub))
0664         brcmf_chip_resetcore(&sysmem->pub, 0, 0, 0);
0665 
0666     coreinfo = brcmf_chip_core_read32(sysmem, SYSMEMREGOFFS(coreinfo));
0667     nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
0668 
0669     for (idx = 0; idx < nb; idx++) {
0670         brcmf_chip_socram_banksize(sysmem, idx, &banksize);
0671         memsize += banksize;
0672     }
0673 
0674     return memsize;
0675 }
0676 
0677 /** Return the TCM-RAM size of the ARMCR4 core. */
0678 static u32 brcmf_chip_tcm_ramsize(struct brcmf_core_priv *cr4)
0679 {
0680     u32 corecap;
0681     u32 memsize = 0;
0682     u32 nab;
0683     u32 nbb;
0684     u32 totb;
0685     u32 bxinfo;
0686     u32 idx;
0687 
0688     corecap = brcmf_chip_core_read32(cr4, ARMCR4_CAP);
0689 
0690     nab = (corecap & ARMCR4_TCBANB_MASK) >> ARMCR4_TCBANB_SHIFT;
0691     nbb = (corecap & ARMCR4_TCBBNB_MASK) >> ARMCR4_TCBBNB_SHIFT;
0692     totb = nab + nbb;
0693 
0694     for (idx = 0; idx < totb; idx++) {
0695         brcmf_chip_core_write32(cr4, ARMCR4_BANKIDX, idx);
0696         bxinfo = brcmf_chip_core_read32(cr4, ARMCR4_BANKINFO);
0697         memsize += ((bxinfo & ARMCR4_BSZ_MASK) + 1) * ARMCR4_BSZ_MULT;
0698     }
0699 
0700     return memsize;
0701 }
0702 
0703 static u32 brcmf_chip_tcm_rambase(struct brcmf_chip_priv *ci)
0704 {
0705     switch (ci->pub.chip) {
0706     case BRCM_CC_4345_CHIP_ID:
0707     case BRCM_CC_43454_CHIP_ID:
0708         return 0x198000;
0709     case BRCM_CC_4335_CHIP_ID:
0710     case BRCM_CC_4339_CHIP_ID:
0711     case BRCM_CC_4350_CHIP_ID:
0712     case BRCM_CC_4354_CHIP_ID:
0713     case BRCM_CC_4356_CHIP_ID:
0714     case BRCM_CC_43567_CHIP_ID:
0715     case BRCM_CC_43569_CHIP_ID:
0716     case BRCM_CC_43570_CHIP_ID:
0717     case BRCM_CC_4358_CHIP_ID:
0718     case BRCM_CC_43602_CHIP_ID:
0719     case BRCM_CC_4371_CHIP_ID:
0720         return 0x180000;
0721     case BRCM_CC_43465_CHIP_ID:
0722     case BRCM_CC_43525_CHIP_ID:
0723     case BRCM_CC_4365_CHIP_ID:
0724     case BRCM_CC_4366_CHIP_ID:
0725     case BRCM_CC_43664_CHIP_ID:
0726     case BRCM_CC_43666_CHIP_ID:
0727         return 0x200000;
0728     case BRCM_CC_4359_CHIP_ID:
0729         return (ci->pub.chiprev < 9) ? 0x180000 : 0x160000;
0730     case BRCM_CC_4364_CHIP_ID:
0731     case CY_CC_4373_CHIP_ID:
0732         return 0x160000;
0733     case CY_CC_43752_CHIP_ID:
0734         return 0x170000;
0735     default:
0736         brcmf_err("unknown chip: %s\n", ci->pub.name);
0737         break;
0738     }
0739     return INVALID_RAMBASE;
0740 }
0741 
0742 int brcmf_chip_get_raminfo(struct brcmf_chip *pub)
0743 {
0744     struct brcmf_chip_priv *ci = container_of(pub, struct brcmf_chip_priv,
0745                           pub);
0746     struct brcmf_core_priv *mem_core;
0747     struct brcmf_core *mem;
0748 
0749     mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_ARM_CR4);
0750     if (mem) {
0751         mem_core = container_of(mem, struct brcmf_core_priv, pub);
0752         ci->pub.ramsize = brcmf_chip_tcm_ramsize(mem_core);
0753         ci->pub.rambase = brcmf_chip_tcm_rambase(ci);
0754         if (ci->pub.rambase == INVALID_RAMBASE) {
0755             brcmf_err("RAM base not provided with ARM CR4 core\n");
0756             return -EINVAL;
0757         }
0758     } else {
0759         mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_SYS_MEM);
0760         if (mem) {
0761             mem_core = container_of(mem, struct brcmf_core_priv,
0762                         pub);
0763             ci->pub.ramsize = brcmf_chip_sysmem_ramsize(mem_core);
0764             ci->pub.rambase = brcmf_chip_tcm_rambase(ci);
0765             if (ci->pub.rambase == INVALID_RAMBASE) {
0766                 brcmf_err("RAM base not provided with ARM CA7 core\n");
0767                 return -EINVAL;
0768             }
0769         } else {
0770             mem = brcmf_chip_get_core(&ci->pub,
0771                           BCMA_CORE_INTERNAL_MEM);
0772             if (!mem) {
0773                 brcmf_err("No memory cores found\n");
0774                 return -ENOMEM;
0775             }
0776             mem_core = container_of(mem, struct brcmf_core_priv,
0777                         pub);
0778             brcmf_chip_socram_ramsize(mem_core, &ci->pub.ramsize,
0779                           &ci->pub.srsize);
0780         }
0781     }
0782     brcmf_dbg(INFO, "RAM: base=0x%x size=%d (0x%x) sr=%d (0x%x)\n",
0783           ci->pub.rambase, ci->pub.ramsize, ci->pub.ramsize,
0784           ci->pub.srsize, ci->pub.srsize);
0785 
0786     if (!ci->pub.ramsize) {
0787         brcmf_err("RAM size is undetermined\n");
0788         return -ENOMEM;
0789     }
0790 
0791     if (ci->pub.ramsize > BRCMF_CHIP_MAX_MEMSIZE) {
0792         brcmf_err("RAM size is incorrect\n");
0793         return -ENOMEM;
0794     }
0795 
0796     return 0;
0797 }
0798 
0799 static u32 brcmf_chip_dmp_get_desc(struct brcmf_chip_priv *ci, u32 *eromaddr,
0800                    u8 *type)
0801 {
0802     u32 val;
0803 
0804     /* read next descriptor */
0805     val = ci->ops->read32(ci->ctx, *eromaddr);
0806     *eromaddr += 4;
0807 
0808     if (!type)
0809         return val;
0810 
0811     /* determine descriptor type */
0812     *type = (val & DMP_DESC_TYPE_MSK);
0813     if ((*type & ~DMP_DESC_ADDRSIZE_GT32) == DMP_DESC_ADDRESS)
0814         *type = DMP_DESC_ADDRESS;
0815 
0816     return val;
0817 }
0818 
0819 static int brcmf_chip_dmp_get_regaddr(struct brcmf_chip_priv *ci, u32 *eromaddr,
0820                       u32 *regbase, u32 *wrapbase)
0821 {
0822     u8 desc;
0823     u32 val, szdesc;
0824     u8 stype, sztype, wraptype;
0825 
0826     *regbase = 0;
0827     *wrapbase = 0;
0828 
0829     val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
0830     if (desc == DMP_DESC_MASTER_PORT) {
0831         wraptype = DMP_SLAVE_TYPE_MWRAP;
0832     } else if (desc == DMP_DESC_ADDRESS) {
0833         /* revert erom address */
0834         *eromaddr -= 4;
0835         wraptype = DMP_SLAVE_TYPE_SWRAP;
0836     } else {
0837         *eromaddr -= 4;
0838         return -EILSEQ;
0839     }
0840 
0841     do {
0842         /* locate address descriptor */
0843         do {
0844             val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
0845             /* unexpected table end */
0846             if (desc == DMP_DESC_EOT) {
0847                 *eromaddr -= 4;
0848                 return -EFAULT;
0849             }
0850         } while (desc != DMP_DESC_ADDRESS &&
0851              desc != DMP_DESC_COMPONENT);
0852 
0853         /* stop if we crossed current component border */
0854         if (desc == DMP_DESC_COMPONENT) {
0855             *eromaddr -= 4;
0856             return 0;
0857         }
0858 
0859         /* skip upper 32-bit address descriptor */
0860         if (val & DMP_DESC_ADDRSIZE_GT32)
0861             brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
0862 
0863         sztype = (val & DMP_SLAVE_SIZE_TYPE) >> DMP_SLAVE_SIZE_TYPE_S;
0864 
0865         /* next size descriptor can be skipped */
0866         if (sztype == DMP_SLAVE_SIZE_DESC) {
0867             szdesc = brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
0868             /* skip upper size descriptor if present */
0869             if (szdesc & DMP_DESC_ADDRSIZE_GT32)
0870                 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
0871         }
0872 
0873         /* look for 4K or 8K register regions */
0874         if (sztype != DMP_SLAVE_SIZE_4K &&
0875             sztype != DMP_SLAVE_SIZE_8K)
0876             continue;
0877 
0878         stype = (val & DMP_SLAVE_TYPE) >> DMP_SLAVE_TYPE_S;
0879 
0880         /* only regular slave and wrapper */
0881         if (*regbase == 0 && stype == DMP_SLAVE_TYPE_SLAVE)
0882             *regbase = val & DMP_SLAVE_ADDR_BASE;
0883         if (*wrapbase == 0 && stype == wraptype)
0884             *wrapbase = val & DMP_SLAVE_ADDR_BASE;
0885     } while (*regbase == 0 || *wrapbase == 0);
0886 
0887     return 0;
0888 }
0889 
0890 static
0891 int brcmf_chip_dmp_erom_scan(struct brcmf_chip_priv *ci)
0892 {
0893     struct brcmf_core *core;
0894     u32 eromaddr;
0895     u8 desc_type = 0;
0896     u32 val;
0897     u16 id;
0898     u8 nmw, nsw, rev;
0899     u32 base, wrap;
0900     int err;
0901 
0902     eromaddr = ci->ops->read32(ci->ctx,
0903                    CORE_CC_REG(ci->pub.enum_base, eromptr));
0904 
0905     while (desc_type != DMP_DESC_EOT) {
0906         val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
0907         if (!(val & DMP_DESC_VALID))
0908             continue;
0909 
0910         if (desc_type == DMP_DESC_EMPTY)
0911             continue;
0912 
0913         /* need a component descriptor */
0914         if (desc_type != DMP_DESC_COMPONENT)
0915             continue;
0916 
0917         id = (val & DMP_COMP_PARTNUM) >> DMP_COMP_PARTNUM_S;
0918 
0919         /* next descriptor must be component as well */
0920         val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
0921         if (WARN_ON((val & DMP_DESC_TYPE_MSK) != DMP_DESC_COMPONENT))
0922             return -EFAULT;
0923 
0924         /* only look at cores with master port(s) */
0925         nmw = (val & DMP_COMP_NUM_MWRAP) >> DMP_COMP_NUM_MWRAP_S;
0926         nsw = (val & DMP_COMP_NUM_SWRAP) >> DMP_COMP_NUM_SWRAP_S;
0927         rev = (val & DMP_COMP_REVISION) >> DMP_COMP_REVISION_S;
0928 
0929         /* need core with ports */
0930         if (nmw + nsw == 0 &&
0931             id != BCMA_CORE_PMU &&
0932             id != BCMA_CORE_GCI)
0933             continue;
0934 
0935         /* try to obtain register address info */
0936         err = brcmf_chip_dmp_get_regaddr(ci, &eromaddr, &base, &wrap);
0937         if (err)
0938             continue;
0939 
0940         /* finally a core to be added */
0941         core = brcmf_chip_add_core(ci, id, base, wrap);
0942         if (IS_ERR(core))
0943             return PTR_ERR(core);
0944 
0945         core->rev = rev;
0946     }
0947 
0948     return 0;
0949 }
0950 
0951 u32 brcmf_chip_enum_base(u16 devid)
0952 {
0953     return SI_ENUM_BASE_DEFAULT;
0954 }
0955 
0956 static int brcmf_chip_recognition(struct brcmf_chip_priv *ci)
0957 {
0958     struct brcmf_core *core;
0959     u32 regdata;
0960     u32 socitype;
0961     int ret;
0962 
0963     /* Get CC core rev
0964      * Chipid is assume to be at offset 0 from SI_ENUM_BASE
0965      * For different chiptypes or old sdio hosts w/o chipcommon,
0966      * other ways of recognition should be added here.
0967      */
0968     regdata = ci->ops->read32(ci->ctx,
0969                   CORE_CC_REG(ci->pub.enum_base, chipid));
0970     ci->pub.chip = regdata & CID_ID_MASK;
0971     ci->pub.chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
0972     socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
0973 
0974     brcmf_chip_name(ci->pub.chip, ci->pub.chiprev,
0975             ci->pub.name, sizeof(ci->pub.name));
0976     brcmf_dbg(INFO, "found %s chip: %s\n",
0977           socitype == SOCI_SB ? "SB" : "AXI", ci->pub.name);
0978 
0979     if (socitype == SOCI_SB) {
0980         if (ci->pub.chip != BRCM_CC_4329_CHIP_ID) {
0981             brcmf_err("SB chip is not supported\n");
0982             return -ENODEV;
0983         }
0984         ci->iscoreup = brcmf_chip_sb_iscoreup;
0985         ci->coredisable = brcmf_chip_sb_coredisable;
0986         ci->resetcore = brcmf_chip_sb_resetcore;
0987 
0988         core = brcmf_chip_add_core(ci, BCMA_CORE_CHIPCOMMON,
0989                        SI_ENUM_BASE_DEFAULT, 0);
0990         brcmf_chip_sb_corerev(ci, core);
0991         core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
0992                        BCM4329_CORE_BUS_BASE, 0);
0993         brcmf_chip_sb_corerev(ci, core);
0994         core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM,
0995                        BCM4329_CORE_SOCRAM_BASE, 0);
0996         brcmf_chip_sb_corerev(ci, core);
0997         core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
0998                        BCM4329_CORE_ARM_BASE, 0);
0999         brcmf_chip_sb_corerev(ci, core);
1000 
1001         core = brcmf_chip_add_core(ci, BCMA_CORE_80211, 0x18001000, 0);
1002         brcmf_chip_sb_corerev(ci, core);
1003     } else if (socitype == SOCI_AI) {
1004         ci->iscoreup = brcmf_chip_ai_iscoreup;
1005         ci->coredisable = brcmf_chip_ai_coredisable;
1006         ci->resetcore = brcmf_chip_ai_resetcore;
1007 
1008         brcmf_chip_dmp_erom_scan(ci);
1009     } else {
1010         brcmf_err("chip backplane type %u is not supported\n",
1011               socitype);
1012         return -ENODEV;
1013     }
1014 
1015     ret = brcmf_chip_cores_check(ci);
1016     if (ret)
1017         return ret;
1018 
1019     /* assure chip is passive for core access */
1020     brcmf_chip_set_passive(&ci->pub);
1021 
1022     /* Call bus specific reset function now. Cores have been determined
1023      * but further access may require a chip specific reset at this point.
1024      */
1025     if (ci->ops->reset) {
1026         ci->ops->reset(ci->ctx, &ci->pub);
1027         brcmf_chip_set_passive(&ci->pub);
1028     }
1029 
1030     return brcmf_chip_get_raminfo(&ci->pub);
1031 }
1032 
1033 static void brcmf_chip_disable_arm(struct brcmf_chip_priv *chip, u16 id)
1034 {
1035     struct brcmf_core *core;
1036     struct brcmf_core_priv *cpu;
1037     u32 val;
1038 
1039 
1040     core = brcmf_chip_get_core(&chip->pub, id);
1041     if (!core)
1042         return;
1043 
1044     switch (id) {
1045     case BCMA_CORE_ARM_CM3:
1046         brcmf_chip_coredisable(core, 0, 0);
1047         break;
1048     case BCMA_CORE_ARM_CR4:
1049     case BCMA_CORE_ARM_CA7:
1050         cpu = container_of(core, struct brcmf_core_priv, pub);
1051 
1052         /* clear all IOCTL bits except HALT bit */
1053         val = chip->ops->read32(chip->ctx, cpu->wrapbase + BCMA_IOCTL);
1054         val &= ARMCR4_BCMA_IOCTL_CPUHALT;
1055         brcmf_chip_resetcore(core, val, ARMCR4_BCMA_IOCTL_CPUHALT,
1056                      ARMCR4_BCMA_IOCTL_CPUHALT);
1057         break;
1058     default:
1059         brcmf_err("unknown id: %u\n", id);
1060         break;
1061     }
1062 }
1063 
1064 static int brcmf_chip_setup(struct brcmf_chip_priv *chip)
1065 {
1066     struct brcmf_chip *pub;
1067     struct brcmf_core_priv *cc;
1068     struct brcmf_core *pmu;
1069     u32 base;
1070     u32 val;
1071     int ret = 0;
1072 
1073     pub = &chip->pub;
1074     cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
1075     base = cc->pub.base;
1076 
1077     /* get chipcommon capabilites */
1078     pub->cc_caps = chip->ops->read32(chip->ctx,
1079                      CORE_CC_REG(base, capabilities));
1080     pub->cc_caps_ext = chip->ops->read32(chip->ctx,
1081                          CORE_CC_REG(base,
1082                              capabilities_ext));
1083 
1084     /* get pmu caps & rev */
1085     pmu = brcmf_chip_get_pmu(pub); /* after reading cc_caps_ext */
1086     if (pub->cc_caps & CC_CAP_PMU) {
1087         val = chip->ops->read32(chip->ctx,
1088                     CORE_CC_REG(pmu->base, pmucapabilities));
1089         pub->pmurev = val & PCAP_REV_MASK;
1090         pub->pmucaps = val;
1091     }
1092 
1093     brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, pmucaps=0x%x\n",
1094           cc->pub.rev, pub->pmurev, pub->pmucaps);
1095 
1096     /* execute bus core specific setup */
1097     if (chip->ops->setup)
1098         ret = chip->ops->setup(chip->ctx, pub);
1099 
1100     return ret;
1101 }
1102 
1103 struct brcmf_chip *brcmf_chip_attach(void *ctx, u16 devid,
1104                      const struct brcmf_buscore_ops *ops)
1105 {
1106     struct brcmf_chip_priv *chip;
1107     int err = 0;
1108 
1109     if (WARN_ON(!ops->read32))
1110         err = -EINVAL;
1111     if (WARN_ON(!ops->write32))
1112         err = -EINVAL;
1113     if (WARN_ON(!ops->prepare))
1114         err = -EINVAL;
1115     if (WARN_ON(!ops->activate))
1116         err = -EINVAL;
1117     if (err < 0)
1118         return ERR_PTR(-EINVAL);
1119 
1120     chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1121     if (!chip)
1122         return ERR_PTR(-ENOMEM);
1123 
1124     INIT_LIST_HEAD(&chip->cores);
1125     chip->num_cores = 0;
1126     chip->ops = ops;
1127     chip->ctx = ctx;
1128     chip->pub.enum_base = brcmf_chip_enum_base(devid);
1129 
1130     err = ops->prepare(ctx);
1131     if (err < 0)
1132         goto fail;
1133 
1134     err = brcmf_chip_recognition(chip);
1135     if (err < 0)
1136         goto fail;
1137 
1138     err = brcmf_chip_setup(chip);
1139     if (err < 0)
1140         goto fail;
1141 
1142     return &chip->pub;
1143 
1144 fail:
1145     brcmf_chip_detach(&chip->pub);
1146     return ERR_PTR(err);
1147 }
1148 
1149 void brcmf_chip_detach(struct brcmf_chip *pub)
1150 {
1151     struct brcmf_chip_priv *chip;
1152     struct brcmf_core_priv *core;
1153     struct brcmf_core_priv *tmp;
1154 
1155     chip = container_of(pub, struct brcmf_chip_priv, pub);
1156     list_for_each_entry_safe(core, tmp, &chip->cores, list) {
1157         list_del(&core->list);
1158         kfree(core);
1159     }
1160     kfree(chip);
1161 }
1162 
1163 struct brcmf_core *brcmf_chip_get_d11core(struct brcmf_chip *pub, u8 unit)
1164 {
1165     struct brcmf_chip_priv *chip;
1166     struct brcmf_core_priv *core;
1167 
1168     chip = container_of(pub, struct brcmf_chip_priv, pub);
1169     list_for_each_entry(core, &chip->cores, list) {
1170         if (core->pub.id == BCMA_CORE_80211) {
1171             if (unit-- == 0)
1172                 return &core->pub;
1173         }
1174     }
1175     return NULL;
1176 }
1177 
1178 struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *pub, u16 coreid)
1179 {
1180     struct brcmf_chip_priv *chip;
1181     struct brcmf_core_priv *core;
1182 
1183     chip = container_of(pub, struct brcmf_chip_priv, pub);
1184     list_for_each_entry(core, &chip->cores, list)
1185         if (core->pub.id == coreid)
1186             return &core->pub;
1187 
1188     return NULL;
1189 }
1190 
1191 struct brcmf_core *brcmf_chip_get_chipcommon(struct brcmf_chip *pub)
1192 {
1193     struct brcmf_chip_priv *chip;
1194     struct brcmf_core_priv *cc;
1195 
1196     chip = container_of(pub, struct brcmf_chip_priv, pub);
1197     cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
1198     if (WARN_ON(!cc || cc->pub.id != BCMA_CORE_CHIPCOMMON))
1199         return brcmf_chip_get_core(pub, BCMA_CORE_CHIPCOMMON);
1200     return &cc->pub;
1201 }
1202 
1203 struct brcmf_core *brcmf_chip_get_pmu(struct brcmf_chip *pub)
1204 {
1205     struct brcmf_core *cc = brcmf_chip_get_chipcommon(pub);
1206     struct brcmf_core *pmu;
1207 
1208     /* See if there is separated PMU core available */
1209     if (cc->rev >= 35 &&
1210         pub->cc_caps_ext & BCMA_CC_CAP_EXT_AOB_PRESENT) {
1211         pmu = brcmf_chip_get_core(pub, BCMA_CORE_PMU);
1212         if (pmu)
1213             return pmu;
1214     }
1215 
1216     /* Fallback to ChipCommon core for older hardware */
1217     return cc;
1218 }
1219 
1220 bool brcmf_chip_iscoreup(struct brcmf_core *pub)
1221 {
1222     struct brcmf_core_priv *core;
1223 
1224     core = container_of(pub, struct brcmf_core_priv, pub);
1225     return core->chip->iscoreup(core);
1226 }
1227 
1228 void brcmf_chip_coredisable(struct brcmf_core *pub, u32 prereset, u32 reset)
1229 {
1230     struct brcmf_core_priv *core;
1231 
1232     core = container_of(pub, struct brcmf_core_priv, pub);
1233     core->chip->coredisable(core, prereset, reset);
1234 }
1235 
1236 void brcmf_chip_resetcore(struct brcmf_core *pub, u32 prereset, u32 reset,
1237               u32 postreset)
1238 {
1239     struct brcmf_core_priv *core;
1240 
1241     core = container_of(pub, struct brcmf_core_priv, pub);
1242     core->chip->resetcore(core, prereset, reset, postreset);
1243 }
1244 
1245 static void
1246 brcmf_chip_cm3_set_passive(struct brcmf_chip_priv *chip)
1247 {
1248     struct brcmf_core *core;
1249     struct brcmf_core_priv *sr;
1250 
1251     brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CM3);
1252     core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
1253     brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
1254                    D11_BCMA_IOCTL_PHYCLOCKEN,
1255                  D11_BCMA_IOCTL_PHYCLOCKEN,
1256                  D11_BCMA_IOCTL_PHYCLOCKEN);
1257     core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
1258     brcmf_chip_resetcore(core, 0, 0, 0);
1259 
1260     /* disable bank #3 remap for this device */
1261     if (chip->pub.chip == BRCM_CC_43430_CHIP_ID) {
1262         sr = container_of(core, struct brcmf_core_priv, pub);
1263         brcmf_chip_core_write32(sr, SOCRAMREGOFFS(bankidx), 3);
1264         brcmf_chip_core_write32(sr, SOCRAMREGOFFS(bankpda), 0);
1265     }
1266 }
1267 
1268 static bool brcmf_chip_cm3_set_active(struct brcmf_chip_priv *chip)
1269 {
1270     struct brcmf_core *core;
1271 
1272     core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
1273     if (!brcmf_chip_iscoreup(core)) {
1274         brcmf_err("SOCRAM core is down after reset?\n");
1275         return false;
1276     }
1277 
1278     chip->ops->activate(chip->ctx, &chip->pub, 0);
1279 
1280     core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CM3);
1281     brcmf_chip_resetcore(core, 0, 0, 0);
1282 
1283     return true;
1284 }
1285 
1286 static inline void
1287 brcmf_chip_cr4_set_passive(struct brcmf_chip_priv *chip)
1288 {
1289     struct brcmf_core *core;
1290 
1291     brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CR4);
1292 
1293     core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
1294     brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
1295                    D11_BCMA_IOCTL_PHYCLOCKEN,
1296                  D11_BCMA_IOCTL_PHYCLOCKEN,
1297                  D11_BCMA_IOCTL_PHYCLOCKEN);
1298 }
1299 
1300 static bool brcmf_chip_cr4_set_active(struct brcmf_chip_priv *chip, u32 rstvec)
1301 {
1302     struct brcmf_core *core;
1303 
1304     chip->ops->activate(chip->ctx, &chip->pub, rstvec);
1305 
1306     /* restore ARM */
1307     core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CR4);
1308     brcmf_chip_resetcore(core, ARMCR4_BCMA_IOCTL_CPUHALT, 0, 0);
1309 
1310     return true;
1311 }
1312 
1313 static inline void
1314 brcmf_chip_ca7_set_passive(struct brcmf_chip_priv *chip)
1315 {
1316     struct brcmf_core *core;
1317 
1318     brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CA7);
1319 
1320     core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
1321     brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
1322                    D11_BCMA_IOCTL_PHYCLOCKEN,
1323                  D11_BCMA_IOCTL_PHYCLOCKEN,
1324                  D11_BCMA_IOCTL_PHYCLOCKEN);
1325 }
1326 
1327 static bool brcmf_chip_ca7_set_active(struct brcmf_chip_priv *chip, u32 rstvec)
1328 {
1329     struct brcmf_core *core;
1330 
1331     chip->ops->activate(chip->ctx, &chip->pub, rstvec);
1332 
1333     /* restore ARM */
1334     core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CA7);
1335     brcmf_chip_resetcore(core, ARMCR4_BCMA_IOCTL_CPUHALT, 0, 0);
1336 
1337     return true;
1338 }
1339 
1340 void brcmf_chip_set_passive(struct brcmf_chip *pub)
1341 {
1342     struct brcmf_chip_priv *chip;
1343     struct brcmf_core *arm;
1344 
1345     brcmf_dbg(TRACE, "Enter\n");
1346 
1347     chip = container_of(pub, struct brcmf_chip_priv, pub);
1348     arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4);
1349     if (arm) {
1350         brcmf_chip_cr4_set_passive(chip);
1351         return;
1352     }
1353     arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CA7);
1354     if (arm) {
1355         brcmf_chip_ca7_set_passive(chip);
1356         return;
1357     }
1358     arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CM3);
1359     if (arm) {
1360         brcmf_chip_cm3_set_passive(chip);
1361         return;
1362     }
1363 }
1364 
1365 bool brcmf_chip_set_active(struct brcmf_chip *pub, u32 rstvec)
1366 {
1367     struct brcmf_chip_priv *chip;
1368     struct brcmf_core *arm;
1369 
1370     brcmf_dbg(TRACE, "Enter\n");
1371 
1372     chip = container_of(pub, struct brcmf_chip_priv, pub);
1373     arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4);
1374     if (arm)
1375         return brcmf_chip_cr4_set_active(chip, rstvec);
1376     arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CA7);
1377     if (arm)
1378         return brcmf_chip_ca7_set_active(chip, rstvec);
1379     arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CM3);
1380     if (arm)
1381         return brcmf_chip_cm3_set_active(chip);
1382 
1383     return false;
1384 }
1385 
1386 bool brcmf_chip_sr_capable(struct brcmf_chip *pub)
1387 {
1388     u32 base, addr, reg, pmu_cc3_mask = ~0;
1389     struct brcmf_chip_priv *chip;
1390     struct brcmf_core *pmu = brcmf_chip_get_pmu(pub);
1391 
1392     brcmf_dbg(TRACE, "Enter\n");
1393 
1394     /* old chips with PMU version less than 17 don't support save restore */
1395     if (pub->pmurev < 17)
1396         return false;
1397 
1398     base = brcmf_chip_get_chipcommon(pub)->base;
1399     chip = container_of(pub, struct brcmf_chip_priv, pub);
1400 
1401     switch (pub->chip) {
1402     case BRCM_CC_4354_CHIP_ID:
1403     case BRCM_CC_4356_CHIP_ID:
1404     case BRCM_CC_4345_CHIP_ID:
1405     case BRCM_CC_43454_CHIP_ID:
1406         /* explicitly check SR engine enable bit */
1407         pmu_cc3_mask = BIT(2);
1408         fallthrough;
1409     case BRCM_CC_43241_CHIP_ID:
1410     case BRCM_CC_4335_CHIP_ID:
1411     case BRCM_CC_4339_CHIP_ID:
1412         /* read PMU chipcontrol register 3 */
1413         addr = CORE_CC_REG(pmu->base, chipcontrol_addr);
1414         chip->ops->write32(chip->ctx, addr, 3);
1415         addr = CORE_CC_REG(pmu->base, chipcontrol_data);
1416         reg = chip->ops->read32(chip->ctx, addr);
1417         return (reg & pmu_cc3_mask) != 0;
1418     case BRCM_CC_43430_CHIP_ID:
1419         addr = CORE_CC_REG(base, sr_control1);
1420         reg = chip->ops->read32(chip->ctx, addr);
1421         return reg != 0;
1422     case CY_CC_4373_CHIP_ID:
1423         /* explicitly check SR engine enable bit */
1424         addr = CORE_CC_REG(base, sr_control0);
1425         reg = chip->ops->read32(chip->ctx, addr);
1426         return (reg & CC_SR_CTL0_ENABLE_MASK) != 0;
1427     case BRCM_CC_4359_CHIP_ID:
1428     case CY_CC_43752_CHIP_ID:
1429     case CY_CC_43012_CHIP_ID:
1430         addr = CORE_CC_REG(pmu->base, retention_ctl);
1431         reg = chip->ops->read32(chip->ctx, addr);
1432         return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
1433                    PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;
1434     default:
1435         addr = CORE_CC_REG(pmu->base, pmucapabilities_ext);
1436         reg = chip->ops->read32(chip->ctx, addr);
1437         if ((reg & PCAPEXT_SR_SUPPORTED_MASK) == 0)
1438             return false;
1439 
1440         addr = CORE_CC_REG(pmu->base, retention_ctl);
1441         reg = chip->ops->read32(chip->ctx, addr);
1442         return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
1443                    PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;
1444     }
1445 }
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