broadcom/b43legacy/dma.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef B43legacy_DMA_H_
0003 #define B43legacy_DMA_H_
0004
0005 #include <linux/list.h>
0006 #include <linux/spinlock.h>
0007 #include <linux/workqueue.h>
0008 #include <linux/linkage.h>
0009 #include <linux/atomic.h>
0010
0011 #include "b43legacy.h"
0012
0013
0014 /* DMA-Interrupt reasons. */
0015 #define B43legacy_DMAIRQ_FATALMASK  ((1 << 10) | (1 << 11) | (1 << 12) \
0016                      | (1 << 14) | (1 << 15))
0017 #define B43legacy_DMAIRQ_NONFATALMASK   (1 << 13)
0018 #define B43legacy_DMAIRQ_RX_DONE        (1 << 16)
0019
0020
0021 /*** 32-bit DMA Engine. ***/
0022
0023 /* 32-bit DMA controller registers. */
0024 #define B43legacy_DMA32_TXCTL               0x00
0025 #define     B43legacy_DMA32_TXENABLE        0x00000001
0026 #define     B43legacy_DMA32_TXSUSPEND       0x00000002
0027 #define     B43legacy_DMA32_TXLOOPBACK      0x00000004
0028 #define     B43legacy_DMA32_TXFLUSH         0x00000010
0029 #define     B43legacy_DMA32_TXADDREXT_MASK      0x00030000
0030 #define     B43legacy_DMA32_TXADDREXT_SHIFT     16
0031 #define B43legacy_DMA32_TXRING              0x04
0032 #define B43legacy_DMA32_TXINDEX             0x08
0033 #define B43legacy_DMA32_TXSTATUS            0x0C
0034 #define     B43legacy_DMA32_TXDPTR          0x00000FFF
0035 #define     B43legacy_DMA32_TXSTATE         0x0000F000
0036 #define         B43legacy_DMA32_TXSTAT_DISABLED 0x00000000
0037 #define         B43legacy_DMA32_TXSTAT_ACTIVE   0x00001000
0038 #define         B43legacy_DMA32_TXSTAT_IDLEWAIT 0x00002000
0039 #define         B43legacy_DMA32_TXSTAT_STOPPED  0x00003000
0040 #define         B43legacy_DMA32_TXSTAT_SUSP 0x00004000
0041 #define     B43legacy_DMA32_TXERROR         0x000F0000
0042 #define         B43legacy_DMA32_TXERR_NOERR 0x00000000
0043 #define         B43legacy_DMA32_TXERR_PROT  0x00010000
0044 #define         B43legacy_DMA32_TXERR_UNDERRUN  0x00020000
0045 #define         B43legacy_DMA32_TXERR_BUFREAD   0x00030000
0046 #define         B43legacy_DMA32_TXERR_DESCREAD  0x00040000
0047 #define     B43legacy_DMA32_TXACTIVE        0xFFF00000
0048 #define B43legacy_DMA32_RXCTL               0x10
0049 #define     B43legacy_DMA32_RXENABLE        0x00000001
0050 #define     B43legacy_DMA32_RXFROFF_MASK        0x000000FE
0051 #define     B43legacy_DMA32_RXFROFF_SHIFT       1
0052 #define     B43legacy_DMA32_RXDIRECTFIFO        0x00000100
0053 #define     B43legacy_DMA32_RXADDREXT_MASK      0x00030000
0054 #define     B43legacy_DMA32_RXADDREXT_SHIFT     16
0055 #define B43legacy_DMA32_RXRING              0x14
0056 #define B43legacy_DMA32_RXINDEX             0x18
0057 #define B43legacy_DMA32_RXSTATUS            0x1C
0058 #define     B43legacy_DMA32_RXDPTR          0x00000FFF
0059 #define     B43legacy_DMA32_RXSTATE         0x0000F000
0060 #define         B43legacy_DMA32_RXSTAT_DISABLED 0x00000000
0061 #define         B43legacy_DMA32_RXSTAT_ACTIVE   0x00001000
0062 #define         B43legacy_DMA32_RXSTAT_IDLEWAIT 0x00002000
0063 #define         B43legacy_DMA32_RXSTAT_STOPPED  0x00003000
0064 #define     B43legacy_DMA32_RXERROR         0x000F0000
0065 #define         B43legacy_DMA32_RXERR_NOERR 0x00000000
0066 #define         B43legacy_DMA32_RXERR_PROT  0x00010000
0067 #define         B43legacy_DMA32_RXERR_OVERFLOW  0x00020000
0068 #define         B43legacy_DMA32_RXERR_BUFWRITE  0x00030000
0069 #define         B43legacy_DMA32_RXERR_DESCREAD  0x00040000
0070 #define     B43legacy_DMA32_RXACTIVE        0xFFF00000
0071
0072 /* 32-bit DMA descriptor. */
0073 struct b43legacy_dmadesc32 {
0074     __le32 control;
0075     __le32 address;
0076 } __packed;
0077 #define B43legacy_DMA32_DCTL_BYTECNT        0x00001FFF
0078 #define B43legacy_DMA32_DCTL_ADDREXT_MASK   0x00030000
0079 #define B43legacy_DMA32_DCTL_ADDREXT_SHIFT  16
0080 #define B43legacy_DMA32_DCTL_DTABLEEND      0x10000000
0081 #define B43legacy_DMA32_DCTL_IRQ        0x20000000
0082 #define B43legacy_DMA32_DCTL_FRAMEEND       0x40000000
0083 #define B43legacy_DMA32_DCTL_FRAMESTART     0x80000000
0084
0085
0086 /* Misc DMA constants */
0087 #define B43legacy_DMA_RINGMEMSIZE   PAGE_SIZE
0088 #define B43legacy_DMA0_RX_FRAMEOFFSET   30
0089 #define B43legacy_DMA3_RX_FRAMEOFFSET   0
0090
0091
0092 /* DMA engine tuning knobs */
0093 #define B43legacy_TXRING_SLOTS      128
0094 #define B43legacy_RXRING_SLOTS      64
0095 #define B43legacy_DMA0_RX_BUFFERSIZE    (2304 + 100)
0096 #define B43legacy_DMA3_RX_BUFFERSIZE    16
0097
0098
0099
0100 #ifdef CONFIG_B43LEGACY_DMA
0101
0102
0103 struct sk_buff;
0104 struct b43legacy_private;
0105 struct b43legacy_txstatus;
0106
0107
0108 struct b43legacy_dmadesc_meta {
0109     /* The kernel DMA-able buffer. */
0110     struct sk_buff *skb;
0111     /* DMA base bus-address of the descriptor buffer. */
0112     dma_addr_t dmaaddr;
0113     /* ieee80211 TX status. Only used once per 802.11 frag. */
0114     bool is_last_fragment;
0115 };
0116
0117 enum b43legacy_dmatype {
0118     B43legacy_DMA_30BIT = 30,
0119     B43legacy_DMA_32BIT = 32,
0120 };
0121
0122 struct b43legacy_dmaring {
0123     /* Kernel virtual base address of the ring memory. */
0124     void *descbase;
0125     /* Meta data about all descriptors. */
0126     struct b43legacy_dmadesc_meta *meta;
0127     /* Cache of TX headers for each slot.
0128      * This is to avoid an allocation on each TX.
0129      * This is NULL for an RX ring.
0130      */
0131     u8 *txhdr_cache;
0132     /* (Unadjusted) DMA base bus-address of the ring memory. */
0133     dma_addr_t dmabase;
0134     /* Number of descriptor slots in the ring. */
0135     int nr_slots;
0136     /* Number of used descriptor slots. */
0137     int used_slots;
0138     /* Currently used slot in the ring. */
0139     int current_slot;
0140     /* Frameoffset in octets. */
0141     u32 frameoffset;
0142     /* Descriptor buffer size. */
0143     u16 rx_buffersize;
0144     /* The MMIO base register of the DMA controller. */
0145     u16 mmio_base;
0146     /* DMA controller index number (0-5). */
0147     int index;
0148     /* Boolean. Is this a TX ring? */
0149     bool tx;
0150     /* The type of DMA engine used. */
0151     enum b43legacy_dmatype type;
0152     /* Boolean. Is this ring stopped at ieee80211 level? */
0153     bool stopped;
0154     /* The QOS priority assigned to this ring. Only used for TX rings.
0155      * This is the mac80211 "queue" value. */
0156     u8 queue_prio;
0157     struct b43legacy_wldev *dev;
0158 #ifdef CONFIG_B43LEGACY_DEBUG
0159     /* Maximum number of used slots. */
0160     int max_used_slots;
0161     /* Last time we injected a ring overflow. */
0162     unsigned long last_injected_overflow;
0163 #endif /* CONFIG_B43LEGACY_DEBUG*/
0164 };
0165
0166
0167 static inline
0168 u32 b43legacy_dma_read(struct b43legacy_dmaring *ring,
0169                u16 offset)
0170 {
0171     return b43legacy_read32(ring->dev, ring->mmio_base + offset);
0172 }
0173
0174 static inline
0175 void b43legacy_dma_write(struct b43legacy_dmaring *ring,
0176              u16 offset, u32 value)
0177 {
0178     b43legacy_write32(ring->dev, ring->mmio_base + offset, value);
0179 }
0180
0181
0182 int b43legacy_dma_init(struct b43legacy_wldev *dev);
0183 void b43legacy_dma_free(struct b43legacy_wldev *dev);
0184
0185 void b43legacy_dma_tx_suspend(struct b43legacy_wldev *dev);
0186 void b43legacy_dma_tx_resume(struct b43legacy_wldev *dev);
0187
0188 int b43legacy_dma_tx(struct b43legacy_wldev *dev,
0189              struct sk_buff *skb);
0190 void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev,
0191                    const struct b43legacy_txstatus *status);
0192
0193 void b43legacy_dma_rx(struct b43legacy_dmaring *ring);
0194
0195 #else /* CONFIG_B43LEGACY_DMA */
0196
0197
0198 static inline
0199 int b43legacy_dma_init(struct b43legacy_wldev *dev)
0200 {
0201     return 0;
0202 }
0203 static inline
0204 void b43legacy_dma_free(struct b43legacy_wldev *dev)
0205 {
0206 }
0207 static inline
0208 int b43legacy_dma_tx(struct b43legacy_wldev *dev,
0209              struct sk_buff *skb)
0210 {
0211     return 0;
0212 }
0213 static inline
0214 void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev,
0215                    const struct b43legacy_txstatus *status)
0216 {
0217 }
0218 static inline
0219 void b43legacy_dma_rx(struct b43legacy_dmaring *ring)
0220 {
0221 }
0222 static inline
0223 void b43legacy_dma_tx_suspend(struct b43legacy_wldev *dev)
0224 {
0225 }
0226 static inline
0227 void b43legacy_dma_tx_resume(struct b43legacy_wldev *dev)
0228 {
0229 }
0230
0231 #endif /* CONFIG_B43LEGACY_DMA */
0232 #endif /* B43legacy_DMA_H_ */