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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 
0004   Broadcom B43legacy wireless driver
0005 
0006   DMA ringbuffer and descriptor allocation/management
0007 
0008   Copyright (c) 2005, 2006 Michael Buesch <m@bues.ch>
0009 
0010   Some code in this file is derived from the b44.c driver
0011   Copyright (C) 2002 David S. Miller
0012   Copyright (C) Pekka Pietikainen
0013 
0014 
0015 */
0016 
0017 #include "b43legacy.h"
0018 #include "dma.h"
0019 #include "main.h"
0020 #include "debugfs.h"
0021 #include "xmit.h"
0022 
0023 #include <linux/dma-mapping.h>
0024 #include <linux/pci.h>
0025 #include <linux/delay.h>
0026 #include <linux/skbuff.h>
0027 #include <linux/slab.h>
0028 #include <net/dst.h>
0029 
0030 /* 32bit DMA ops. */
0031 static
0032 struct b43legacy_dmadesc32 *op32_idx2desc(struct b43legacy_dmaring *ring,
0033                       int slot,
0034                       struct b43legacy_dmadesc_meta **meta)
0035 {
0036     struct b43legacy_dmadesc32 *desc;
0037 
0038     *meta = &(ring->meta[slot]);
0039     desc = ring->descbase;
0040     desc = &(desc[slot]);
0041 
0042     return desc;
0043 }
0044 
0045 static void op32_fill_descriptor(struct b43legacy_dmaring *ring,
0046                  struct b43legacy_dmadesc32 *desc,
0047                  dma_addr_t dmaaddr, u16 bufsize,
0048                  int start, int end, int irq)
0049 {
0050     struct b43legacy_dmadesc32 *descbase = ring->descbase;
0051     int slot;
0052     u32 ctl;
0053     u32 addr;
0054     u32 addrext;
0055 
0056     slot = (int)(desc - descbase);
0057     B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
0058 
0059     addr = (u32)(dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
0060     addrext = (u32)(dmaaddr & SSB_DMA_TRANSLATION_MASK)
0061            >> SSB_DMA_TRANSLATION_SHIFT;
0062     addr |= ring->dev->dma.translation;
0063     ctl = (bufsize - ring->frameoffset)
0064           & B43legacy_DMA32_DCTL_BYTECNT;
0065     if (slot == ring->nr_slots - 1)
0066         ctl |= B43legacy_DMA32_DCTL_DTABLEEND;
0067     if (start)
0068         ctl |= B43legacy_DMA32_DCTL_FRAMESTART;
0069     if (end)
0070         ctl |= B43legacy_DMA32_DCTL_FRAMEEND;
0071     if (irq)
0072         ctl |= B43legacy_DMA32_DCTL_IRQ;
0073     ctl |= (addrext << B43legacy_DMA32_DCTL_ADDREXT_SHIFT)
0074            & B43legacy_DMA32_DCTL_ADDREXT_MASK;
0075 
0076     desc->control = cpu_to_le32(ctl);
0077     desc->address = cpu_to_le32(addr);
0078 }
0079 
0080 static void op32_poke_tx(struct b43legacy_dmaring *ring, int slot)
0081 {
0082     b43legacy_dma_write(ring, B43legacy_DMA32_TXINDEX,
0083                 (u32)(slot * sizeof(struct b43legacy_dmadesc32)));
0084 }
0085 
0086 static void op32_tx_suspend(struct b43legacy_dmaring *ring)
0087 {
0088     b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
0089                 b43legacy_dma_read(ring, B43legacy_DMA32_TXCTL)
0090                 | B43legacy_DMA32_TXSUSPEND);
0091 }
0092 
0093 static void op32_tx_resume(struct b43legacy_dmaring *ring)
0094 {
0095     b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
0096                 b43legacy_dma_read(ring, B43legacy_DMA32_TXCTL)
0097                 & ~B43legacy_DMA32_TXSUSPEND);
0098 }
0099 
0100 static int op32_get_current_rxslot(struct b43legacy_dmaring *ring)
0101 {
0102     u32 val;
0103 
0104     val = b43legacy_dma_read(ring, B43legacy_DMA32_RXSTATUS);
0105     val &= B43legacy_DMA32_RXDPTR;
0106 
0107     return (val / sizeof(struct b43legacy_dmadesc32));
0108 }
0109 
0110 static void op32_set_current_rxslot(struct b43legacy_dmaring *ring,
0111                     int slot)
0112 {
0113     b43legacy_dma_write(ring, B43legacy_DMA32_RXINDEX,
0114                 (u32)(slot * sizeof(struct b43legacy_dmadesc32)));
0115 }
0116 
0117 static inline int free_slots(struct b43legacy_dmaring *ring)
0118 {
0119     return (ring->nr_slots - ring->used_slots);
0120 }
0121 
0122 static inline int next_slot(struct b43legacy_dmaring *ring, int slot)
0123 {
0124     B43legacy_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
0125     if (slot == ring->nr_slots - 1)
0126         return 0;
0127     return slot + 1;
0128 }
0129 
0130 static inline int prev_slot(struct b43legacy_dmaring *ring, int slot)
0131 {
0132     B43legacy_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
0133     if (slot == 0)
0134         return ring->nr_slots - 1;
0135     return slot - 1;
0136 }
0137 
0138 #ifdef CONFIG_B43LEGACY_DEBUG
0139 static void update_max_used_slots(struct b43legacy_dmaring *ring,
0140                   int current_used_slots)
0141 {
0142     if (current_used_slots <= ring->max_used_slots)
0143         return;
0144     ring->max_used_slots = current_used_slots;
0145     if (b43legacy_debug(ring->dev, B43legacy_DBG_DMAVERBOSE))
0146         b43legacydbg(ring->dev->wl,
0147                "max_used_slots increased to %d on %s ring %d\n",
0148                ring->max_used_slots,
0149                ring->tx ? "TX" : "RX",
0150                ring->index);
0151 }
0152 #else
0153 static inline
0154 void update_max_used_slots(struct b43legacy_dmaring *ring,
0155                int current_used_slots)
0156 { }
0157 #endif /* DEBUG */
0158 
0159 /* Request a slot for usage. */
0160 static inline
0161 int request_slot(struct b43legacy_dmaring *ring)
0162 {
0163     int slot;
0164 
0165     B43legacy_WARN_ON(!ring->tx);
0166     B43legacy_WARN_ON(ring->stopped);
0167     B43legacy_WARN_ON(free_slots(ring) == 0);
0168 
0169     slot = next_slot(ring, ring->current_slot);
0170     ring->current_slot = slot;
0171     ring->used_slots++;
0172 
0173     update_max_used_slots(ring, ring->used_slots);
0174 
0175     return slot;
0176 }
0177 
0178 /* Mac80211-queue to b43legacy-ring mapping */
0179 static struct b43legacy_dmaring *priority_to_txring(
0180                         struct b43legacy_wldev *dev,
0181                         int queue_priority)
0182 {
0183     struct b43legacy_dmaring *ring;
0184 
0185 /*FIXME: For now we always run on TX-ring-1 */
0186 return dev->dma.tx_ring1;
0187 
0188     /* 0 = highest priority */
0189     switch (queue_priority) {
0190     default:
0191         B43legacy_WARN_ON(1);
0192         fallthrough;
0193     case 0:
0194         ring = dev->dma.tx_ring3;
0195         break;
0196     case 1:
0197         ring = dev->dma.tx_ring2;
0198         break;
0199     case 2:
0200         ring = dev->dma.tx_ring1;
0201         break;
0202     case 3:
0203         ring = dev->dma.tx_ring0;
0204         break;
0205     case 4:
0206         ring = dev->dma.tx_ring4;
0207         break;
0208     case 5:
0209         ring = dev->dma.tx_ring5;
0210         break;
0211     }
0212 
0213     return ring;
0214 }
0215 
0216 static u16 b43legacy_dmacontroller_base(enum b43legacy_dmatype type,
0217                     int controller_idx)
0218 {
0219     static const u16 map32[] = {
0220         B43legacy_MMIO_DMA32_BASE0,
0221         B43legacy_MMIO_DMA32_BASE1,
0222         B43legacy_MMIO_DMA32_BASE2,
0223         B43legacy_MMIO_DMA32_BASE3,
0224         B43legacy_MMIO_DMA32_BASE4,
0225         B43legacy_MMIO_DMA32_BASE5,
0226     };
0227 
0228     B43legacy_WARN_ON(!(controller_idx >= 0 &&
0229               controller_idx < ARRAY_SIZE(map32)));
0230     return map32[controller_idx];
0231 }
0232 
0233 static inline
0234 dma_addr_t map_descbuffer(struct b43legacy_dmaring *ring,
0235               unsigned char *buf,
0236               size_t len,
0237               int tx)
0238 {
0239     dma_addr_t dmaaddr;
0240 
0241     if (tx)
0242         dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
0243                          buf, len,
0244                          DMA_TO_DEVICE);
0245     else
0246         dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
0247                          buf, len,
0248                          DMA_FROM_DEVICE);
0249 
0250     return dmaaddr;
0251 }
0252 
0253 static inline
0254 void unmap_descbuffer(struct b43legacy_dmaring *ring,
0255               dma_addr_t addr,
0256               size_t len,
0257               int tx)
0258 {
0259     if (tx)
0260         dma_unmap_single(ring->dev->dev->dma_dev,
0261                      addr, len,
0262                      DMA_TO_DEVICE);
0263     else
0264         dma_unmap_single(ring->dev->dev->dma_dev,
0265                      addr, len,
0266                      DMA_FROM_DEVICE);
0267 }
0268 
0269 static inline
0270 void sync_descbuffer_for_cpu(struct b43legacy_dmaring *ring,
0271                  dma_addr_t addr,
0272                  size_t len)
0273 {
0274     B43legacy_WARN_ON(ring->tx);
0275 
0276     dma_sync_single_for_cpu(ring->dev->dev->dma_dev,
0277                 addr, len, DMA_FROM_DEVICE);
0278 }
0279 
0280 static inline
0281 void sync_descbuffer_for_device(struct b43legacy_dmaring *ring,
0282                 dma_addr_t addr,
0283                 size_t len)
0284 {
0285     B43legacy_WARN_ON(ring->tx);
0286 
0287     dma_sync_single_for_device(ring->dev->dev->dma_dev,
0288                    addr, len, DMA_FROM_DEVICE);
0289 }
0290 
0291 static inline
0292 void free_descriptor_buffer(struct b43legacy_dmaring *ring,
0293                 struct b43legacy_dmadesc_meta *meta,
0294                 int irq_context)
0295 {
0296     if (meta->skb) {
0297         if (irq_context)
0298             dev_kfree_skb_irq(meta->skb);
0299         else
0300             dev_kfree_skb(meta->skb);
0301         meta->skb = NULL;
0302     }
0303 }
0304 
0305 static int alloc_ringmemory(struct b43legacy_dmaring *ring)
0306 {
0307     /* GFP flags must match the flags in free_ringmemory()! */
0308     ring->descbase = dma_alloc_coherent(ring->dev->dev->dma_dev,
0309                         B43legacy_DMA_RINGMEMSIZE,
0310                         &(ring->dmabase), GFP_KERNEL);
0311     if (!ring->descbase)
0312         return -ENOMEM;
0313 
0314     return 0;
0315 }
0316 
0317 static void free_ringmemory(struct b43legacy_dmaring *ring)
0318 {
0319     dma_free_coherent(ring->dev->dev->dma_dev, B43legacy_DMA_RINGMEMSIZE,
0320               ring->descbase, ring->dmabase);
0321 }
0322 
0323 /* Reset the RX DMA channel */
0324 static int b43legacy_dmacontroller_rx_reset(struct b43legacy_wldev *dev,
0325                         u16 mmio_base,
0326                         enum b43legacy_dmatype type)
0327 {
0328     int i;
0329     u32 value;
0330     u16 offset;
0331 
0332     might_sleep();
0333 
0334     offset = B43legacy_DMA32_RXCTL;
0335     b43legacy_write32(dev, mmio_base + offset, 0);
0336     for (i = 0; i < 10; i++) {
0337         offset = B43legacy_DMA32_RXSTATUS;
0338         value = b43legacy_read32(dev, mmio_base + offset);
0339         value &= B43legacy_DMA32_RXSTATE;
0340         if (value == B43legacy_DMA32_RXSTAT_DISABLED) {
0341             i = -1;
0342             break;
0343         }
0344         msleep(1);
0345     }
0346     if (i != -1) {
0347         b43legacyerr(dev->wl, "DMA RX reset timed out\n");
0348         return -ENODEV;
0349     }
0350 
0351     return 0;
0352 }
0353 
0354 /* Reset the RX DMA channel */
0355 static int b43legacy_dmacontroller_tx_reset(struct b43legacy_wldev *dev,
0356                         u16 mmio_base,
0357                         enum b43legacy_dmatype type)
0358 {
0359     int i;
0360     u32 value;
0361     u16 offset;
0362 
0363     might_sleep();
0364 
0365     for (i = 0; i < 10; i++) {
0366         offset = B43legacy_DMA32_TXSTATUS;
0367         value = b43legacy_read32(dev, mmio_base + offset);
0368         value &= B43legacy_DMA32_TXSTATE;
0369         if (value == B43legacy_DMA32_TXSTAT_DISABLED ||
0370             value == B43legacy_DMA32_TXSTAT_IDLEWAIT ||
0371             value == B43legacy_DMA32_TXSTAT_STOPPED)
0372             break;
0373         msleep(1);
0374     }
0375     offset = B43legacy_DMA32_TXCTL;
0376     b43legacy_write32(dev, mmio_base + offset, 0);
0377     for (i = 0; i < 10; i++) {
0378         offset = B43legacy_DMA32_TXSTATUS;
0379         value = b43legacy_read32(dev, mmio_base + offset);
0380         value &= B43legacy_DMA32_TXSTATE;
0381         if (value == B43legacy_DMA32_TXSTAT_DISABLED) {
0382             i = -1;
0383             break;
0384         }
0385         msleep(1);
0386     }
0387     if (i != -1) {
0388         b43legacyerr(dev->wl, "DMA TX reset timed out\n");
0389         return -ENODEV;
0390     }
0391     /* ensure the reset is completed. */
0392     msleep(1);
0393 
0394     return 0;
0395 }
0396 
0397 /* Check if a DMA mapping address is invalid. */
0398 static bool b43legacy_dma_mapping_error(struct b43legacy_dmaring *ring,
0399                      dma_addr_t addr,
0400                      size_t buffersize,
0401                      bool dma_to_device)
0402 {
0403     if (unlikely(dma_mapping_error(ring->dev->dev->dma_dev, addr)))
0404         return true;
0405 
0406     switch (ring->type) {
0407     case B43legacy_DMA_30BIT:
0408         if ((u64)addr + buffersize > (1ULL << 30))
0409             goto address_error;
0410         break;
0411     case B43legacy_DMA_32BIT:
0412         if ((u64)addr + buffersize > (1ULL << 32))
0413             goto address_error;
0414         break;
0415     }
0416 
0417     /* The address is OK. */
0418     return false;
0419 
0420 address_error:
0421     /* We can't support this address. Unmap it again. */
0422     unmap_descbuffer(ring, addr, buffersize, dma_to_device);
0423 
0424     return true;
0425 }
0426 
0427 static int setup_rx_descbuffer(struct b43legacy_dmaring *ring,
0428                    struct b43legacy_dmadesc32 *desc,
0429                    struct b43legacy_dmadesc_meta *meta,
0430                    gfp_t gfp_flags)
0431 {
0432     struct b43legacy_rxhdr_fw3 *rxhdr;
0433     struct b43legacy_hwtxstatus *txstat;
0434     dma_addr_t dmaaddr;
0435     struct sk_buff *skb;
0436 
0437     B43legacy_WARN_ON(ring->tx);
0438 
0439     skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
0440     if (unlikely(!skb))
0441         return -ENOMEM;
0442     dmaaddr = map_descbuffer(ring, skb->data,
0443                  ring->rx_buffersize, 0);
0444     if (b43legacy_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
0445         /* ugh. try to realloc in zone_dma */
0446         gfp_flags |= GFP_DMA;
0447 
0448         dev_kfree_skb_any(skb);
0449 
0450         skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
0451         if (unlikely(!skb))
0452             return -ENOMEM;
0453         dmaaddr = map_descbuffer(ring, skb->data,
0454                      ring->rx_buffersize, 0);
0455     }
0456 
0457     if (b43legacy_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
0458         dev_kfree_skb_any(skb);
0459         return -EIO;
0460     }
0461 
0462     meta->skb = skb;
0463     meta->dmaaddr = dmaaddr;
0464     op32_fill_descriptor(ring, desc, dmaaddr, ring->rx_buffersize, 0, 0, 0);
0465 
0466     rxhdr = (struct b43legacy_rxhdr_fw3 *)(skb->data);
0467     rxhdr->frame_len = 0;
0468     txstat = (struct b43legacy_hwtxstatus *)(skb->data);
0469     txstat->cookie = 0;
0470 
0471     return 0;
0472 }
0473 
0474 /* Allocate the initial descbuffers.
0475  * This is used for an RX ring only.
0476  */
0477 static int alloc_initial_descbuffers(struct b43legacy_dmaring *ring)
0478 {
0479     int i;
0480     int err = -ENOMEM;
0481     struct b43legacy_dmadesc32 *desc;
0482     struct b43legacy_dmadesc_meta *meta;
0483 
0484     for (i = 0; i < ring->nr_slots; i++) {
0485         desc = op32_idx2desc(ring, i, &meta);
0486 
0487         err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
0488         if (err) {
0489             b43legacyerr(ring->dev->wl,
0490                    "Failed to allocate initial descbuffers\n");
0491             goto err_unwind;
0492         }
0493     }
0494     mb(); /* all descbuffer setup before next line */
0495     ring->used_slots = ring->nr_slots;
0496     err = 0;
0497 out:
0498     return err;
0499 
0500 err_unwind:
0501     for (i--; i >= 0; i--) {
0502         desc = op32_idx2desc(ring, i, &meta);
0503 
0504         unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
0505         dev_kfree_skb(meta->skb);
0506     }
0507     goto out;
0508 }
0509 
0510 /* Do initial setup of the DMA controller.
0511  * Reset the controller, write the ring busaddress
0512  * and switch the "enable" bit on.
0513  */
0514 static int dmacontroller_setup(struct b43legacy_dmaring *ring)
0515 {
0516     int err = 0;
0517     u32 value;
0518     u32 addrext;
0519     u32 trans = ring->dev->dma.translation;
0520     u32 ringbase = (u32)(ring->dmabase);
0521 
0522     if (ring->tx) {
0523         addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
0524               >> SSB_DMA_TRANSLATION_SHIFT;
0525         value = B43legacy_DMA32_TXENABLE;
0526         value |= (addrext << B43legacy_DMA32_TXADDREXT_SHIFT)
0527             & B43legacy_DMA32_TXADDREXT_MASK;
0528         b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL, value);
0529         b43legacy_dma_write(ring, B43legacy_DMA32_TXRING,
0530                     (ringbase & ~SSB_DMA_TRANSLATION_MASK)
0531                     | trans);
0532     } else {
0533         err = alloc_initial_descbuffers(ring);
0534         if (err)
0535             goto out;
0536 
0537         addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
0538               >> SSB_DMA_TRANSLATION_SHIFT;
0539         value = (ring->frameoffset <<
0540              B43legacy_DMA32_RXFROFF_SHIFT);
0541         value |= B43legacy_DMA32_RXENABLE;
0542         value |= (addrext << B43legacy_DMA32_RXADDREXT_SHIFT)
0543              & B43legacy_DMA32_RXADDREXT_MASK;
0544         b43legacy_dma_write(ring, B43legacy_DMA32_RXCTL, value);
0545         b43legacy_dma_write(ring, B43legacy_DMA32_RXRING,
0546                     (ringbase & ~SSB_DMA_TRANSLATION_MASK)
0547                     | trans);
0548         b43legacy_dma_write(ring, B43legacy_DMA32_RXINDEX, 200);
0549     }
0550 
0551 out:
0552     return err;
0553 }
0554 
0555 /* Shutdown the DMA controller. */
0556 static void dmacontroller_cleanup(struct b43legacy_dmaring *ring)
0557 {
0558     if (ring->tx) {
0559         b43legacy_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
0560                          ring->type);
0561         b43legacy_dma_write(ring, B43legacy_DMA32_TXRING, 0);
0562     } else {
0563         b43legacy_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
0564                          ring->type);
0565         b43legacy_dma_write(ring, B43legacy_DMA32_RXRING, 0);
0566     }
0567 }
0568 
0569 static void free_all_descbuffers(struct b43legacy_dmaring *ring)
0570 {
0571     struct b43legacy_dmadesc_meta *meta;
0572     int i;
0573 
0574     if (!ring->used_slots)
0575         return;
0576     for (i = 0; i < ring->nr_slots; i++) {
0577         op32_idx2desc(ring, i, &meta);
0578 
0579         if (!meta->skb) {
0580             B43legacy_WARN_ON(!ring->tx);
0581             continue;
0582         }
0583         if (ring->tx)
0584             unmap_descbuffer(ring, meta->dmaaddr,
0585                      meta->skb->len, 1);
0586         else
0587             unmap_descbuffer(ring, meta->dmaaddr,
0588                      ring->rx_buffersize, 0);
0589         free_descriptor_buffer(ring, meta, 0);
0590     }
0591 }
0592 
0593 static enum b43legacy_dmatype b43legacy_engine_type(struct b43legacy_wldev *dev)
0594 {
0595     u32 tmp;
0596     u16 mmio_base;
0597 
0598     mmio_base = b43legacy_dmacontroller_base(0, 0);
0599     b43legacy_write32(dev,
0600             mmio_base + B43legacy_DMA32_TXCTL,
0601             B43legacy_DMA32_TXADDREXT_MASK);
0602     tmp = b43legacy_read32(dev, mmio_base +
0603                    B43legacy_DMA32_TXCTL);
0604     if (tmp & B43legacy_DMA32_TXADDREXT_MASK)
0605         return B43legacy_DMA_32BIT;
0606     return B43legacy_DMA_30BIT;
0607 }
0608 
0609 /* Main initialization function. */
0610 static
0611 struct b43legacy_dmaring *b43legacy_setup_dmaring(struct b43legacy_wldev *dev,
0612                           int controller_index,
0613                           int for_tx,
0614                           enum b43legacy_dmatype type)
0615 {
0616     struct b43legacy_dmaring *ring;
0617     int err;
0618     int nr_slots;
0619     dma_addr_t dma_test;
0620 
0621     ring = kzalloc(sizeof(*ring), GFP_KERNEL);
0622     if (!ring)
0623         goto out;
0624     ring->type = type;
0625     ring->dev = dev;
0626 
0627     nr_slots = B43legacy_RXRING_SLOTS;
0628     if (for_tx)
0629         nr_slots = B43legacy_TXRING_SLOTS;
0630 
0631     ring->meta = kcalloc(nr_slots, sizeof(struct b43legacy_dmadesc_meta),
0632                  GFP_KERNEL);
0633     if (!ring->meta)
0634         goto err_kfree_ring;
0635     if (for_tx) {
0636         ring->txhdr_cache = kcalloc(nr_slots,
0637                     sizeof(struct b43legacy_txhdr_fw3),
0638                     GFP_KERNEL);
0639         if (!ring->txhdr_cache)
0640             goto err_kfree_meta;
0641 
0642         /* test for ability to dma to txhdr_cache */
0643         dma_test = dma_map_single(dev->dev->dma_dev, ring->txhdr_cache,
0644                           sizeof(struct b43legacy_txhdr_fw3),
0645                           DMA_TO_DEVICE);
0646 
0647         if (b43legacy_dma_mapping_error(ring, dma_test,
0648                     sizeof(struct b43legacy_txhdr_fw3), 1)) {
0649             /* ugh realloc */
0650             kfree(ring->txhdr_cache);
0651             ring->txhdr_cache = kcalloc(nr_slots,
0652                     sizeof(struct b43legacy_txhdr_fw3),
0653                     GFP_KERNEL | GFP_DMA);
0654             if (!ring->txhdr_cache)
0655                 goto err_kfree_meta;
0656 
0657             dma_test = dma_map_single(dev->dev->dma_dev,
0658                     ring->txhdr_cache,
0659                     sizeof(struct b43legacy_txhdr_fw3),
0660                     DMA_TO_DEVICE);
0661 
0662             if (b43legacy_dma_mapping_error(ring, dma_test,
0663                     sizeof(struct b43legacy_txhdr_fw3), 1))
0664                 goto err_kfree_txhdr_cache;
0665         }
0666 
0667         dma_unmap_single(dev->dev->dma_dev, dma_test,
0668                  sizeof(struct b43legacy_txhdr_fw3),
0669                  DMA_TO_DEVICE);
0670     }
0671 
0672     ring->nr_slots = nr_slots;
0673     ring->mmio_base = b43legacy_dmacontroller_base(type, controller_index);
0674     ring->index = controller_index;
0675     if (for_tx) {
0676         ring->tx = true;
0677         ring->current_slot = -1;
0678     } else {
0679         if (ring->index == 0) {
0680             ring->rx_buffersize = B43legacy_DMA0_RX_BUFFERSIZE;
0681             ring->frameoffset = B43legacy_DMA0_RX_FRAMEOFFSET;
0682         } else if (ring->index == 3) {
0683             ring->rx_buffersize = B43legacy_DMA3_RX_BUFFERSIZE;
0684             ring->frameoffset = B43legacy_DMA3_RX_FRAMEOFFSET;
0685         } else
0686             B43legacy_WARN_ON(1);
0687     }
0688 #ifdef CONFIG_B43LEGACY_DEBUG
0689     ring->last_injected_overflow = jiffies;
0690 #endif
0691 
0692     err = alloc_ringmemory(ring);
0693     if (err)
0694         goto err_kfree_txhdr_cache;
0695     err = dmacontroller_setup(ring);
0696     if (err)
0697         goto err_free_ringmemory;
0698 
0699 out:
0700     return ring;
0701 
0702 err_free_ringmemory:
0703     free_ringmemory(ring);
0704 err_kfree_txhdr_cache:
0705     kfree(ring->txhdr_cache);
0706 err_kfree_meta:
0707     kfree(ring->meta);
0708 err_kfree_ring:
0709     kfree(ring);
0710     ring = NULL;
0711     goto out;
0712 }
0713 
0714 /* Main cleanup function. */
0715 static void b43legacy_destroy_dmaring(struct b43legacy_dmaring *ring)
0716 {
0717     if (!ring)
0718         return;
0719 
0720     b43legacydbg(ring->dev->wl, "DMA-%u 0x%04X (%s) max used slots:"
0721              " %d/%d\n", (unsigned int)(ring->type), ring->mmio_base,
0722              (ring->tx) ? "TX" : "RX", ring->max_used_slots,
0723              ring->nr_slots);
0724     /* Device IRQs are disabled prior entering this function,
0725      * so no need to take care of concurrency with rx handler stuff.
0726      */
0727     dmacontroller_cleanup(ring);
0728     free_all_descbuffers(ring);
0729     free_ringmemory(ring);
0730 
0731     kfree(ring->txhdr_cache);
0732     kfree(ring->meta);
0733     kfree(ring);
0734 }
0735 
0736 void b43legacy_dma_free(struct b43legacy_wldev *dev)
0737 {
0738     struct b43legacy_dma *dma;
0739 
0740     if (b43legacy_using_pio(dev))
0741         return;
0742     dma = &dev->dma;
0743 
0744     b43legacy_destroy_dmaring(dma->rx_ring3);
0745     dma->rx_ring3 = NULL;
0746     b43legacy_destroy_dmaring(dma->rx_ring0);
0747     dma->rx_ring0 = NULL;
0748 
0749     b43legacy_destroy_dmaring(dma->tx_ring5);
0750     dma->tx_ring5 = NULL;
0751     b43legacy_destroy_dmaring(dma->tx_ring4);
0752     dma->tx_ring4 = NULL;
0753     b43legacy_destroy_dmaring(dma->tx_ring3);
0754     dma->tx_ring3 = NULL;
0755     b43legacy_destroy_dmaring(dma->tx_ring2);
0756     dma->tx_ring2 = NULL;
0757     b43legacy_destroy_dmaring(dma->tx_ring1);
0758     dma->tx_ring1 = NULL;
0759     b43legacy_destroy_dmaring(dma->tx_ring0);
0760     dma->tx_ring0 = NULL;
0761 }
0762 
0763 int b43legacy_dma_init(struct b43legacy_wldev *dev)
0764 {
0765     struct b43legacy_dma *dma = &dev->dma;
0766     struct b43legacy_dmaring *ring;
0767     enum b43legacy_dmatype type = b43legacy_engine_type(dev);
0768     int err;
0769 
0770     err = dma_set_mask_and_coherent(dev->dev->dma_dev, DMA_BIT_MASK(type));
0771     if (err) {
0772 #ifdef CONFIG_B43LEGACY_PIO
0773         b43legacywarn(dev->wl, "DMA for this device not supported. "
0774             "Falling back to PIO\n");
0775         dev->__using_pio = true;
0776         return -EAGAIN;
0777 #else
0778         b43legacyerr(dev->wl, "DMA for this device not supported and "
0779                "no PIO support compiled in\n");
0780         return -EOPNOTSUPP;
0781 #endif
0782     }
0783     dma->translation = ssb_dma_translation(dev->dev);
0784 
0785     err = -ENOMEM;
0786     /* setup TX DMA channels. */
0787     ring = b43legacy_setup_dmaring(dev, 0, 1, type);
0788     if (!ring)
0789         goto out;
0790     dma->tx_ring0 = ring;
0791 
0792     ring = b43legacy_setup_dmaring(dev, 1, 1, type);
0793     if (!ring)
0794         goto err_destroy_tx0;
0795     dma->tx_ring1 = ring;
0796 
0797     ring = b43legacy_setup_dmaring(dev, 2, 1, type);
0798     if (!ring)
0799         goto err_destroy_tx1;
0800     dma->tx_ring2 = ring;
0801 
0802     ring = b43legacy_setup_dmaring(dev, 3, 1, type);
0803     if (!ring)
0804         goto err_destroy_tx2;
0805     dma->tx_ring3 = ring;
0806 
0807     ring = b43legacy_setup_dmaring(dev, 4, 1, type);
0808     if (!ring)
0809         goto err_destroy_tx3;
0810     dma->tx_ring4 = ring;
0811 
0812     ring = b43legacy_setup_dmaring(dev, 5, 1, type);
0813     if (!ring)
0814         goto err_destroy_tx4;
0815     dma->tx_ring5 = ring;
0816 
0817     /* setup RX DMA channels. */
0818     ring = b43legacy_setup_dmaring(dev, 0, 0, type);
0819     if (!ring)
0820         goto err_destroy_tx5;
0821     dma->rx_ring0 = ring;
0822 
0823     if (dev->dev->id.revision < 5) {
0824         ring = b43legacy_setup_dmaring(dev, 3, 0, type);
0825         if (!ring)
0826             goto err_destroy_rx0;
0827         dma->rx_ring3 = ring;
0828     }
0829 
0830     b43legacydbg(dev->wl, "%u-bit DMA initialized\n", (unsigned int)type);
0831     err = 0;
0832 out:
0833     return err;
0834 
0835 err_destroy_rx0:
0836     b43legacy_destroy_dmaring(dma->rx_ring0);
0837     dma->rx_ring0 = NULL;
0838 err_destroy_tx5:
0839     b43legacy_destroy_dmaring(dma->tx_ring5);
0840     dma->tx_ring5 = NULL;
0841 err_destroy_tx4:
0842     b43legacy_destroy_dmaring(dma->tx_ring4);
0843     dma->tx_ring4 = NULL;
0844 err_destroy_tx3:
0845     b43legacy_destroy_dmaring(dma->tx_ring3);
0846     dma->tx_ring3 = NULL;
0847 err_destroy_tx2:
0848     b43legacy_destroy_dmaring(dma->tx_ring2);
0849     dma->tx_ring2 = NULL;
0850 err_destroy_tx1:
0851     b43legacy_destroy_dmaring(dma->tx_ring1);
0852     dma->tx_ring1 = NULL;
0853 err_destroy_tx0:
0854     b43legacy_destroy_dmaring(dma->tx_ring0);
0855     dma->tx_ring0 = NULL;
0856     goto out;
0857 }
0858 
0859 /* Generate a cookie for the TX header. */
0860 static u16 generate_cookie(struct b43legacy_dmaring *ring,
0861                int slot)
0862 {
0863     u16 cookie = 0x1000;
0864 
0865     /* Use the upper 4 bits of the cookie as
0866      * DMA controller ID and store the slot number
0867      * in the lower 12 bits.
0868      * Note that the cookie must never be 0, as this
0869      * is a special value used in RX path.
0870      */
0871     switch (ring->index) {
0872     case 0:
0873         cookie = 0xA000;
0874         break;
0875     case 1:
0876         cookie = 0xB000;
0877         break;
0878     case 2:
0879         cookie = 0xC000;
0880         break;
0881     case 3:
0882         cookie = 0xD000;
0883         break;
0884     case 4:
0885         cookie = 0xE000;
0886         break;
0887     case 5:
0888         cookie = 0xF000;
0889         break;
0890     }
0891     B43legacy_WARN_ON(!(((u16)slot & 0xF000) == 0x0000));
0892     cookie |= (u16)slot;
0893 
0894     return cookie;
0895 }
0896 
0897 /* Inspect a cookie and find out to which controller/slot it belongs. */
0898 static
0899 struct b43legacy_dmaring *parse_cookie(struct b43legacy_wldev *dev,
0900                       u16 cookie, int *slot)
0901 {
0902     struct b43legacy_dma *dma = &dev->dma;
0903     struct b43legacy_dmaring *ring = NULL;
0904 
0905     switch (cookie & 0xF000) {
0906     case 0xA000:
0907         ring = dma->tx_ring0;
0908         break;
0909     case 0xB000:
0910         ring = dma->tx_ring1;
0911         break;
0912     case 0xC000:
0913         ring = dma->tx_ring2;
0914         break;
0915     case 0xD000:
0916         ring = dma->tx_ring3;
0917         break;
0918     case 0xE000:
0919         ring = dma->tx_ring4;
0920         break;
0921     case 0xF000:
0922         ring = dma->tx_ring5;
0923         break;
0924     default:
0925         B43legacy_WARN_ON(1);
0926     }
0927     *slot = (cookie & 0x0FFF);
0928     B43legacy_WARN_ON(!(ring && *slot >= 0 && *slot < ring->nr_slots));
0929 
0930     return ring;
0931 }
0932 
0933 static int dma_tx_fragment(struct b43legacy_dmaring *ring,
0934                 struct sk_buff **in_skb)
0935 {
0936     struct sk_buff *skb = *in_skb;
0937     struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
0938     u8 *header;
0939     int slot, old_top_slot, old_used_slots;
0940     int err;
0941     struct b43legacy_dmadesc32 *desc;
0942     struct b43legacy_dmadesc_meta *meta;
0943     struct b43legacy_dmadesc_meta *meta_hdr;
0944     struct sk_buff *bounce_skb;
0945 
0946 #define SLOTS_PER_PACKET  2
0947     B43legacy_WARN_ON(skb_shinfo(skb)->nr_frags != 0);
0948 
0949     old_top_slot = ring->current_slot;
0950     old_used_slots = ring->used_slots;
0951 
0952     /* Get a slot for the header. */
0953     slot = request_slot(ring);
0954     desc = op32_idx2desc(ring, slot, &meta_hdr);
0955     memset(meta_hdr, 0, sizeof(*meta_hdr));
0956 
0957     header = &(ring->txhdr_cache[slot * sizeof(
0958                    struct b43legacy_txhdr_fw3)]);
0959     err = b43legacy_generate_txhdr(ring->dev, header,
0960                  skb->data, skb->len, info,
0961                  generate_cookie(ring, slot));
0962     if (unlikely(err)) {
0963         ring->current_slot = old_top_slot;
0964         ring->used_slots = old_used_slots;
0965         return err;
0966     }
0967 
0968     meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
0969                        sizeof(struct b43legacy_txhdr_fw3), 1);
0970     if (b43legacy_dma_mapping_error(ring, meta_hdr->dmaaddr,
0971                     sizeof(struct b43legacy_txhdr_fw3), 1)) {
0972         ring->current_slot = old_top_slot;
0973         ring->used_slots = old_used_slots;
0974         return -EIO;
0975     }
0976     op32_fill_descriptor(ring, desc, meta_hdr->dmaaddr,
0977                  sizeof(struct b43legacy_txhdr_fw3), 1, 0, 0);
0978 
0979     /* Get a slot for the payload. */
0980     slot = request_slot(ring);
0981     desc = op32_idx2desc(ring, slot, &meta);
0982     memset(meta, 0, sizeof(*meta));
0983 
0984     meta->skb = skb;
0985     meta->is_last_fragment = true;
0986 
0987     meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
0988     /* create a bounce buffer in zone_dma on mapping failure. */
0989     if (b43legacy_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
0990         bounce_skb = alloc_skb(skb->len, GFP_KERNEL | GFP_DMA);
0991         if (!bounce_skb) {
0992             ring->current_slot = old_top_slot;
0993             ring->used_slots = old_used_slots;
0994             err = -ENOMEM;
0995             goto out_unmap_hdr;
0996         }
0997 
0998         skb_put_data(bounce_skb, skb->data, skb->len);
0999         memcpy(bounce_skb->cb, skb->cb, sizeof(skb->cb));
1000         bounce_skb->dev = skb->dev;
1001         skb_set_queue_mapping(bounce_skb, skb_get_queue_mapping(skb));
1002         info = IEEE80211_SKB_CB(bounce_skb);
1003 
1004         dev_kfree_skb_any(skb);
1005         skb = bounce_skb;
1006         *in_skb = bounce_skb;
1007         meta->skb = skb;
1008         meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1009         if (b43legacy_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1010             ring->current_slot = old_top_slot;
1011             ring->used_slots = old_used_slots;
1012             err = -EIO;
1013             goto out_free_bounce;
1014         }
1015     }
1016 
1017     op32_fill_descriptor(ring, desc, meta->dmaaddr,
1018                  skb->len, 0, 1, 1);
1019 
1020     wmb();  /* previous stuff MUST be done */
1021     /* Now transfer the whole frame. */
1022     op32_poke_tx(ring, next_slot(ring, slot));
1023     return 0;
1024 
1025 out_free_bounce:
1026     dev_kfree_skb_any(skb);
1027 out_unmap_hdr:
1028     unmap_descbuffer(ring, meta_hdr->dmaaddr,
1029              sizeof(struct b43legacy_txhdr_fw3), 1);
1030     return err;
1031 }
1032 
1033 static inline
1034 int should_inject_overflow(struct b43legacy_dmaring *ring)
1035 {
1036 #ifdef CONFIG_B43LEGACY_DEBUG
1037     if (unlikely(b43legacy_debug(ring->dev,
1038                      B43legacy_DBG_DMAOVERFLOW))) {
1039         /* Check if we should inject another ringbuffer overflow
1040          * to test handling of this situation in the stack. */
1041         unsigned long next_overflow;
1042 
1043         next_overflow = ring->last_injected_overflow + HZ;
1044         if (time_after(jiffies, next_overflow)) {
1045             ring->last_injected_overflow = jiffies;
1046             b43legacydbg(ring->dev->wl,
1047                    "Injecting TX ring overflow on "
1048                    "DMA controller %d\n", ring->index);
1049             return 1;
1050         }
1051     }
1052 #endif /* CONFIG_B43LEGACY_DEBUG */
1053     return 0;
1054 }
1055 
1056 int b43legacy_dma_tx(struct b43legacy_wldev *dev,
1057              struct sk_buff *skb)
1058 {
1059     struct b43legacy_dmaring *ring;
1060     int err = 0;
1061 
1062     ring = priority_to_txring(dev, skb_get_queue_mapping(skb));
1063     B43legacy_WARN_ON(!ring->tx);
1064 
1065     if (unlikely(ring->stopped)) {
1066         /* We get here only because of a bug in mac80211.
1067          * Because of a race, one packet may be queued after
1068          * the queue is stopped, thus we got called when we shouldn't.
1069          * For now, just refuse the transmit. */
1070         if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE))
1071             b43legacyerr(dev->wl, "Packet after queue stopped\n");
1072         return -ENOSPC;
1073     }
1074 
1075     if (WARN_ON(free_slots(ring) < SLOTS_PER_PACKET)) {
1076         /* If we get here, we have a real error with the queue
1077          * full, but queues not stopped. */
1078         b43legacyerr(dev->wl, "DMA queue overflow\n");
1079         return -ENOSPC;
1080     }
1081 
1082     /* dma_tx_fragment might reallocate the skb, so invalidate pointers pointing
1083      * into the skb data or cb now. */
1084     err = dma_tx_fragment(ring, &skb);
1085     if (unlikely(err == -ENOKEY)) {
1086         /* Drop this packet, as we don't have the encryption key
1087          * anymore and must not transmit it unencrypted. */
1088         dev_kfree_skb_any(skb);
1089         return 0;
1090     }
1091     if (unlikely(err)) {
1092         b43legacyerr(dev->wl, "DMA tx mapping failure\n");
1093         return err;
1094     }
1095     if ((free_slots(ring) < SLOTS_PER_PACKET) ||
1096         should_inject_overflow(ring)) {
1097         /* This TX ring is full. */
1098         unsigned int skb_mapping = skb_get_queue_mapping(skb);
1099         ieee80211_stop_queue(dev->wl->hw, skb_mapping);
1100         dev->wl->tx_queue_stopped[skb_mapping] = 1;
1101         ring->stopped = true;
1102         if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE))
1103             b43legacydbg(dev->wl, "Stopped TX ring %d\n",
1104                    ring->index);
1105     }
1106     return err;
1107 }
1108 
1109 void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev,
1110                  const struct b43legacy_txstatus *status)
1111 {
1112     struct b43legacy_dmaring *ring;
1113     struct b43legacy_dmadesc_meta *meta;
1114     int retry_limit;
1115     int slot;
1116     int firstused;
1117 
1118     ring = parse_cookie(dev, status->cookie, &slot);
1119     if (unlikely(!ring))
1120         return;
1121     B43legacy_WARN_ON(!ring->tx);
1122 
1123     /* Sanity check: TX packets are processed in-order on one ring.
1124      * Check if the slot deduced from the cookie really is the first
1125      * used slot. */
1126     firstused = ring->current_slot - ring->used_slots + 1;
1127     if (firstused < 0)
1128         firstused = ring->nr_slots + firstused;
1129     if (unlikely(slot != firstused)) {
1130         /* This possibly is a firmware bug and will result in
1131          * malfunction, memory leaks and/or stall of DMA functionality.
1132          */
1133         b43legacydbg(dev->wl, "Out of order TX status report on DMA "
1134                  "ring %d. Expected %d, but got %d\n",
1135                  ring->index, firstused, slot);
1136         return;
1137     }
1138 
1139     while (1) {
1140         B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
1141         op32_idx2desc(ring, slot, &meta);
1142 
1143         if (meta->skb)
1144             unmap_descbuffer(ring, meta->dmaaddr,
1145                      meta->skb->len, 1);
1146         else
1147             unmap_descbuffer(ring, meta->dmaaddr,
1148                      sizeof(struct b43legacy_txhdr_fw3),
1149                      1);
1150 
1151         if (meta->is_last_fragment) {
1152             struct ieee80211_tx_info *info;
1153             BUG_ON(!meta->skb);
1154             info = IEEE80211_SKB_CB(meta->skb);
1155 
1156             /* preserve the confiured retry limit before clearing the status
1157              * The xmit function has overwritten the rc's value with the actual
1158              * retry limit done by the hardware */
1159             retry_limit = info->status.rates[0].count;
1160             ieee80211_tx_info_clear_status(info);
1161 
1162             if (status->acked)
1163                 info->flags |= IEEE80211_TX_STAT_ACK;
1164 
1165             if (status->rts_count > dev->wl->hw->conf.short_frame_max_tx_count) {
1166                 /*
1167                  * If the short retries (RTS, not data frame) have exceeded
1168                  * the limit, the hw will not have tried the selected rate,
1169                  * but will have used the fallback rate instead.
1170                  * Don't let the rate control count attempts for the selected
1171                  * rate in this case, otherwise the statistics will be off.
1172                  */
1173                 info->status.rates[0].count = 0;
1174                 info->status.rates[1].count = status->frame_count;
1175             } else {
1176                 if (status->frame_count > retry_limit) {
1177                     info->status.rates[0].count = retry_limit;
1178                     info->status.rates[1].count = status->frame_count -
1179                             retry_limit;
1180 
1181                 } else {
1182                     info->status.rates[0].count = status->frame_count;
1183                     info->status.rates[1].idx = -1;
1184                 }
1185             }
1186 
1187             /* Call back to inform the ieee80211 subsystem about the
1188              * status of the transmission.
1189              * Some fields of txstat are already filled in dma_tx().
1190              */
1191             ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb);
1192             /* skb is freed by ieee80211_tx_status_irqsafe() */
1193             meta->skb = NULL;
1194         } else {
1195             /* No need to call free_descriptor_buffer here, as
1196              * this is only the txhdr, which is not allocated.
1197              */
1198             B43legacy_WARN_ON(meta->skb != NULL);
1199         }
1200 
1201         /* Everything unmapped and free'd. So it's not used anymore. */
1202         ring->used_slots--;
1203 
1204         if (meta->is_last_fragment)
1205             break;
1206         slot = next_slot(ring, slot);
1207     }
1208     dev->stats.last_tx = jiffies;
1209     if (ring->stopped) {
1210         B43legacy_WARN_ON(free_slots(ring) < SLOTS_PER_PACKET);
1211         ring->stopped = false;
1212     }
1213 
1214     if (dev->wl->tx_queue_stopped[ring->queue_prio]) {
1215         dev->wl->tx_queue_stopped[ring->queue_prio] = 0;
1216     } else {
1217         /* If the driver queue is running wake the corresponding
1218          * mac80211 queue. */
1219         ieee80211_wake_queue(dev->wl->hw, ring->queue_prio);
1220         if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE))
1221             b43legacydbg(dev->wl, "Woke up TX ring %d\n",
1222                      ring->index);
1223     }
1224     /* Add work to the queue. */
1225     ieee80211_queue_work(dev->wl->hw, &dev->wl->tx_work);
1226 }
1227 
1228 static void dma_rx(struct b43legacy_dmaring *ring,
1229            int *slot)
1230 {
1231     struct b43legacy_dmadesc32 *desc;
1232     struct b43legacy_dmadesc_meta *meta;
1233     struct b43legacy_rxhdr_fw3 *rxhdr;
1234     struct sk_buff *skb;
1235     u16 len;
1236     int err;
1237     dma_addr_t dmaaddr;
1238 
1239     desc = op32_idx2desc(ring, *slot, &meta);
1240 
1241     sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1242     skb = meta->skb;
1243 
1244     if (ring->index == 3) {
1245         /* We received an xmit status. */
1246         struct b43legacy_hwtxstatus *hw =
1247                 (struct b43legacy_hwtxstatus *)skb->data;
1248         int i = 0;
1249 
1250         while (hw->cookie == 0) {
1251             if (i > 100)
1252                 break;
1253             i++;
1254             udelay(2);
1255             barrier();
1256         }
1257         b43legacy_handle_hwtxstatus(ring->dev, hw);
1258         /* recycle the descriptor buffer. */
1259         sync_descbuffer_for_device(ring, meta->dmaaddr,
1260                        ring->rx_buffersize);
1261 
1262         return;
1263     }
1264     rxhdr = (struct b43legacy_rxhdr_fw3 *)skb->data;
1265     len = le16_to_cpu(rxhdr->frame_len);
1266     if (len == 0) {
1267         int i = 0;
1268 
1269         do {
1270             udelay(2);
1271             barrier();
1272             len = le16_to_cpu(rxhdr->frame_len);
1273         } while (len == 0 && i++ < 5);
1274         if (unlikely(len == 0)) {
1275             /* recycle the descriptor buffer. */
1276             sync_descbuffer_for_device(ring, meta->dmaaddr,
1277                            ring->rx_buffersize);
1278             goto drop;
1279         }
1280     }
1281     if (unlikely(len > ring->rx_buffersize)) {
1282         /* The data did not fit into one descriptor buffer
1283          * and is split over multiple buffers.
1284          * This should never happen, as we try to allocate buffers
1285          * big enough. So simply ignore this packet.
1286          */
1287         int cnt = 0;
1288         s32 tmp = len;
1289 
1290         while (1) {
1291             desc = op32_idx2desc(ring, *slot, &meta);
1292             /* recycle the descriptor buffer. */
1293             sync_descbuffer_for_device(ring, meta->dmaaddr,
1294                            ring->rx_buffersize);
1295             *slot = next_slot(ring, *slot);
1296             cnt++;
1297             tmp -= ring->rx_buffersize;
1298             if (tmp <= 0)
1299                 break;
1300         }
1301         b43legacyerr(ring->dev->wl, "DMA RX buffer too small "
1302                "(len: %u, buffer: %u, nr-dropped: %d)\n",
1303                len, ring->rx_buffersize, cnt);
1304         goto drop;
1305     }
1306 
1307     dmaaddr = meta->dmaaddr;
1308     err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1309     if (unlikely(err)) {
1310         b43legacydbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer()"
1311                  " failed\n");
1312         sync_descbuffer_for_device(ring, dmaaddr,
1313                        ring->rx_buffersize);
1314         goto drop;
1315     }
1316 
1317     unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1318     skb_put(skb, len + ring->frameoffset);
1319     skb_pull(skb, ring->frameoffset);
1320 
1321     b43legacy_rx(ring->dev, skb, rxhdr);
1322 drop:
1323     return;
1324 }
1325 
1326 void b43legacy_dma_rx(struct b43legacy_dmaring *ring)
1327 {
1328     int slot;
1329     int current_slot;
1330     int used_slots = 0;
1331 
1332     B43legacy_WARN_ON(ring->tx);
1333     current_slot = op32_get_current_rxslot(ring);
1334     B43legacy_WARN_ON(!(current_slot >= 0 && current_slot <
1335                ring->nr_slots));
1336 
1337     slot = ring->current_slot;
1338     for (; slot != current_slot; slot = next_slot(ring, slot)) {
1339         dma_rx(ring, &slot);
1340         update_max_used_slots(ring, ++used_slots);
1341     }
1342     op32_set_current_rxslot(ring, slot);
1343     ring->current_slot = slot;
1344 }
1345 
1346 static void b43legacy_dma_tx_suspend_ring(struct b43legacy_dmaring *ring)
1347 {
1348     B43legacy_WARN_ON(!ring->tx);
1349     op32_tx_suspend(ring);
1350 }
1351 
1352 static void b43legacy_dma_tx_resume_ring(struct b43legacy_dmaring *ring)
1353 {
1354     B43legacy_WARN_ON(!ring->tx);
1355     op32_tx_resume(ring);
1356 }
1357 
1358 void b43legacy_dma_tx_suspend(struct b43legacy_wldev *dev)
1359 {
1360     b43legacy_power_saving_ctl_bits(dev, -1, 1);
1361     b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring0);
1362     b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring1);
1363     b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring2);
1364     b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring3);
1365     b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring4);
1366     b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring5);
1367 }
1368 
1369 void b43legacy_dma_tx_resume(struct b43legacy_wldev *dev)
1370 {
1371     b43legacy_dma_tx_resume_ring(dev->dma.tx_ring5);
1372     b43legacy_dma_tx_resume_ring(dev->dma.tx_ring4);
1373     b43legacy_dma_tx_resume_ring(dev->dma.tx_ring3);
1374     b43legacy_dma_tx_resume_ring(dev->dma.tx_ring2);
1375     b43legacy_dma_tx_resume_ring(dev->dma.tx_ring1);
1376     b43legacy_dma_tx_resume_ring(dev->dma.tx_ring0);
1377     b43legacy_power_saving_ctl_bits(dev, -1, -1);
1378 }
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