broadcom/b43/xmit.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef B43_XMIT_H_
0003 #define B43_XMIT_H_
0004
0005 #include "main.h"
0006 #include <net/mac80211.h>
0007
0008
0009 #define _b43_declare_plcp_hdr(size) \
0010     struct b43_plcp_hdr##size {     \
0011         union {             \
0012             __le32 data;        \
0013             __u8 raw[size];     \
0014         } __packed; \
0015     } __packed
0016
0017 /* struct b43_plcp_hdr4 */
0018 _b43_declare_plcp_hdr(4);
0019 /* struct b43_plcp_hdr6 */
0020 _b43_declare_plcp_hdr(6);
0021
0022 #undef _b43_declare_plcp_hdr
0023
0024 /* TX header for v4 firmware */
0025 struct b43_txhdr {
0026     __le32 mac_ctl;         /* MAC TX control */
0027     __le16 mac_frame_ctl;       /* Copy of the FrameControl field */
0028     __le16 tx_fes_time_norm;    /* TX FES Time Normal */
0029     __le16 phy_ctl;         /* PHY TX control */
0030     __le16 phy_ctl1;        /* PHY TX control word 1 */
0031     __le16 phy_ctl1_fb;     /* PHY TX control word 1 for fallback rates */
0032     __le16 phy_ctl1_rts;        /* PHY TX control word 1 RTS */
0033     __le16 phy_ctl1_rts_fb;     /* PHY TX control word 1 RTS for fallback rates */
0034     __u8 phy_rate;          /* PHY rate */
0035     __u8 phy_rate_rts;      /* PHY rate for RTS/CTS */
0036     __u8 extra_ft;          /* Extra Frame Types */
0037     __u8 chan_radio_code;       /* Channel Radio Code */
0038     __u8 iv[16];            /* Encryption IV */
0039     __u8 tx_receiver[6];        /* TX Frame Receiver address */
0040     __le16 tx_fes_time_fb;      /* TX FES Time Fallback */
0041     struct b43_plcp_hdr6 rts_plcp_fb; /* RTS fallback PLCP header */
0042     __le16 rts_dur_fb;      /* RTS fallback duration */
0043     struct b43_plcp_hdr6 plcp_fb;   /* Fallback PLCP header */
0044     __le16 dur_fb;          /* Fallback duration */
0045     __le16 mimo_modelen;        /* MIMO mode length */
0046     __le16 mimo_ratelen_fb;     /* MIMO fallback rate length */
0047     __le32 timeout;         /* Timeout */
0048
0049     union {
0050         /* Tested with 598.314, 644.1001 and 666.2 */
0051         struct {
0052             __le16 mimo_antenna;            /* MIMO antenna select */
0053             __le16 preload_size;            /* Preload size */
0054             PAD_BYTES(2);
0055             __le16 cookie;                  /* TX frame cookie */
0056             __le16 tx_status;               /* TX status */
0057             __le16 max_n_mpdus;
0058             __le16 max_a_bytes_mrt;
0059             __le16 max_a_bytes_fbr;
0060             __le16 min_m_bytes;
0061             struct b43_plcp_hdr6 rts_plcp;  /* RTS PLCP header */
0062             __u8 rts_frame[16];             /* The RTS frame (if used) */
0063             PAD_BYTES(2);
0064             struct b43_plcp_hdr6 plcp;      /* Main PLCP header */
0065         } format_598 __packed;
0066
0067         /* Tested with 410.2160, 478.104 and 508.* */
0068         struct {
0069             __le16 mimo_antenna;        /* MIMO antenna select */
0070             __le16 preload_size;        /* Preload size */
0071             PAD_BYTES(2);
0072             __le16 cookie;          /* TX frame cookie */
0073             __le16 tx_status;       /* TX status */
0074             struct b43_plcp_hdr6 rts_plcp;  /* RTS PLCP header */
0075             __u8 rts_frame[16];     /* The RTS frame (if used) */
0076             PAD_BYTES(2);
0077             struct b43_plcp_hdr6 plcp;  /* Main PLCP header */
0078         } format_410 __packed;
0079
0080         /* Tested with 351.126 */
0081         struct {
0082             PAD_BYTES(2);
0083             __le16 cookie;          /* TX frame cookie */
0084             __le16 tx_status;       /* TX status */
0085             struct b43_plcp_hdr6 rts_plcp;  /* RTS PLCP header */
0086             __u8 rts_frame[16];     /* The RTS frame (if used) */
0087             PAD_BYTES(2);
0088             struct b43_plcp_hdr6 plcp;  /* Main PLCP header */
0089         } format_351 __packed;
0090
0091     } __packed;
0092 } __packed;
0093
0094 struct b43_tx_legacy_rate_phy_ctl_entry {
0095     u8 bitrate;
0096     u16 coding_rate;
0097     u16 modulation;
0098 };
0099
0100 /* MAC TX control */
0101 #define B43_TXH_MAC_RTS_FB_SHORTPRMBL   0x80000000 /* RTS fallback preamble */
0102 #define B43_TXH_MAC_RTS_SHORTPRMBL  0x40000000 /* RTS main rate preamble */
0103 #define B43_TXH_MAC_FB_SHORTPRMBL   0x20000000 /* Main fallback preamble */
0104 #define B43_TXH_MAC_USEFBR      0x10000000 /* Use fallback rate for this AMPDU */
0105 #define B43_TXH_MAC_KEYIDX      0x0FF00000 /* Security key index */
0106 #define B43_TXH_MAC_KEYIDX_SHIFT    20
0107 #define B43_TXH_MAC_ALT_TXPWR       0x00080000 /* Use alternate txpwr defined at loc. M_ALT_TXPWR_IDX */
0108 #define B43_TXH_MAC_KEYALG      0x00070000 /* Security key algorithm */
0109 #define B43_TXH_MAC_KEYALG_SHIFT    16
0110 #define B43_TXH_MAC_AMIC        0x00008000 /* AMIC */
0111 #define B43_TXH_MAC_RIFS        0x00004000 /* Use RIFS */
0112 #define B43_TXH_MAC_LIFETIME        0x00002000 /* Lifetime */
0113 #define B43_TXH_MAC_FRAMEBURST      0x00001000 /* Frameburst */
0114 #define B43_TXH_MAC_SENDCTS     0x00000800 /* Send CTS-to-self */
0115 #define B43_TXH_MAC_AMPDU       0x00000600 /* AMPDU status */
0116 #define  B43_TXH_MAC_AMPDU_MPDU     0x00000000 /* Regular MPDU, not an AMPDU */
0117 #define  B43_TXH_MAC_AMPDU_FIRST    0x00000200 /* First MPDU or AMPDU */
0118 #define  B43_TXH_MAC_AMPDU_INTER    0x00000400 /* Intermediate MPDU or AMPDU */
0119 #define  B43_TXH_MAC_AMPDU_LAST     0x00000600 /* Last (or only) MPDU of AMPDU */
0120 #define B43_TXH_MAC_40MHZ       0x00000100 /* Use 40 MHz bandwidth */
0121 #define B43_TXH_MAC_5GHZ        0x00000080 /* 5GHz band */
0122 #define B43_TXH_MAC_DFCS        0x00000040 /* DFCS */
0123 #define B43_TXH_MAC_IGNPMQ      0x00000020 /* Ignore PMQ */
0124 #define B43_TXH_MAC_HWSEQ       0x00000010 /* Use Hardware Sequence Number */
0125 #define B43_TXH_MAC_STMSDU      0x00000008 /* Start MSDU */
0126 #define B43_TXH_MAC_SENDRTS     0x00000004 /* Send RTS */
0127 #define B43_TXH_MAC_LONGFRAME       0x00000002 /* Long frame */
0128 #define B43_TXH_MAC_ACK         0x00000001 /* Immediate ACK */
0129
0130 /* Extra Frame Types */
0131 #define B43_TXH_EFT_FB          0x03 /* Data frame fallback encoding */
0132 #define  B43_TXH_EFT_FB_CCK     0x00 /* CCK */
0133 #define  B43_TXH_EFT_FB_OFDM        0x01 /* OFDM */
0134 #define  B43_TXH_EFT_FB_HT      0x02 /* HT */
0135 #define  B43_TXH_EFT_FB_VHT     0x03 /* VHT */
0136 #define B43_TXH_EFT_RTS         0x0C /* RTS/CTS encoding */
0137 #define  B43_TXH_EFT_RTS_CCK        0x00 /* CCK */
0138 #define  B43_TXH_EFT_RTS_OFDM       0x04 /* OFDM */
0139 #define  B43_TXH_EFT_RTS_HT     0x08 /* HT */
0140 #define  B43_TXH_EFT_RTS_VHT        0x0C /* VHT */
0141 #define B43_TXH_EFT_RTSFB       0x30 /* RTS/CTS fallback encoding */
0142 #define  B43_TXH_EFT_RTSFB_CCK      0x00 /* CCK */
0143 #define  B43_TXH_EFT_RTSFB_OFDM     0x10 /* OFDM */
0144 #define  B43_TXH_EFT_RTSFB_HT       0x20 /* HT */
0145 #define  B43_TXH_EFT_RTSFB_VHT      0x30 /* VHT */
0146
0147 /* PHY TX control word */
0148 #define B43_TXH_PHY_ENC         0x0003 /* Data frame encoding */
0149 #define  B43_TXH_PHY_ENC_CCK        0x0000 /* CCK */
0150 #define  B43_TXH_PHY_ENC_OFDM       0x0001 /* OFDM */
0151 #define  B43_TXH_PHY_ENC_HT     0x0002 /* HT */
0152 #define  B43_TXH_PHY_ENC_VHT        0x0003 /* VHT */
0153 #define B43_TXH_PHY_SHORTPRMBL      0x0010 /* Use short preamble */
0154 #define B43_TXH_PHY_ANT         0x03C0 /* Antenna selection */
0155 #define  B43_TXH_PHY_ANT0       0x0000 /* Use antenna 0 */
0156 #define  B43_TXH_PHY_ANT1       0x0040 /* Use antenna 1 */
0157 #define  B43_TXH_PHY_ANT01AUTO      0x00C0 /* Use antenna 0/1 auto */
0158 #define  B43_TXH_PHY_ANT2       0x0100 /* Use antenna 2 */
0159 #define  B43_TXH_PHY_ANT3       0x0200 /* Use antenna 3 */
0160 #define B43_TXH_PHY_TXPWR       0xFC00 /* TX power */
0161 #define B43_TXH_PHY_TXPWR_SHIFT     10
0162
0163 /* PHY TX control word 1 */
0164 #define B43_TXH_PHY1_BW         0x0007 /* Bandwidth */
0165 #define  B43_TXH_PHY1_BW_10     0x0000 /* 10 MHz */
0166 #define  B43_TXH_PHY1_BW_10U        0x0001 /* 10 MHz upper */
0167 #define  B43_TXH_PHY1_BW_20     0x0002 /* 20 MHz */
0168 #define  B43_TXH_PHY1_BW_20U        0x0003 /* 20 MHz upper */
0169 #define  B43_TXH_PHY1_BW_40     0x0004 /* 40 MHz */
0170 #define  B43_TXH_PHY1_BW_40DUP      0x0005 /* 40 MHz duplicate */
0171 #define B43_TXH_PHY1_MODE       0x0038 /* Mode */
0172 #define  B43_TXH_PHY1_MODE_SISO     0x0000 /* SISO */
0173 #define  B43_TXH_PHY1_MODE_CDD      0x0008 /* CDD */
0174 #define  B43_TXH_PHY1_MODE_STBC     0x0010 /* STBC */
0175 #define  B43_TXH_PHY1_MODE_SDM      0x0018 /* SDM */
0176 #define B43_TXH_PHY1_CRATE      0x0700 /* Coding rate */
0177 #define  B43_TXH_PHY1_CRATE_1_2     0x0000 /* 1/2 */
0178 #define  B43_TXH_PHY1_CRATE_2_3     0x0100 /* 2/3 */
0179 #define  B43_TXH_PHY1_CRATE_3_4     0x0200 /* 3/4 */
0180 #define  B43_TXH_PHY1_CRATE_4_5     0x0300 /* 4/5 */
0181 #define  B43_TXH_PHY1_CRATE_5_6     0x0400 /* 5/6 */
0182 #define  B43_TXH_PHY1_CRATE_7_8     0x0600 /* 7/8 */
0183 #define B43_TXH_PHY1_MODUL      0x3800 /* Modulation scheme */
0184 #define  B43_TXH_PHY1_MODUL_BPSK    0x0000 /* BPSK */
0185 #define  B43_TXH_PHY1_MODUL_QPSK    0x0800 /* QPSK */
0186 #define  B43_TXH_PHY1_MODUL_QAM16   0x1000 /* QAM16 */
0187 #define  B43_TXH_PHY1_MODUL_QAM64   0x1800 /* QAM64 */
0188 #define  B43_TXH_PHY1_MODUL_QAM256  0x2000 /* QAM256 */
0189
0190
0191 static inline
0192 size_t b43_txhdr_size(struct b43_wldev *dev)
0193 {
0194     switch (dev->fw.hdr_format) {
0195     case B43_FW_HDR_598:
0196         return 112 + sizeof(struct b43_plcp_hdr6);
0197     case B43_FW_HDR_410:
0198         return 104 + sizeof(struct b43_plcp_hdr6);
0199     case B43_FW_HDR_351:
0200         return 100 + sizeof(struct b43_plcp_hdr6);
0201     }
0202     return 0;
0203 }
0204
0205
0206 int b43_generate_txhdr(struct b43_wldev *dev,
0207                u8 * txhdr,
0208                struct sk_buff *skb_frag,
0209                struct ieee80211_tx_info *txctl, u16 cookie);
0210
0211 /* Transmit Status */
0212 struct b43_txstatus {
0213     u16 cookie;     /* The cookie from the txhdr */
0214     u16 seq;        /* Sequence number */
0215     u8 phy_stat;        /* PHY TX status */
0216     u8 frame_count;     /* Frame transmit count */
0217     u8 rts_count;       /* RTS transmit count */
0218     u8 supp_reason;     /* Suppression reason */
0219     /* flags */
0220     u8 pm_indicated;    /* PM mode indicated to AP */
0221     u8 intermediate;    /* Intermediate status notification (not final) */
0222     u8 for_ampdu;       /* Status is for an AMPDU (afterburner) */
0223     u8 acked;       /* Wireless ACK received */
0224 };
0225
0226 /* txstatus supp_reason values */
0227 enum {
0228     B43_TXST_SUPP_NONE, /* Not suppressed */
0229     B43_TXST_SUPP_PMQ,  /* Suppressed due to PMQ entry */
0230     B43_TXST_SUPP_FLUSH,    /* Suppressed due to flush request */
0231     B43_TXST_SUPP_PREV, /* Previous fragment failed */
0232     B43_TXST_SUPP_CHAN, /* Channel mismatch */
0233     B43_TXST_SUPP_LIFE, /* Lifetime expired */
0234     B43_TXST_SUPP_UNDER,    /* Buffer underflow */
0235     B43_TXST_SUPP_ABNACK,   /* Afterburner NACK */
0236 };
0237
0238 /* Receive header for v4 firmware. */
0239 struct b43_rxhdr_fw4 {
0240     __le16 frame_len;   /* Frame length */
0241      PAD_BYTES(2);
0242     __le16 phy_status0; /* PHY RX Status 0 */
0243     union {
0244         /* RSSI for A/B/G-PHYs */
0245         struct {
0246             __u8 jssi;  /* PHY RX Status 1: JSSI */
0247             __u8 sig_qual;  /* PHY RX Status 1: Signal Quality */
0248         } __packed;
0249
0250         /* RSSI for N-PHYs */
0251         struct {
0252             __s8 power0;    /* PHY RX Status 1: Power 0 */
0253             __s8 power1;    /* PHY RX Status 1: Power 1 */
0254         } __packed;
0255     } __packed;
0256     union {
0257         /* HT-PHY */
0258         struct {
0259             PAD_BYTES(1);
0260             __s8 phy_ht_power0;
0261         } __packed;
0262
0263         /* RSSI for N-PHYs */
0264         struct {
0265             __s8 power2;
0266             PAD_BYTES(1);
0267         } __packed;
0268
0269         __le16 phy_status2; /* PHY RX Status 2 */
0270     } __packed;
0271     union {
0272         /* HT-PHY */
0273         struct {
0274             __s8 phy_ht_power1;
0275             __s8 phy_ht_power2;
0276         } __packed;
0277
0278         __le16 phy_status3; /* PHY RX Status 3 */
0279     } __packed;
0280     union {
0281         /* Tested with 598.314, 644.1001 and 666.2 */
0282         struct {
0283             __le16 phy_status4; /* PHY RX Status 4 */
0284             __le16 phy_status5; /* PHY RX Status 5 */
0285             __le32 mac_status;  /* MAC RX status */
0286             __le16 mac_time;
0287             __le16 channel;
0288         } format_598 __packed;
0289
0290         /* Tested with 351.126, 410.2160, 478.104 and 508.* */
0291         struct {
0292             __le32 mac_status;  /* MAC RX status */
0293             __le16 mac_time;
0294             __le16 channel;
0295         } format_351 __packed;
0296     } __packed;
0297 } __packed;
0298
0299 /* PHY RX Status 0 */
0300 #define B43_RX_PHYST0_GAINCTL       0x4000 /* Gain Control */
0301 #define B43_RX_PHYST0_PLCPHCF       0x0200
0302 #define B43_RX_PHYST0_PLCPFV        0x0100
0303 #define B43_RX_PHYST0_SHORTPRMBL    0x0080 /* Received with Short Preamble */
0304 #define B43_RX_PHYST0_LCRS      0x0040
0305 #define B43_RX_PHYST0_ANT       0x0020 /* Antenna */
0306 #define B43_RX_PHYST0_UNSRATE       0x0010
0307 #define B43_RX_PHYST0_CLIP      0x000C
0308 #define B43_RX_PHYST0_CLIP_SHIFT    2
0309 #define B43_RX_PHYST0_FTYPE     0x0003 /* Frame type */
0310 #define  B43_RX_PHYST0_CCK      0x0000 /* Frame type: CCK */
0311 #define  B43_RX_PHYST0_OFDM     0x0001 /* Frame type: OFDM */
0312 #define  B43_RX_PHYST0_PRE_N        0x0002 /* Pre-standard N-PHY frame */
0313 #define  B43_RX_PHYST0_STD_N        0x0003 /* Standard N-PHY frame */
0314
0315 /* PHY RX Status 2 */
0316 #define B43_RX_PHYST2_LNAG      0xC000 /* LNA Gain */
0317 #define B43_RX_PHYST2_LNAG_SHIFT    14
0318 #define B43_RX_PHYST2_PNAG      0x3C00 /* PNA Gain */
0319 #define B43_RX_PHYST2_PNAG_SHIFT    10
0320 #define B43_RX_PHYST2_FOFF      0x03FF /* F offset */
0321
0322 /* PHY RX Status 3 */
0323 #define B43_RX_PHYST3_DIGG      0x1800 /* DIG Gain */
0324 #define B43_RX_PHYST3_DIGG_SHIFT    11
0325 #define B43_RX_PHYST3_TRSTATE       0x0400 /* TR state */
0326
0327 /* MAC RX Status */
0328 #define B43_RX_MAC_RXST_VALID       0x01000000 /* PHY RXST valid */
0329 #define B43_RX_MAC_TKIP_MICERR      0x00100000 /* TKIP MIC error */
0330 #define B43_RX_MAC_TKIP_MICATT      0x00080000 /* TKIP MIC attempted */
0331 #define B43_RX_MAC_AGGTYPE      0x00060000 /* Aggregation type */
0332 #define B43_RX_MAC_AGGTYPE_SHIFT    17
0333 #define B43_RX_MAC_AMSDU        0x00010000 /* A-MSDU mask */
0334 #define B43_RX_MAC_BEACONSENT       0x00008000 /* Beacon sent flag */
0335 #define B43_RX_MAC_KEYIDX       0x000007E0 /* Key index */
0336 #define B43_RX_MAC_KEYIDX_SHIFT     5
0337 #define B43_RX_MAC_DECERR       0x00000010 /* Decrypt error */
0338 #define B43_RX_MAC_DEC          0x00000008 /* Decryption attempted */
0339 #define B43_RX_MAC_PADDING      0x00000004 /* Pad bytes present */
0340 #define B43_RX_MAC_RESP         0x00000002 /* Response frame transmitted */
0341 #define B43_RX_MAC_FCSERR       0x00000001 /* FCS error */
0342
0343 /* RX channel */
0344 #define B43_RX_CHAN_40MHZ       0x1000 /* 40 Mhz channel width */
0345 #define B43_RX_CHAN_5GHZ        0x0800 /* 5 Ghz band */
0346 #define B43_RX_CHAN_ID          0x07F8 /* Channel ID */
0347 #define B43_RX_CHAN_ID_SHIFT        3
0348 #define B43_RX_CHAN_PHYTYPE     0x0007 /* PHY type */
0349
0350
0351 u8 b43_plcp_get_ratecode_cck(const u8 bitrate);
0352 u8 b43_plcp_get_ratecode_ofdm(const u8 bitrate);
0353
0354 void b43_generate_plcp_hdr(struct b43_plcp_hdr4 *plcp,
0355                const u16 octets, const u8 bitrate);
0356
0357 void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr);
0358
0359 void b43_handle_txstatus(struct b43_wldev *dev,
0360              const struct b43_txstatus *status);
0361 bool b43_fill_txstatus_report(struct b43_wldev *dev,
0362                   struct ieee80211_tx_info *report,
0363                   const struct b43_txstatus *status);
0364
0365 void b43_tx_suspend(struct b43_wldev *dev);
0366 void b43_tx_resume(struct b43_wldev *dev);
0367
0368
0369 /* Helper functions for converting the key-table index from "firmware-format"
0370  * to "raw-format" and back. The firmware API changed for this at some revision.
0371  * We need to account for that here. */
0372 static inline int b43_new_kidx_api(struct b43_wldev *dev)
0373 {
0374     /* FIXME: Not sure the change was at rev 351 */
0375     return (dev->fw.rev >= 351);
0376 }
0377 static inline u8 b43_kidx_to_fw(struct b43_wldev *dev, u8 raw_kidx)
0378 {
0379     u8 firmware_kidx;
0380     if (b43_new_kidx_api(dev)) {
0381         firmware_kidx = raw_kidx;
0382     } else {
0383         if (raw_kidx >= 4)  /* Is per STA key? */
0384             firmware_kidx = raw_kidx - 4;
0385         else
0386             firmware_kidx = raw_kidx;   /* TX default key */
0387     }
0388     return firmware_kidx;
0389 }
0390 static inline u8 b43_kidx_to_raw(struct b43_wldev *dev, u8 firmware_kidx)
0391 {
0392     u8 raw_kidx;
0393     if (b43_new_kidx_api(dev))
0394         raw_kidx = firmware_kidx;
0395     else
0396         raw_kidx = firmware_kidx + 4;   /* RX default keys or per STA keys */
0397     return raw_kidx;
0398 }
0399
0400 /* struct b43_private_tx_info - TX info private to b43.
0401  * The structure is placed in (struct ieee80211_tx_info *)->rate_driver_data
0402  *
0403  * @bouncebuffer: DMA Bouncebuffer (if used)
0404  */
0405 struct b43_private_tx_info {
0406     void *bouncebuffer;
0407 };
0408
0409 static inline struct b43_private_tx_info *
0410 b43_get_priv_tx_info(struct ieee80211_tx_info *info)
0411 {
0412     BUILD_BUG_ON(sizeof(struct b43_private_tx_info) >
0413              sizeof(info->rate_driver_data));
0414     return (struct b43_private_tx_info *)info->rate_driver_data;
0415 }
0416
0417 #endif /* B43_XMIT_H_ */