broadcom/b43/radio_2055.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef B43_RADIO_2055_H_
0003 #define B43_RADIO_2055_H_
0004
0005 #include <linux/types.h>
0006
0007 #include "tables_nphy.h"
0008
0009 #define B2055_GEN_SPARE         0x00 /* GEN spare */
0010 #define B2055_SP_PINPD          0x02 /* SP PIN PD */
0011 #define B2055_C1_SP_RSSI        0x03 /* SP RSSI Core 1 */
0012 #define B2055_C1_SP_PDMISC      0x04 /* SP PD MISC Core 1 */
0013 #define B2055_C2_SP_RSSI        0x05 /* SP RSSI Core 2 */
0014 #define B2055_C2_SP_PDMISC      0x06 /* SP PD MISC Core 2 */
0015 #define B2055_C1_SP_RXGC1       0x07 /* SP RX GC1 Core 1 */
0016 #define B2055_C1_SP_RXGC2       0x08 /* SP RX GC2 Core 1 */
0017 #define B2055_C2_SP_RXGC1       0x09 /* SP RX GC1 Core 2 */
0018 #define B2055_C2_SP_RXGC2       0x0A /* SP RX GC2 Core 2 */
0019 #define B2055_C1_SP_LPFBWSEL        0x0B /* SP LPF BW select Core 1 */
0020 #define B2055_C2_SP_LPFBWSEL        0x0C /* SP LPF BW select Core 2 */
0021 #define B2055_C1_SP_TXGC1       0x0D /* SP TX GC1 Core 1 */
0022 #define B2055_C1_SP_TXGC2       0x0E /* SP TX GC2 Core 1 */
0023 #define B2055_C2_SP_TXGC1       0x0F /* SP TX GC1 Core 2 */
0024 #define B2055_C2_SP_TXGC2       0x10 /* SP TX GC2 Core 2 */
0025 #define B2055_MASTER1           0x11 /* Master control 1 */
0026 #define B2055_MASTER2           0x12 /* Master control 2 */
0027 #define B2055_PD_LGEN           0x13 /* PD LGEN */
0028 #define B2055_PD_PLLTS          0x14 /* PD PLL TS */
0029 #define B2055_C1_PD_LGBUF       0x15 /* PD Core 1 LGBUF */
0030 #define B2055_C1_PD_TX          0x16 /* PD Core 1 TX */
0031 #define B2055_C1_PD_RXTX        0x17 /* PD Core 1 RXTX */
0032 #define B2055_C1_PD_RSSIMISC        0x18 /* PD Core 1 RSSI MISC */
0033 #define B2055_C2_PD_LGBUF       0x19 /* PD Core 2 LGBUF */
0034 #define B2055_C2_PD_TX          0x1A /* PD Core 2 TX */
0035 #define B2055_C2_PD_RXTX        0x1B /* PD Core 2 RXTX */
0036 #define B2055_C2_PD_RSSIMISC        0x1C /* PD Core 2 RSSI MISC */
0037 #define B2055_PWRDET_LGEN       0x1D /* PWRDET LGEN */
0038 #define B2055_C1_PWRDET_LGBUF       0x1E /* PWRDET LGBUF Core 1 */
0039 #define B2055_C1_PWRDET_RXTX        0x1F /* PWRDET RXTX Core 1 */
0040 #define B2055_C2_PWRDET_LGBUF       0x20 /* PWRDET LGBUF Core 2 */
0041 #define B2055_C2_PWRDET_RXTX        0x21 /* PWRDET RXTX Core 2 */
0042 #define B2055_RRCCAL_CS         0x22 /* RRCCAL Control spare */
0043 #define B2055_RRCCAL_NOPTSEL        0x23 /* RRCCAL N OPT SEL */
0044 #define B2055_CAL_MISC          0x24 /* CAL MISC */
0045 #define B2055_CAL_COUT          0x25 /* CAL Counter out */
0046 #define B2055_CAL_COUT2         0x26 /* CAL Counter out 2 */
0047 #define B2055_CAL_CVARCTL       0x27 /* CAL CVAR Control */
0048 #define B2055_CAL_RVARCTL       0x28 /* CAL RVAR Control */
0049 #define B2055_CAL_LPOCTL        0x29 /* CAL LPO Control */
0050 #define B2055_CAL_TS            0x2A /* CAL TS */
0051 #define B2055_CAL_RCCALRTS      0x2B /* CAL RCCAL READ TS */
0052 #define B2055_CAL_RCALRTS       0x2C /* CAL RCAL READ TS */
0053 #define B2055_PADDRV            0x2D /* PAD driver */
0054 #define B2055_XOCTL1            0x2E /* XO Control 1 */
0055 #define B2055_XOCTL2            0x2F /* XO Control 2 */
0056 #define B2055_XOREGUL           0x30 /* XO Regulator */
0057 #define B2055_XOMISC            0x31 /* XO misc */
0058 #define B2055_PLL_LFC1          0x32 /* PLL LF C1 */
0059 #define B2055_PLL_CALVTH        0x33 /* PLL CAL VTH */
0060 #define B2055_PLL_LFC2          0x34 /* PLL LF C2 */
0061 #define B2055_PLL_REF           0x35 /* PLL reference */
0062 #define B2055_PLL_LFR1          0x36 /* PLL LF R1 */
0063 #define B2055_PLL_PFDCP         0x37 /* PLL PFD CP */
0064 #define B2055_PLL_IDAC_CPOPAMP      0x38 /* PLL IDAC CPOPAMP */
0065 #define B2055_PLL_CPREG         0x39 /* PLL CP Regulator */
0066 #define B2055_PLL_RCAL          0x3A /* PLL RCAL */
0067 #define B2055_RF_PLLMOD0        0x3B /* RF PLL MOD0 */
0068 #define B2055_RF_PLLMOD1        0x3C /* RF PLL MOD1 */
0069 #define B2055_RF_MMDIDAC1       0x3D /* RF MMD IDAC 1 */
0070 #define B2055_RF_MMDIDAC0       0x3E /* RF MMD IDAC 0 */
0071 #define B2055_RF_MMDSP          0x3F /* RF MMD spare */
0072 #define B2055_VCO_CAL1          0x40 /* VCO cal 1 */
0073 #define B2055_VCO_CAL2          0x41 /* VCO cal 2 */
0074 #define B2055_VCO_CAL3          0x42 /* VCO cal 3 */
0075 #define B2055_VCO_CAL4          0x43 /* VCO cal 4 */
0076 #define B2055_VCO_CAL5          0x44 /* VCO cal 5 */
0077 #define B2055_VCO_CAL6          0x45 /* VCO cal 6 */
0078 #define B2055_VCO_CAL7          0x46 /* VCO cal 7 */
0079 #define B2055_VCO_CAL8          0x47 /* VCO cal 8 */
0080 #define B2055_VCO_CAL9          0x48 /* VCO cal 9 */
0081 #define B2055_VCO_CAL10         0x49 /* VCO cal 10 */
0082 #define B2055_VCO_CAL11         0x4A /* VCO cal 11 */
0083 #define B2055_VCO_CAL12         0x4B /* VCO cal 12 */
0084 #define B2055_VCO_CAL13         0x4C /* VCO cal 13 */
0085 #define B2055_VCO_CAL14         0x4D /* VCO cal 14 */
0086 #define B2055_VCO_CAL15         0x4E /* VCO cal 15 */
0087 #define B2055_VCO_CAL16         0x4F /* VCO cal 16 */
0088 #define B2055_VCO_KVCO          0x50 /* VCO KVCO */
0089 #define B2055_VCO_CAPTAIL       0x51 /* VCO CAP TAIL */
0090 #define B2055_VCO_IDACVCO       0x52 /* VCO IDAC VCO */
0091 #define B2055_VCO_REG           0x53 /* VCO Regulator */
0092 #define B2055_PLL_RFVTH         0x54 /* PLL RF VTH */
0093 #define B2055_LGBUF_CENBUF      0x55 /* LGBUF CEN BUF */
0094 #define B2055_LGEN_TUNE1        0x56 /* LGEN tune 1 */
0095 #define B2055_LGEN_TUNE2        0x57 /* LGEN tune 2 */
0096 #define B2055_LGEN_IDAC1        0x58 /* LGEN IDAC 1 */
0097 #define B2055_LGEN_IDAC2        0x59 /* LGEN IDAC 2 */
0098 #define B2055_LGEN_BIASC        0x5A /* LGEN BIAS counter */
0099 #define B2055_LGEN_BIASIDAC     0x5B /* LGEN BIAS IDAC */
0100 #define B2055_LGEN_RCAL         0x5C /* LGEN RCAL */
0101 #define B2055_LGEN_DIV          0x5D /* LGEN div */
0102 #define B2055_LGEN_SPARE2       0x5E /* LGEN spare 2 */
0103 #define B2055_C1_LGBUF_ATUNE        0x5F /* Core 1 LGBUF A tune */
0104 #define B2055_C1_LGBUF_GTUNE        0x60 /* Core 1 LGBUF G tune */
0105 #define B2055_C1_LGBUF_DIV      0x61 /* Core 1 LGBUF div */
0106 #define B2055_C1_LGBUF_AIDAC        0x62 /* Core 1 LGBUF A IDAC */
0107 #define B2055_C1_LGBUF_GIDAC        0x63 /* Core 1 LGBUF G IDAC */
0108 #define B2055_C1_LGBUF_IDACFO       0x64 /* Core 1 LGBUF IDAC filter override */
0109 #define B2055_C1_LGBUF_SPARE        0x65 /* Core 1 LGBUF spare */
0110 #define B2055_C1_RX_RFSPC1      0x66 /* Core 1 RX RF SPC1 */
0111 #define B2055_C1_RX_RFR1        0x67 /* Core 1 RX RF reg 1 */
0112 #define B2055_C1_RX_RFR2        0x68 /* Core 1 RX RF reg 2 */
0113 #define B2055_C1_RX_RFRCAL      0x69 /* Core 1 RX RF RCAL */
0114 #define B2055_C1_RX_BB_BLCMP        0x6A /* Core 1 RX Baseband BUFI LPF CMP */
0115 #define B2055_C1_RX_BB_LPF      0x6B /* Core 1 RX Baseband LPF */
0116 #define B2055_C1_RX_BB_MIDACHP      0x6C /* Core 1 RX Baseband MIDAC High-pass */
0117 #define B2055_C1_RX_BB_VGA1IDAC     0x6D /* Core 1 RX Baseband VGA1 IDAC */
0118 #define B2055_C1_RX_BB_VGA2IDAC     0x6E /* Core 1 RX Baseband VGA2 IDAC */
0119 #define B2055_C1_RX_BB_VGA3IDAC     0x6F /* Core 1 RX Baseband VGA3 IDAC */
0120 #define B2055_C1_RX_BB_BUFOCTL      0x70 /* Core 1 RX Baseband BUFO Control */
0121 #define B2055_C1_RX_BB_RCCALCTL     0x71 /* Core 1 RX Baseband RCCAL Control */
0122 #define B2055_C1_RX_BB_RSSICTL1     0x72 /* Core 1 RX Baseband RSSI Control 1 */
0123 #define B2055_C1_RX_BB_RSSICTL2     0x73 /* Core 1 RX Baseband RSSI Control 2 */
0124 #define B2055_C1_RX_BB_RSSICTL3     0x74 /* Core 1 RX Baseband RSSI Control 3 */
0125 #define B2055_C1_RX_BB_RSSICTL4     0x75 /* Core 1 RX Baseband RSSI Control 4 */
0126 #define B2055_C1_RX_BB_RSSICTL5     0x76 /* Core 1 RX Baseband RSSI Control 5 */
0127 #define B2055_C1_RX_BB_REG      0x77 /* Core 1 RX Baseband Regulator */
0128 #define B2055_C1_RX_BB_SPARE1       0x78 /* Core 1 RX Baseband spare 1 */
0129 #define B2055_C1_RX_TXBBRCAL        0x79 /* Core 1 RX TX BB RCAL */
0130 #define B2055_C1_TX_RF_SPGA     0x7A /* Core 1 TX RF SGM PGA */
0131 #define B2055_C1_TX_RF_SPAD     0x7B /* Core 1 TX RF SGM PAD */
0132 #define B2055_C1_TX_RF_CNTPGA1      0x7C /* Core 1 TX RF counter PGA 1 */
0133 #define B2055_C1_TX_RF_CNTPAD1      0x7D /* Core 1 TX RF counter PAD 1 */
0134 #define B2055_C1_TX_RF_PGAIDAC      0x7E /* Core 1 TX RF PGA IDAC */
0135 #define B2055_C1_TX_PGAPADTN        0x7F /* Core 1 TX PGA PAD TN */
0136 #define B2055_C1_TX_PADIDAC1        0x80 /* Core 1 TX PAD IDAC 1 */
0137 #define B2055_C1_TX_PADIDAC2        0x81 /* Core 1 TX PAD IDAC 2 */
0138 #define B2055_C1_TX_MXBGTRIM        0x82 /* Core 1 TX MX B/G TRIM */
0139 #define B2055_C1_TX_RF_RCAL     0x83 /* Core 1 TX RF RCAL */
0140 #define B2055_C1_TX_RF_PADTSSI1     0x84 /* Core 1 TX RF PAD TSSI1 */
0141 #define B2055_C1_TX_RF_PADTSSI2     0x85 /* Core 1 TX RF PAD TSSI2 */
0142 #define B2055_C1_TX_RF_SPARE        0x86 /* Core 1 TX RF spare */
0143 #define B2055_C1_TX_RF_IQCAL1       0x87 /* Core 1 TX RF I/Q CAL 1 */
0144 #define B2055_C1_TX_RF_IQCAL2       0x88 /* Core 1 TX RF I/Q CAL 2 */
0145 #define B2055_C1_TXBB_RCCAL     0x89 /* Core 1 TXBB RC CAL Control */
0146 #define B2055_C1_TXBB_LPF1      0x8A /* Core 1 TXBB LPF 1 */
0147 #define B2055_C1_TX_VOSCNCL     0x8B /* Core 1 TX VOS CNCL */
0148 #define B2055_C1_TX_LPF_MXGMIDAC    0x8C /* Core 1 TX LPF MXGM IDAC */
0149 #define B2055_C1_TX_BB_MXGM     0x8D /* Core 1 TX BB MXGM */
0150 #define B2055_C2_LGBUF_ATUNE        0x8E /* Core 2 LGBUF A tune */
0151 #define B2055_C2_LGBUF_GTUNE        0x8F /* Core 2 LGBUF G tune */
0152 #define B2055_C2_LGBUF_DIV      0x90 /* Core 2 LGBUF div */
0153 #define B2055_C2_LGBUF_AIDAC        0x91 /* Core 2 LGBUF A IDAC */
0154 #define B2055_C2_LGBUF_GIDAC        0x92 /* Core 2 LGBUF G IDAC */
0155 #define B2055_C2_LGBUF_IDACFO       0x93 /* Core 2 LGBUF IDAC filter override */
0156 #define B2055_C2_LGBUF_SPARE        0x94 /* Core 2 LGBUF spare */
0157 #define B2055_C2_RX_RFSPC1      0x95 /* Core 2 RX RF SPC1 */
0158 #define B2055_C2_RX_RFR1        0x96 /* Core 2 RX RF reg 1 */
0159 #define B2055_C2_RX_RFR2        0x97 /* Core 2 RX RF reg 2 */
0160 #define B2055_C2_RX_RFRCAL      0x98 /* Core 2 RX RF RCAL */
0161 #define B2055_C2_RX_BB_BLCMP        0x99 /* Core 2 RX Baseband BUFI LPF CMP */
0162 #define B2055_C2_RX_BB_LPF      0x9A /* Core 2 RX Baseband LPF */
0163 #define B2055_C2_RX_BB_MIDACHP      0x9B /* Core 2 RX Baseband MIDAC High-pass */
0164 #define B2055_C2_RX_BB_VGA1IDAC     0x9C /* Core 2 RX Baseband VGA1 IDAC */
0165 #define B2055_C2_RX_BB_VGA2IDAC     0x9D /* Core 2 RX Baseband VGA2 IDAC */
0166 #define B2055_C2_RX_BB_VGA3IDAC     0x9E /* Core 2 RX Baseband VGA3 IDAC */
0167 #define B2055_C2_RX_BB_BUFOCTL      0x9F /* Core 2 RX Baseband BUFO Control */
0168 #define B2055_C2_RX_BB_RCCALCTL     0xA0 /* Core 2 RX Baseband RCCAL Control */
0169 #define B2055_C2_RX_BB_RSSICTL1     0xA1 /* Core 2 RX Baseband RSSI Control 1 */
0170 #define B2055_C2_RX_BB_RSSICTL2     0xA2 /* Core 2 RX Baseband RSSI Control 2 */
0171 #define B2055_C2_RX_BB_RSSICTL3     0xA3 /* Core 2 RX Baseband RSSI Control 3 */
0172 #define B2055_C2_RX_BB_RSSICTL4     0xA4 /* Core 2 RX Baseband RSSI Control 4 */
0173 #define B2055_C2_RX_BB_RSSICTL5     0xA5 /* Core 2 RX Baseband RSSI Control 5 */
0174 #define B2055_C2_RX_BB_REG      0xA6 /* Core 2 RX Baseband Regulator */
0175 #define B2055_C2_RX_BB_SPARE1       0xA7 /* Core 2 RX Baseband spare 1 */
0176 #define B2055_C2_RX_TXBBRCAL        0xA8 /* Core 2 RX TX BB RCAL */
0177 #define B2055_C2_TX_RF_SPGA     0xA9 /* Core 2 TX RF SGM PGA */
0178 #define B2055_C2_TX_RF_SPAD     0xAA /* Core 2 TX RF SGM PAD */
0179 #define B2055_C2_TX_RF_CNTPGA1      0xAB /* Core 2 TX RF counter PGA 1 */
0180 #define B2055_C2_TX_RF_CNTPAD1      0xAC /* Core 2 TX RF counter PAD 1 */
0181 #define B2055_C2_TX_RF_PGAIDAC      0xAD /* Core 2 TX RF PGA IDAC */
0182 #define B2055_C2_TX_PGAPADTN        0xAE /* Core 2 TX PGA PAD TN */
0183 #define B2055_C2_TX_PADIDAC1        0xAF /* Core 2 TX PAD IDAC 1 */
0184 #define B2055_C2_TX_PADIDAC2        0xB0 /* Core 2 TX PAD IDAC 2 */
0185 #define B2055_C2_TX_MXBGTRIM        0xB1 /* Core 2 TX MX B/G TRIM */
0186 #define B2055_C2_TX_RF_RCAL     0xB2 /* Core 2 TX RF RCAL */
0187 #define B2055_C2_TX_RF_PADTSSI1     0xB3 /* Core 2 TX RF PAD TSSI1 */
0188 #define B2055_C2_TX_RF_PADTSSI2     0xB4 /* Core 2 TX RF PAD TSSI2 */
0189 #define B2055_C2_TX_RF_SPARE        0xB5 /* Core 2 TX RF spare */
0190 #define B2055_C2_TX_RF_IQCAL1       0xB6 /* Core 2 TX RF I/Q CAL 1 */
0191 #define B2055_C2_TX_RF_IQCAL2       0xB7 /* Core 2 TX RF I/Q CAL 2 */
0192 #define B2055_C2_TXBB_RCCAL     0xB8 /* Core 2 TXBB RC CAL Control */
0193 #define B2055_C2_TXBB_LPF1      0xB9 /* Core 2 TXBB LPF 1 */
0194 #define B2055_C2_TX_VOSCNCL     0xBA /* Core 2 TX VOS CNCL */
0195 #define B2055_C2_TX_LPF_MXGMIDAC    0xBB /* Core 2 TX LPF MXGM IDAC */
0196 #define B2055_C2_TX_BB_MXGM     0xBC /* Core 2 TX BB MXGM */
0197 #define B2055_PRG_GCHP21        0xBD /* PRG GC HPVGA23 21 */
0198 #define B2055_PRG_GCHP22        0xBE /* PRG GC HPVGA23 22 */
0199 #define B2055_PRG_GCHP23        0xBF /* PRG GC HPVGA23 23 */
0200 #define B2055_PRG_GCHP24        0xC0 /* PRG GC HPVGA23 24 */
0201 #define B2055_PRG_GCHP25        0xC1 /* PRG GC HPVGA23 25 */
0202 #define B2055_PRG_GCHP26        0xC2 /* PRG GC HPVGA23 26 */
0203 #define B2055_PRG_GCHP27        0xC3 /* PRG GC HPVGA23 27 */
0204 #define B2055_PRG_GCHP28        0xC4 /* PRG GC HPVGA23 28 */
0205 #define B2055_PRG_GCHP29        0xC5 /* PRG GC HPVGA23 29 */
0206 #define B2055_PRG_GCHP30        0xC6 /* PRG GC HPVGA23 30 */
0207 #define B2055_C1_LNA_GAINBST        0xCD /* Core 1 LNA GAINBST */
0208 #define B2055_C1_B0NB_RSSIVCM       0xD2 /* Core 1 B0 narrow-band RSSI VCM */
0209 #define B2055_C1_GENSPARE2      0xD6 /* Core 1 GEN spare 2 */
0210 #define B2055_C2_LNA_GAINBST        0xD9 /* Core 2 LNA GAINBST */
0211 #define B2055_C2_B0NB_RSSIVCM       0xDE /* Core 2 B0 narrow-band RSSI VCM */
0212 #define B2055_C2_GENSPARE2      0xE2 /* Core 2 GEN spare 2 */
0213
0214 struct b43_nphy_channeltab_entry_rev2 {
0215     /* The channel number */
0216     u8 channel;
0217     /* The channel frequency in MHz */
0218     u16 freq;
0219     /* An unknown value */
0220     u16 unk2;
0221     /* Radio register values on channelswitch */
0222     u8 radio_pll_ref;
0223     u8 radio_rf_pllmod0;
0224     u8 radio_rf_pllmod1;
0225     u8 radio_vco_captail;
0226     u8 radio_vco_cal1;
0227     u8 radio_vco_cal2;
0228     u8 radio_pll_lfc1;
0229     u8 radio_pll_lfr1;
0230     u8 radio_pll_lfc2;
0231     u8 radio_lgbuf_cenbuf;
0232     u8 radio_lgen_tune1;
0233     u8 radio_lgen_tune2;
0234     u8 radio_c1_lgbuf_atune;
0235     u8 radio_c1_lgbuf_gtune;
0236     u8 radio_c1_rx_rfr1;
0237     u8 radio_c1_tx_pgapadtn;
0238     u8 radio_c1_tx_mxbgtrim;
0239     u8 radio_c2_lgbuf_atune;
0240     u8 radio_c2_lgbuf_gtune;
0241     u8 radio_c2_rx_rfr1;
0242     u8 radio_c2_tx_pgapadtn;
0243     u8 radio_c2_tx_mxbgtrim;
0244     /* PHY register values on channelswitch */
0245     struct b43_phy_n_sfo_cfg phy_regs;
0246 };
0247
0248 /* Upload the default register value table.
0249  * If "ghz5" is true, we upload the 5Ghz table. Otherwise the 2.4Ghz
0250  * table is uploaded. If "ignore_uploadflag" is true, we upload any value
0251  * and ignore the "UPLOAD" flag. */
0252 void b2055_upload_inittab(struct b43_wldev *dev,
0253               bool ghz5, bool ignore_uploadflag);
0254
0255 /* Get the NPHY Channel Switch Table entry for a channel.
0256  * Returns NULL on failure to find an entry. */
0257 const struct b43_nphy_channeltab_entry_rev2 *
0258 b43_nphy_get_chantabent_rev2(struct b43_wldev *dev, u8 channel);
0259
0260 #endif /* B43_RADIO_2055_H_ */