broadcom/b43/pio.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef B43_PIO_H_
0003 #define B43_PIO_H_
0004
0005 #include "b43.h"
0006
0007 #include <linux/interrupt.h>
0008 #include <linux/io.h>
0009 #include <linux/list.h>
0010 #include <linux/skbuff.h>
0011
0012
0013 /*** Registers for PIO queues up to revision 7. ***/
0014 /* TX queue. */
0015 #define B43_PIO_TXCTL           0x00
0016 #define  B43_PIO_TXCTL_WRITELO      0x0001
0017 #define  B43_PIO_TXCTL_WRITEHI      0x0002
0018 #define  B43_PIO_TXCTL_EOF      0x0004
0019 #define  B43_PIO_TXCTL_FREADY       0x0008
0020 #define  B43_PIO_TXCTL_FLUSHREQ     0x0020
0021 #define  B43_PIO_TXCTL_FLUSHPEND    0x0040
0022 #define  B43_PIO_TXCTL_SUSPREQ      0x0080
0023 #define  B43_PIO_TXCTL_QSUSP        0x0100
0024 #define  B43_PIO_TXCTL_COMMCNT      0xFC00
0025 #define  B43_PIO_TXCTL_COMMCNT_SHIFT    10
0026 #define B43_PIO_TXDATA          0x02
0027 #define B43_PIO_TXQBUFSIZE      0x04
0028 /* RX queue. */
0029 #define B43_PIO_RXCTL           0x00
0030 #define  B43_PIO_RXCTL_FRAMERDY     0x0001
0031 #define  B43_PIO_RXCTL_DATARDY      0x0002
0032 #define B43_PIO_RXDATA          0x02
0033
0034 /*** Registers for PIO queues revision 8 and later. ***/
0035 /* TX queue */
0036 #define B43_PIO8_TXCTL          0x00
0037 #define  B43_PIO8_TXCTL_0_7     0x00000001
0038 #define  B43_PIO8_TXCTL_8_15        0x00000002
0039 #define  B43_PIO8_TXCTL_16_23       0x00000004
0040 #define  B43_PIO8_TXCTL_24_31       0x00000008
0041 #define  B43_PIO8_TXCTL_EOF     0x00000010
0042 #define  B43_PIO8_TXCTL_FREADY      0x00000080
0043 #define  B43_PIO8_TXCTL_SUSPREQ     0x00000100
0044 #define  B43_PIO8_TXCTL_QSUSP       0x00000200
0045 #define  B43_PIO8_TXCTL_FLUSHREQ    0x00000400
0046 #define  B43_PIO8_TXCTL_FLUSHPEND   0x00000800
0047 #define B43_PIO8_TXDATA         0x04
0048 /* RX queue */
0049 #define B43_PIO8_RXCTL          0x00
0050 #define  B43_PIO8_RXCTL_FRAMERDY    0x00000001
0051 #define  B43_PIO8_RXCTL_DATARDY     0x00000002
0052 #define B43_PIO8_RXDATA         0x04
0053
0054
0055 /* The maximum number of TX-packets the HW can handle. */
0056 #define B43_PIO_MAX_NR_TXPACKETS    32
0057
0058
0059 struct b43_pio_txpacket {
0060     /* Pointer to the TX queue we belong to. */
0061     struct b43_pio_txqueue *queue;
0062     /* The TX data packet. */
0063     struct sk_buff *skb;
0064     /* Index in the (struct b43_pio_txqueue)->packets array. */
0065     u8 index;
0066
0067     struct list_head list;
0068 };
0069
0070 struct b43_pio_txqueue {
0071     struct b43_wldev *dev;
0072     u16 mmio_base;
0073
0074     /* The device queue buffer size in bytes. */
0075     u16 buffer_size;
0076     /* The number of used bytes in the device queue buffer. */
0077     u16 buffer_used;
0078     /* The number of packets that can still get queued.
0079      * This is decremented on queueing a packet and incremented
0080      * after receiving the transmit status. */
0081     u16 free_packet_slots;
0082
0083     /* True, if the mac80211 queue was stopped due to overflow at TX. */
0084     bool stopped;
0085     /* Our b43 queue index number */
0086     u8 index;
0087     /* The mac80211 QoS queue priority. */
0088     u8 queue_prio;
0089
0090     /* Buffer for TX packet meta data. */
0091     struct b43_pio_txpacket packets[B43_PIO_MAX_NR_TXPACKETS];
0092     struct list_head packets_list;
0093
0094     /* Shortcut to the 802.11 core revision. This is to
0095      * avoid horrible pointer dereferencing in the fastpaths. */
0096     u8 rev;
0097 };
0098
0099 struct b43_pio_rxqueue {
0100     struct b43_wldev *dev;
0101     u16 mmio_base;
0102
0103     /* Shortcut to the 802.11 core revision. This is to
0104      * avoid horrible pointer dereferencing in the fastpaths. */
0105     u8 rev;
0106 };
0107
0108
0109 static inline u16 b43_piotx_read16(struct b43_pio_txqueue *q, u16 offset)
0110 {
0111     return b43_read16(q->dev, q->mmio_base + offset);
0112 }
0113
0114 static inline u32 b43_piotx_read32(struct b43_pio_txqueue *q, u16 offset)
0115 {
0116     return b43_read32(q->dev, q->mmio_base + offset);
0117 }
0118
0119 static inline void b43_piotx_write16(struct b43_pio_txqueue *q,
0120                      u16 offset, u16 value)
0121 {
0122     b43_write16(q->dev, q->mmio_base + offset, value);
0123 }
0124
0125 static inline void b43_piotx_write32(struct b43_pio_txqueue *q,
0126                      u16 offset, u32 value)
0127 {
0128     b43_write32(q->dev, q->mmio_base + offset, value);
0129 }
0130
0131
0132 static inline u16 b43_piorx_read16(struct b43_pio_rxqueue *q, u16 offset)
0133 {
0134     return b43_read16(q->dev, q->mmio_base + offset);
0135 }
0136
0137 static inline u32 b43_piorx_read32(struct b43_pio_rxqueue *q, u16 offset)
0138 {
0139     return b43_read32(q->dev, q->mmio_base + offset);
0140 }
0141
0142 static inline void b43_piorx_write16(struct b43_pio_rxqueue *q,
0143                      u16 offset, u16 value)
0144 {
0145     b43_write16(q->dev, q->mmio_base + offset, value);
0146 }
0147
0148 static inline void b43_piorx_write32(struct b43_pio_rxqueue *q,
0149                      u16 offset, u32 value)
0150 {
0151     b43_write32(q->dev, q->mmio_base + offset, value);
0152 }
0153
0154
0155 int b43_pio_init(struct b43_wldev *dev);
0156 void b43_pio_free(struct b43_wldev *dev);
0157
0158 int b43_pio_tx(struct b43_wldev *dev, struct sk_buff *skb);
0159 void b43_pio_handle_txstatus(struct b43_wldev *dev,
0160                  const struct b43_txstatus *status);
0161 void b43_pio_rx(struct b43_pio_rxqueue *q);
0162
0163 void b43_pio_tx_suspend(struct b43_wldev *dev);
0164 void b43_pio_tx_resume(struct b43_wldev *dev);
0165
0166 #endif /* B43_PIO_H_ */