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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef B43_NPHY_H_
0003 #define B43_NPHY_H_
0004 
0005 #include "phy_common.h"
0006 #include "ppr.h"
0007 
0008 
0009 /* N-PHY registers. */
0010 
0011 #define B43_NPHY_BBCFG              B43_PHY_N(0x001) /* BB config */
0012 #define  B43_NPHY_BBCFG_RSTCCA          0x4000 /* Reset CCA */
0013 #define  B43_NPHY_BBCFG_RSTRX           0x8000 /* Reset RX */
0014 #define B43_NPHY_CHANNEL            B43_PHY_N(0x005) /* Channel */
0015 #define B43_NPHY_TXERR              B43_PHY_N(0x007) /* TX error */
0016 #define B43_NPHY_BANDCTL            B43_PHY_N(0x009) /* Band control */
0017 #define  B43_NPHY_BANDCTL_5GHZ          0x0001 /* Use the 5GHz band */
0018 #define B43_NPHY_4WI_ADDR           B43_PHY_N(0x00B) /* Four-wire bus address */
0019 #define B43_NPHY_4WI_DATAHI         B43_PHY_N(0x00C) /* Four-wire bus data high */
0020 #define B43_NPHY_4WI_DATALO         B43_PHY_N(0x00D) /* Four-wire bus data low */
0021 #define B43_NPHY_BIST_STAT0         B43_PHY_N(0x00E) /* Built-in self test status 0 */
0022 #define B43_NPHY_BIST_STAT1         B43_PHY_N(0x00F) /* Built-in self test status 1 */
0023 
0024 #define B43_NPHY_C1_DESPWR          B43_PHY_N(0x018) /* Core 1 desired power */
0025 #define B43_NPHY_C1_CCK_DESPWR          B43_PHY_N(0x019) /* Core 1 CCK desired power */
0026 #define B43_NPHY_C1_BCLIPBKOFF          B43_PHY_N(0x01A) /* Core 1 barely clip backoff */
0027 #define B43_NPHY_C1_CCK_BCLIPBKOFF      B43_PHY_N(0x01B) /* Core 1 CCK barely clip backoff */
0028 #define B43_NPHY_C1_CGAINI          B43_PHY_N(0x01C) /* Core 1 compute gain info */
0029 #define  B43_NPHY_C1_CGAINI_GAINBKOFF       0x001F /* Gain backoff */
0030 #define  B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT 0
0031 #define  B43_NPHY_C1_CGAINI_CLIPGBKOFF      0x03E0 /* Clip gain backoff */
0032 #define  B43_NPHY_C1_CGAINI_CLIPGBKOFF_SHIFT    5
0033 #define  B43_NPHY_C1_CGAINI_GAINSTEP        0x1C00 /* Gain step */
0034 #define  B43_NPHY_C1_CGAINI_GAINSTEP_SHIFT  10
0035 #define  B43_NPHY_C1_CGAINI_CL2DETECT       0x2000 /* Clip 2 detect mask */
0036 #define B43_NPHY_C1_CCK_CGAINI          B43_PHY_N(0x01D) /* Core 1 CCK compute gain info */
0037 #define  B43_NPHY_C1_CCK_CGAINI_GAINBKOFF   0x001F /* Gain backoff */
0038 #define  B43_NPHY_C1_CCK_CGAINI_CLIPGBKOFF  0x01E0 /* CCK barely clip gain backoff */
0039 #define B43_NPHY_C1_MINMAX_GAIN         B43_PHY_N(0x01E) /* Core 1 min/max gain */
0040 #define  B43_NPHY_C1_MINGAIN            0x00FF /* Minimum gain */
0041 #define  B43_NPHY_C1_MINGAIN_SHIFT      0
0042 #define  B43_NPHY_C1_MAXGAIN            0xFF00 /* Maximum gain */
0043 #define  B43_NPHY_C1_MAXGAIN_SHIFT      8
0044 #define B43_NPHY_C1_CCK_MINMAX_GAIN     B43_PHY_N(0x01F) /* Core 1 CCK min/max gain */
0045 #define  B43_NPHY_C1_CCK_MINGAIN        0x00FF /* Minimum gain */
0046 #define  B43_NPHY_C1_CCK_MINGAIN_SHIFT      0
0047 #define  B43_NPHY_C1_CCK_MAXGAIN        0xFF00 /* Maximum gain */
0048 #define  B43_NPHY_C1_CCK_MAXGAIN_SHIFT      8
0049 #define B43_NPHY_C1_INITGAIN            B43_PHY_N(0x020) /* Core 1 initial gain code */
0050 #define  B43_NPHY_C1_INITGAIN_EXTLNA        0x0001 /* External LNA index */
0051 #define  B43_NPHY_C1_INITGAIN_LNA       0x0006 /* LNA index */
0052 #define  B43_NPHY_C1_INITGAIN_LNAIDX_SHIFT  1
0053 #define  B43_NPHY_C1_INITGAIN_HPVGA1        0x0078 /* HPVGA1 index */
0054 #define  B43_NPHY_C1_INITGAIN_HPVGA1_SHIFT  3
0055 #define  B43_NPHY_C1_INITGAIN_HPVGA2        0x0F80 /* HPVGA2 index */
0056 #define  B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT  7
0057 #define  B43_NPHY_C1_INITGAIN_TRRX      0x1000 /* TR RX index */
0058 #define  B43_NPHY_C1_INITGAIN_TRTX      0x2000 /* TR TX index */
0059 #define B43_NPHY_REV3_C1_INITGAIN_A     B43_PHY_N(0x020)
0060 #define B43_NPHY_C1_CLIP1_HIGAIN        B43_PHY_N(0x021) /* Core 1 clip1 high gain code */
0061 #define B43_NPHY_REV3_C1_INITGAIN_B     B43_PHY_N(0x021)
0062 #define B43_NPHY_C1_CLIP1_MEDGAIN       B43_PHY_N(0x022) /* Core 1 clip1 medium gain code */
0063 #define B43_NPHY_REV3_C1_CLIP_HIGAIN_A      B43_PHY_N(0x022)
0064 #define B43_NPHY_C1_CLIP1_LOGAIN        B43_PHY_N(0x023) /* Core 1 clip1 low gain code */
0065 #define B43_NPHY_REV3_C1_CLIP_HIGAIN_B      B43_PHY_N(0x023)
0066 #define B43_NPHY_C1_CLIP2_GAIN          B43_PHY_N(0x024) /* Core 1 clip2 gain code */
0067 #define B43_NPHY_REV3_C1_CLIP_MEDGAIN_A     B43_PHY_N(0x024)
0068 #define B43_NPHY_C1_FILTERGAIN          B43_PHY_N(0x025) /* Core 1 filter gain */
0069 #define B43_NPHY_C1_LPF_QHPF_BW         B43_PHY_N(0x026) /* Core 1 LPF Q HP F bandwidth */
0070 #define B43_NPHY_C1_CLIPWBTHRES         B43_PHY_N(0x027) /* Core 1 clip wideband threshold */
0071 #define  B43_NPHY_C1_CLIPWBTHRES_CLIP2      0x003F /* Clip 2 */
0072 #define  B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT    0
0073 #define  B43_NPHY_C1_CLIPWBTHRES_CLIP1      0x0FC0 /* Clip 1 */
0074 #define  B43_NPHY_C1_CLIPWBTHRES_CLIP1_SHIFT    6
0075 #define B43_NPHY_C1_W1THRES         B43_PHY_N(0x028) /* Core 1 W1 threshold */
0076 #define B43_NPHY_C1_EDTHRES         B43_PHY_N(0x029) /* Core 1 ED threshold */
0077 #define B43_NPHY_C1_SMSIGTHRES          B43_PHY_N(0x02A) /* Core 1 small sig threshold */
0078 #define B43_NPHY_C1_NBCLIPTHRES         B43_PHY_N(0x02B) /* Core 1 NB clip threshold */
0079 #define B43_NPHY_C1_CLIP1THRES          B43_PHY_N(0x02C) /* Core 1 clip1 threshold */
0080 #define B43_NPHY_C1_CLIP2THRES          B43_PHY_N(0x02D) /* Core 1 clip2 threshold */
0081 
0082 #define B43_NPHY_C2_DESPWR          B43_PHY_N(0x02E) /* Core 2 desired power */
0083 #define B43_NPHY_C2_CCK_DESPWR          B43_PHY_N(0x02F) /* Core 2 CCK desired power */
0084 #define B43_NPHY_C2_BCLIPBKOFF          B43_PHY_N(0x030) /* Core 2 barely clip backoff */
0085 #define B43_NPHY_C2_CCK_BCLIPBKOFF      B43_PHY_N(0x031) /* Core 2 CCK barely clip backoff */
0086 #define B43_NPHY_C2_CGAINI          B43_PHY_N(0x032) /* Core 2 compute gain info */
0087 #define  B43_NPHY_C2_CGAINI_GAINBKOFF       0x001F /* Gain backoff */
0088 #define  B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT 0
0089 #define  B43_NPHY_C2_CGAINI_CLIPGBKOFF      0x03E0 /* Clip gain backoff */
0090 #define  B43_NPHY_C2_CGAINI_CLIPGBKOFF_SHIFT    5
0091 #define  B43_NPHY_C2_CGAINI_GAINSTEP        0x1C00 /* Gain step */
0092 #define  B43_NPHY_C2_CGAINI_GAINSTEP_SHIFT  10
0093 #define  B43_NPHY_C2_CGAINI_CL2DETECT       0x2000 /* Clip 2 detect mask */
0094 #define B43_NPHY_C2_CCK_CGAINI          B43_PHY_N(0x033) /* Core 2 CCK compute gain info */
0095 #define  B43_NPHY_C2_CCK_CGAINI_GAINBKOFF   0x001F /* Gain backoff */
0096 #define  B43_NPHY_C2_CCK_CGAINI_CLIPGBKOFF  0x01E0 /* CCK barely clip gain backoff */
0097 #define B43_NPHY_C2_MINMAX_GAIN         B43_PHY_N(0x034) /* Core 2 min/max gain */
0098 #define  B43_NPHY_C2_MINGAIN            0x00FF /* Minimum gain */
0099 #define  B43_NPHY_C2_MINGAIN_SHIFT      0
0100 #define  B43_NPHY_C2_MAXGAIN            0xFF00 /* Maximum gain */
0101 #define  B43_NPHY_C2_MAXGAIN_SHIFT      8
0102 #define B43_NPHY_C2_CCK_MINMAX_GAIN     B43_PHY_N(0x035) /* Core 2 CCK min/max gain */
0103 #define  B43_NPHY_C2_CCK_MINGAIN        0x00FF /* Minimum gain */
0104 #define  B43_NPHY_C2_CCK_MINGAIN_SHIFT      0
0105 #define  B43_NPHY_C2_CCK_MAXGAIN        0xFF00 /* Maximum gain */
0106 #define  B43_NPHY_C2_CCK_MAXGAIN_SHIFT      8
0107 #define B43_NPHY_C2_INITGAIN            B43_PHY_N(0x036) /* Core 2 initial gain code */
0108 #define  B43_NPHY_C2_INITGAIN_EXTLNA        0x0001 /* External LNA index */
0109 #define  B43_NPHY_C2_INITGAIN_LNA       0x0006 /* LNA index */
0110 #define  B43_NPHY_C2_INITGAIN_LNAIDX_SHIFT  1
0111 #define  B43_NPHY_C2_INITGAIN_HPVGA1        0x0078 /* HPVGA1 index */
0112 #define  B43_NPHY_C2_INITGAIN_HPVGA1_SHIFT  3
0113 #define  B43_NPHY_C2_INITGAIN_HPVGA2        0x0F80 /* HPVGA2 index */
0114 #define  B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT  7
0115 #define  B43_NPHY_C2_INITGAIN_TRRX      0x1000 /* TR RX index */
0116 #define  B43_NPHY_C2_INITGAIN_TRTX      0x2000 /* TR TX index */
0117 #define B43_NPHY_REV3_C1_CLIP_MEDGAIN_B     B43_PHY_N(0x036)
0118 #define B43_NPHY_C2_CLIP1_HIGAIN        B43_PHY_N(0x037) /* Core 2 clip1 high gain code */
0119 #define B43_NPHY_REV3_C1_CLIP_LOGAIN_A      B43_PHY_N(0x037)
0120 #define B43_NPHY_C2_CLIP1_MEDGAIN       B43_PHY_N(0x038) /* Core 2 clip1 medium gain code */
0121 #define B43_NPHY_REV3_C1_CLIP_LOGAIN_B      B43_PHY_N(0x038)
0122 #define B43_NPHY_C2_CLIP1_LOGAIN        B43_PHY_N(0x039) /* Core 2 clip1 low gain code */
0123 #define B43_NPHY_REV3_C1_CLIP2_GAIN_A       B43_PHY_N(0x039)
0124 #define B43_NPHY_C2_CLIP2_GAIN          B43_PHY_N(0x03A) /* Core 2 clip2 gain code */
0125 #define B43_NPHY_REV3_C1_CLIP2_GAIN_B       B43_PHY_N(0x03A)
0126 #define B43_NPHY_C2_FILTERGAIN          B43_PHY_N(0x03B) /* Core 2 filter gain */
0127 #define B43_NPHY_C2_LPF_QHPF_BW         B43_PHY_N(0x03C) /* Core 2 LPF Q HP F bandwidth */
0128 #define B43_NPHY_C2_CLIPWBTHRES         B43_PHY_N(0x03D) /* Core 2 clip wideband threshold */
0129 #define  B43_NPHY_C2_CLIPWBTHRES_CLIP2      0x003F /* Clip 2 */
0130 #define  B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT    0
0131 #define  B43_NPHY_C2_CLIPWBTHRES_CLIP1      0x0FC0 /* Clip 1 */
0132 #define  B43_NPHY_C2_CLIPWBTHRES_CLIP1_SHIFT    6
0133 #define B43_NPHY_C2_W1THRES         B43_PHY_N(0x03E) /* Core 2 W1 threshold */
0134 #define B43_NPHY_C2_EDTHRES         B43_PHY_N(0x03F) /* Core 2 ED threshold */
0135 #define B43_NPHY_C2_SMSIGTHRES          B43_PHY_N(0x040) /* Core 2 small sig threshold */
0136 #define B43_NPHY_C2_NBCLIPTHRES         B43_PHY_N(0x041) /* Core 2 NB clip threshold */
0137 #define B43_NPHY_C2_CLIP1THRES          B43_PHY_N(0x042) /* Core 2 clip1 threshold */
0138 #define B43_NPHY_C2_CLIP2THRES          B43_PHY_N(0x043) /* Core 2 clip2 threshold */
0139 
0140 #define B43_NPHY_CRS_THRES1         B43_PHY_N(0x044) /* CRS threshold 1 */
0141 #define B43_NPHY_CRS_THRES2         B43_PHY_N(0x045) /* CRS threshold 2 */
0142 #define B43_NPHY_CRS_THRES3         B43_PHY_N(0x046) /* CRS threshold 3 */
0143 #define B43_NPHY_CRSCTL             B43_PHY_N(0x047) /* CRS control */
0144 #define B43_NPHY_DCFADDR            B43_PHY_N(0x048) /* DC filter address */
0145 #define B43_NPHY_RXF20_NUM0         B43_PHY_N(0x049) /* RX filter 20 numerator 0 */
0146 #define B43_NPHY_RXF20_NUM1         B43_PHY_N(0x04A) /* RX filter 20 numerator 1 */
0147 #define B43_NPHY_RXF20_NUM2         B43_PHY_N(0x04B) /* RX filter 20 numerator 2 */
0148 #define B43_NPHY_RXF20_DENOM0           B43_PHY_N(0x04C) /* RX filter 20 denominator 0 */
0149 #define B43_NPHY_RXF20_DENOM1           B43_PHY_N(0x04D) /* RX filter 20 denominator 1 */
0150 #define B43_NPHY_RXF20_NUM10            B43_PHY_N(0x04E) /* RX filter 20 numerator 10 */
0151 #define B43_NPHY_RXF20_NUM11            B43_PHY_N(0x04F) /* RX filter 20 numerator 11 */
0152 #define B43_NPHY_RXF20_NUM12            B43_PHY_N(0x050) /* RX filter 20 numerator 12 */
0153 #define B43_NPHY_RXF20_DENOM10          B43_PHY_N(0x051) /* RX filter 20 denominator 10 */
0154 #define B43_NPHY_RXF20_DENOM11          B43_PHY_N(0x052) /* RX filter 20 denominator 11 */
0155 #define B43_NPHY_RXF40_NUM0         B43_PHY_N(0x053) /* RX filter 40 numerator 0 */
0156 #define B43_NPHY_RXF40_NUM1         B43_PHY_N(0x054) /* RX filter 40 numerator 1 */
0157 #define B43_NPHY_RXF40_NUM2         B43_PHY_N(0x055) /* RX filter 40 numerator 2 */
0158 #define B43_NPHY_RXF40_DENOM0           B43_PHY_N(0x056) /* RX filter 40 denominator 0 */
0159 #define B43_NPHY_RXF40_DENOM1           B43_PHY_N(0x057) /* RX filter 40 denominator 1 */
0160 #define B43_NPHY_RXF40_NUM10            B43_PHY_N(0x058) /* RX filter 40 numerator 10 */
0161 #define B43_NPHY_RXF40_NUM11            B43_PHY_N(0x059) /* RX filter 40 numerator 11 */
0162 #define B43_NPHY_RXF40_NUM12            B43_PHY_N(0x05A) /* RX filter 40 numerator 12 */
0163 #define B43_NPHY_RXF40_DENOM10          B43_PHY_N(0x05B) /* RX filter 40 denominator 10 */
0164 #define B43_NPHY_RXF40_DENOM11          B43_PHY_N(0x05C) /* RX filter 40 denominator 11 */
0165 #define B43_NPHY_PPROC_RSTLEN           B43_PHY_N(0x060) /* Packet processing reset length */
0166 #define B43_NPHY_INITCARR_DLEN          B43_PHY_N(0x061) /* Initial carrier detection length */
0167 #define B43_NPHY_CLIP1CARR_DLEN         B43_PHY_N(0x062) /* Clip1 carrier detection length */
0168 #define B43_NPHY_CLIP2CARR_DLEN         B43_PHY_N(0x063) /* Clip2 carrier detection length */
0169 #define B43_NPHY_INITGAIN_SLEN          B43_PHY_N(0x064) /* Initial gain settle length */
0170 #define B43_NPHY_CLIP1GAIN_SLEN         B43_PHY_N(0x065) /* Clip1 gain settle length */
0171 #define B43_NPHY_CLIP2GAIN_SLEN         B43_PHY_N(0x066) /* Clip2 gain settle length */
0172 #define B43_NPHY_PACKGAIN_SLEN          B43_PHY_N(0x067) /* Packet gain settle length */
0173 #define B43_NPHY_CARRSRC_TLEN           B43_PHY_N(0x068) /* Carrier search timeout length */
0174 #define B43_NPHY_TISRC_TLEN         B43_PHY_N(0x069) /* Timing search timeout length */
0175 #define B43_NPHY_ENDROP_TLEN            B43_PHY_N(0x06A) /* Energy drop timeout length */
0176 #define B43_NPHY_CLIP1_NBDWELL_LEN      B43_PHY_N(0x06B) /* Clip1 NB dwell length */
0177 #define B43_NPHY_CLIP2_NBDWELL_LEN      B43_PHY_N(0x06C) /* Clip2 NB dwell length */
0178 #define B43_NPHY_W1CLIP1_DWELL_LEN      B43_PHY_N(0x06D) /* W1 clip1 dwell length */
0179 #define B43_NPHY_W1CLIP2_DWELL_LEN      B43_PHY_N(0x06E) /* W1 clip2 dwell length */
0180 #define B43_NPHY_W2CLIP1_DWELL_LEN      B43_PHY_N(0x06F) /* W2 clip1 dwell length */
0181 #define B43_NPHY_PLOAD_CSENSE_EXTLEN        B43_PHY_N(0x070) /* Payload carrier sense extension length */
0182 #define B43_NPHY_EDROP_CSENSE_EXTLEN        B43_PHY_N(0x071) /* Energy drop carrier sense extension length */
0183 #define B43_NPHY_TABLE_ADDR         B43_PHY_N(0x072) /* Table address */
0184 #define B43_NPHY_TABLE_DATALO           B43_PHY_N(0x073) /* Table data low */
0185 #define B43_NPHY_TABLE_DATAHI           B43_PHY_N(0x074) /* Table data high */
0186 #define B43_NPHY_WWISE_LENIDX           B43_PHY_N(0x075) /* WWiSE length index */
0187 #define B43_NPHY_TGNSYNC_LENIDX         B43_PHY_N(0x076) /* TGNsync length index */
0188 #define B43_NPHY_TXMACIF_HOLDOFF        B43_PHY_N(0x077) /* TX MAC IF Hold off */
0189 #define B43_NPHY_RFCTL_CMD          B43_PHY_N(0x078) /* RF control (command) */
0190 #define  B43_NPHY_RFCTL_CMD_START       0x0001 /* Start sequence */
0191 #define  B43_NPHY_RFCTL_CMD_RXTX        0x0002 /* RX/TX */
0192 #define  B43_NPHY_RFCTL_CMD_CORESEL     0x0038 /* Core select */
0193 #define  B43_NPHY_RFCTL_CMD_CORESEL_SHIFT   3
0194 #define  B43_NPHY_RFCTL_CMD_PORFORCE        0x0040 /* POR force */
0195 #define  B43_NPHY_RFCTL_CMD_OEPORFORCE      0x0080 /* OE POR force */
0196 #define  B43_NPHY_RFCTL_CMD_RXEN        0x0100 /* RX enable */
0197 #define  B43_NPHY_RFCTL_CMD_TXEN        0x0200 /* TX enable */
0198 #define  B43_NPHY_RFCTL_CMD_CHIP0PU     0x0400 /* Chip0 PU */
0199 #define  B43_NPHY_RFCTL_CMD_EN          0x0800 /* Radio enabled */
0200 #define  B43_NPHY_RFCTL_CMD_SEQENCORE       0xF000 /* Seq en core */
0201 #define  B43_NPHY_RFCTL_CMD_SEQENCORE_SHIFT 12
0202 #define B43_NPHY_RFCTL_RSSIO1           B43_PHY_N(0x07A) /* RF control (RSSI others 1) */
0203 #define  B43_NPHY_RFCTL_RSSIO1_RXPD     0x0001 /* RX PD */
0204 #define  B43_NPHY_RFCTL_RSSIO1_TXPD     0x0002 /* TX PD */
0205 #define  B43_NPHY_RFCTL_RSSIO1_PAPD     0x0004 /* PA PD */
0206 #define  B43_NPHY_RFCTL_RSSIO1_RSSICTL      0x0030 /* RSSI control */
0207 #define  B43_NPHY_RFCTL_RSSIO1_LPFBW        0x00C0 /* LPF bandwidth */
0208 #define  B43_NPHY_RFCTL_RSSIO1_HPFBWHI      0x0100 /* HPF bandwidth high */
0209 #define  B43_NPHY_RFCTL_RSSIO1_HIQDISCO     0x0200 /* HIQ dis core */
0210 #define B43_NPHY_RFCTL_RXG1         B43_PHY_N(0x07B) /* RF control (RX gain 1) */
0211 #define B43_NPHY_RFCTL_TXG1         B43_PHY_N(0x07C) /* RF control (TX gain 1) */
0212 #define B43_NPHY_RFCTL_RSSIO2           B43_PHY_N(0x07D) /* RF control (RSSI others 2) */
0213 #define  B43_NPHY_RFCTL_RSSIO2_RXPD     0x0001 /* RX PD */
0214 #define  B43_NPHY_RFCTL_RSSIO2_TXPD     0x0002 /* TX PD */
0215 #define  B43_NPHY_RFCTL_RSSIO2_PAPD     0x0004 /* PA PD */
0216 #define  B43_NPHY_RFCTL_RSSIO2_RSSICTL      0x0030 /* RSSI control */
0217 #define  B43_NPHY_RFCTL_RSSIO2_LPFBW        0x00C0 /* LPF bandwidth */
0218 #define  B43_NPHY_RFCTL_RSSIO2_HPFBWHI      0x0100 /* HPF bandwidth high */
0219 #define  B43_NPHY_RFCTL_RSSIO2_HIQDISCO     0x0200 /* HIQ dis core */
0220 #define B43_NPHY_RFCTL_RXG2         B43_PHY_N(0x07E) /* RF control (RX gain 2) */
0221 #define B43_NPHY_RFCTL_TXG2         B43_PHY_N(0x07F) /* RF control (TX gain 2) */
0222 #define B43_NPHY_RFCTL_RSSIO3           B43_PHY_N(0x080) /* RF control (RSSI others 3) */
0223 #define  B43_NPHY_RFCTL_RSSIO3_RXPD     0x0001 /* RX PD */
0224 #define  B43_NPHY_RFCTL_RSSIO3_TXPD     0x0002 /* TX PD */
0225 #define  B43_NPHY_RFCTL_RSSIO3_PAPD     0x0004 /* PA PD */
0226 #define  B43_NPHY_RFCTL_RSSIO3_RSSICTL      0x0030 /* RSSI control */
0227 #define  B43_NPHY_RFCTL_RSSIO3_LPFBW        0x00C0 /* LPF bandwidth */
0228 #define  B43_NPHY_RFCTL_RSSIO3_HPFBWHI      0x0100 /* HPF bandwidth high */
0229 #define  B43_NPHY_RFCTL_RSSIO3_HIQDISCO     0x0200 /* HIQ dis core */
0230 #define B43_NPHY_RFCTL_RXG3         B43_PHY_N(0x081) /* RF control (RX gain 3) */
0231 #define B43_NPHY_RFCTL_TXG3         B43_PHY_N(0x082) /* RF control (TX gain 3) */
0232 #define B43_NPHY_RFCTL_RSSIO4           B43_PHY_N(0x083) /* RF control (RSSI others 4) */
0233 #define  B43_NPHY_RFCTL_RSSIO4_RXPD     0x0001 /* RX PD */
0234 #define  B43_NPHY_RFCTL_RSSIO4_TXPD     0x0002 /* TX PD */
0235 #define  B43_NPHY_RFCTL_RSSIO4_PAPD     0x0004 /* PA PD */
0236 #define  B43_NPHY_RFCTL_RSSIO4_RSSICTL      0x0030 /* RSSI control */
0237 #define  B43_NPHY_RFCTL_RSSIO4_LPFBW        0x00C0 /* LPF bandwidth */
0238 #define  B43_NPHY_RFCTL_RSSIO4_HPFBWHI      0x0100 /* HPF bandwidth high */
0239 #define  B43_NPHY_RFCTL_RSSIO4_HIQDISCO     0x0200 /* HIQ dis core */
0240 #define B43_NPHY_RFCTL_RXG4         B43_PHY_N(0x084) /* RF control (RX gain 4) */
0241 #define B43_NPHY_RFCTL_TXG4         B43_PHY_N(0x085) /* RF control (TX gain 4) */
0242 #define B43_NPHY_C1_TXIQ_COMP_OFF       B43_PHY_N(0x087) /* Core 1 TX I/Q comp offset */
0243 #define B43_NPHY_C2_TXIQ_COMP_OFF       B43_PHY_N(0x088) /* Core 2 TX I/Q comp offset */
0244 #define B43_NPHY_C1_TXCTL           B43_PHY_N(0x08B) /* Core 1 TX control */
0245 #define B43_NPHY_C2_TXCTL           B43_PHY_N(0x08C) /* Core 2 TX control */
0246 #define B43_NPHY_AFECTL_OVER1           B43_PHY_N(0x08F) /* AFE control override 1 */
0247 #define B43_NPHY_SCRAM_SIGCTL           B43_PHY_N(0x090) /* Scram signal control */
0248 #define  B43_NPHY_SCRAM_SIGCTL_INITST       0x007F /* Initial state value */
0249 #define  B43_NPHY_SCRAM_SIGCTL_INITST_SHIFT 0
0250 #define  B43_NPHY_SCRAM_SIGCTL_SCM      0x0080 /* Scram control mode */
0251 #define  B43_NPHY_SCRAM_SIGCTL_SICE     0x0100 /* Scram index control enable */
0252 #define  B43_NPHY_SCRAM_SIGCTL_START        0xFE00 /* Scram start bit */
0253 #define  B43_NPHY_SCRAM_SIGCTL_START_SHIFT  9
0254 #define B43_NPHY_RFCTL_INTC1            B43_PHY_N(0x091) /* RF control (intc 1) */
0255 #define B43_NPHY_RFCTL_INTC2            B43_PHY_N(0x092) /* RF control (intc 2) */
0256 #define B43_NPHY_RFCTL_INTC3            B43_PHY_N(0x093) /* RF control (intc 3) */
0257 #define B43_NPHY_RFCTL_INTC4            B43_PHY_N(0x094) /* RF control (intc 4) */
0258 #define B43_NPHY_NRDTO_WWISE            B43_PHY_N(0x095) /* # datatones WWiSE */
0259 #define B43_NPHY_NRDTO_TGNSYNC          B43_PHY_N(0x096) /* # datatones TGNsync */
0260 #define B43_NPHY_SIGFMOD_WWISE          B43_PHY_N(0x097) /* Signal field mod WWiSE */
0261 #define B43_NPHY_LEG_SIGFMOD_11N        B43_PHY_N(0x098) /* Legacy signal field mod 11n */
0262 #define B43_NPHY_HT_SIGFMOD_11N         B43_PHY_N(0x099) /* HT signal field mod 11n */
0263 #define B43_NPHY_C1_RXIQ_COMPA0         B43_PHY_N(0x09A) /* Core 1 RX I/Q comp A0 */
0264 #define B43_NPHY_C1_RXIQ_COMPB0         B43_PHY_N(0x09B) /* Core 1 RX I/Q comp B0 */
0265 #define B43_NPHY_C2_RXIQ_COMPA1         B43_PHY_N(0x09C) /* Core 2 RX I/Q comp A1 */
0266 #define B43_NPHY_C2_RXIQ_COMPB1         B43_PHY_N(0x09D) /* Core 2 RX I/Q comp B1 */
0267 #define B43_NPHY_RXCTL              B43_PHY_N(0x0A0) /* RX control */
0268 #define  B43_NPHY_RXCTL_BSELU20         0x0010 /* Band select upper 20 */
0269 #define  B43_NPHY_RXCTL_RIFSEN          0x0080 /* RIFS enable */
0270 #define B43_NPHY_RFSEQMODE          B43_PHY_N(0x0A1) /* RF seq mode */
0271 #define  B43_NPHY_RFSEQMODE_CAOVER      0x0001 /* Core active override */
0272 #define  B43_NPHY_RFSEQMODE_TROVER      0x0002 /* Trigger override */
0273 #define B43_NPHY_RFSEQCA            B43_PHY_N(0x0A2) /* RF seq core active */
0274 #define  B43_NPHY_RFSEQCA_TXEN          0x000F /* TX enable */
0275 #define  B43_NPHY_RFSEQCA_TXEN_SHIFT        0
0276 #define  B43_NPHY_RFSEQCA_RXEN          0x00F0 /* RX enable */
0277 #define  B43_NPHY_RFSEQCA_RXEN_SHIFT        4
0278 #define  B43_NPHY_RFSEQCA_TXDIS         0x0F00 /* TX disable */
0279 #define  B43_NPHY_RFSEQCA_TXDIS_SHIFT       8
0280 #define  B43_NPHY_RFSEQCA_RXDIS         0xF000 /* RX disable */
0281 #define  B43_NPHY_RFSEQCA_RXDIS_SHIFT       12
0282 #define B43_NPHY_RFSEQTR            B43_PHY_N(0x0A3) /* RF seq trigger */
0283 #define  B43_NPHY_RFSEQTR_RX2TX         0x0001 /* RX2TX */
0284 #define  B43_NPHY_RFSEQTR_TX2RX         0x0002 /* TX2RX */
0285 #define  B43_NPHY_RFSEQTR_UPGH          0x0004 /* Update gain H */
0286 #define  B43_NPHY_RFSEQTR_UPGL          0x0008 /* Update gain L */
0287 #define  B43_NPHY_RFSEQTR_UPGU          0x0010 /* Update gain U */
0288 #define  B43_NPHY_RFSEQTR_RST2RX        0x0020 /* Reset to RX */
0289 #define B43_NPHY_RFSEQST            B43_PHY_N(0x0A4) /* RF seq status. Values same as trigger. */
0290 #define B43_NPHY_AFECTL_OVER            B43_PHY_N(0x0A5) /* AFE control override */
0291 #define B43_NPHY_AFECTL_C1          B43_PHY_N(0x0A6) /* AFE control core 1 */
0292 #define B43_NPHY_AFECTL_C2          B43_PHY_N(0x0A7) /* AFE control core 2 */
0293 #define B43_NPHY_AFECTL_C3          B43_PHY_N(0x0A8) /* AFE control core 3 */
0294 #define B43_NPHY_AFECTL_C4          B43_PHY_N(0x0A9) /* AFE control core 4 */
0295 #define B43_NPHY_AFECTL_DACGAIN1        B43_PHY_N(0x0AA) /* AFE control DAC gain 1 */
0296 #define B43_NPHY_AFECTL_DACGAIN2        B43_PHY_N(0x0AB) /* AFE control DAC gain 2 */
0297 #define B43_NPHY_AFECTL_DACGAIN3        B43_PHY_N(0x0AC) /* AFE control DAC gain 3 */
0298 #define B43_NPHY_AFECTL_DACGAIN4        B43_PHY_N(0x0AD) /* AFE control DAC gain 4 */
0299 #define B43_NPHY_STR_ADDR1          B43_PHY_N(0x0AE) /* STR address 1 */
0300 #define B43_NPHY_STR_ADDR2          B43_PHY_N(0x0AF) /* STR address 2 */
0301 #define B43_NPHY_CLASSCTL           B43_PHY_N(0x0B0) /* Classifier control */
0302 #define  B43_NPHY_CLASSCTL_CCKEN        0x0001 /* CCK enable */
0303 #define  B43_NPHY_CLASSCTL_OFDMEN       0x0002 /* OFDM enable */
0304 #define  B43_NPHY_CLASSCTL_WAITEDEN     0x0004 /* Waited enable */
0305 #define B43_NPHY_IQFLIP             B43_PHY_N(0x0B1) /* I/Q flip */
0306 #define  B43_NPHY_IQFLIP_ADC1           0x0001 /* ADC1 */
0307 #define  B43_NPHY_IQFLIP_ADC2           0x0010 /* ADC2 */
0308 #define B43_NPHY_SISO_SNR_THRES         B43_PHY_N(0x0B2) /* SISO SNR threshold */
0309 #define B43_NPHY_SIGMA_N_MULT           B43_PHY_N(0x0B3) /* Sigma N multiplier */
0310 #define B43_NPHY_TXMACDELAY         B43_PHY_N(0x0B4) /* TX MAC delay */
0311 #define B43_NPHY_TXFRAMEDELAY           B43_PHY_N(0x0B5) /* TX frame delay */
0312 #define B43_NPHY_MLPARM             B43_PHY_N(0x0B6) /* ML parameters */
0313 #define B43_NPHY_MLCTL              B43_PHY_N(0x0B7) /* ML control */
0314 #define B43_NPHY_WWISE_20NCYCDAT        B43_PHY_N(0x0B8) /* WWiSE 20 N cyc data */
0315 #define B43_NPHY_WWISE_40NCYCDAT        B43_PHY_N(0x0B9) /* WWiSE 40 N cyc data */
0316 #define B43_NPHY_TGNSYNC_20NCYCDAT      B43_PHY_N(0x0BA) /* TGNsync 20 N cyc data */
0317 #define B43_NPHY_TGNSYNC_40NCYCDAT      B43_PHY_N(0x0BB) /* TGNsync 40 N cyc data */
0318 #define B43_NPHY_INITSWIZP          B43_PHY_N(0x0BC) /* Initial swizzle pattern */
0319 #define B43_NPHY_TXTAILCNT          B43_PHY_N(0x0BD) /* TX tail count value */
0320 #define B43_NPHY_BPHY_CTL1          B43_PHY_N(0x0BE) /* B PHY control 1 */
0321 #define B43_NPHY_BPHY_CTL2          B43_PHY_N(0x0BF) /* B PHY control 2 */
0322 #define  B43_NPHY_BPHY_CTL2_LUT         0x001F /* LUT index */
0323 #define  B43_NPHY_BPHY_CTL2_LUT_SHIFT       0
0324 #define  B43_NPHY_BPHY_CTL2_MACDEL      0x7FE0 /* MAC delay */
0325 #define  B43_NPHY_BPHY_CTL2_MACDEL_SHIFT    5
0326 #define B43_NPHY_IQLOCAL_CMD            B43_PHY_N(0x0C0) /* I/Q LO cal command */
0327 #define  B43_NPHY_IQLOCAL_CMD_EN        0x8000
0328 #define B43_NPHY_IQLOCAL_CMDNNUM        B43_PHY_N(0x0C1) /* I/Q LO cal command N num */
0329 #define B43_NPHY_IQLOCAL_CMDGCTL        B43_PHY_N(0x0C2) /* I/Q LO cal command G control */
0330 #define B43_NPHY_SAMP_CMD           B43_PHY_N(0x0C3) /* Sample command */
0331 #define  B43_NPHY_SAMP_CMD_STOP         0x0002 /* Stop */
0332 #define B43_NPHY_SAMP_LOOPCNT           B43_PHY_N(0x0C4) /* Sample loop count */
0333 #define B43_NPHY_SAMP_WAITCNT           B43_PHY_N(0x0C5) /* Sample wait count */
0334 #define B43_NPHY_SAMP_DEPCNT            B43_PHY_N(0x0C6) /* Sample depth count */
0335 #define B43_NPHY_SAMP_STAT          B43_PHY_N(0x0C7) /* Sample status */
0336 #define B43_NPHY_GPIO_LOOEN         B43_PHY_N(0x0C8) /* GPIO low out enable */
0337 #define B43_NPHY_GPIO_HIOEN         B43_PHY_N(0x0C9) /* GPIO high out enable */
0338 #define B43_NPHY_GPIO_SEL           B43_PHY_N(0x0CA) /* GPIO select */
0339 #define B43_NPHY_GPIO_CLKCTL            B43_PHY_N(0x0CB) /* GPIO clock control */
0340 #define B43_NPHY_TXF_20CO_AS0           B43_PHY_N(0x0CC) /* TX filter 20 coeff A stage 0 */
0341 #define B43_NPHY_TXF_20CO_AS1           B43_PHY_N(0x0CD) /* TX filter 20 coeff A stage 1 */
0342 #define B43_NPHY_TXF_20CO_AS2           B43_PHY_N(0x0CE) /* TX filter 20 coeff A stage 2 */
0343 #define B43_NPHY_TXF_20CO_B32S0         B43_PHY_N(0x0CF) /* TX filter 20 coeff B32 stage 0 */
0344 #define B43_NPHY_TXF_20CO_B1S0          B43_PHY_N(0x0D0) /* TX filter 20 coeff B1 stage 0 */
0345 #define B43_NPHY_TXF_20CO_B32S1         B43_PHY_N(0x0D1) /* TX filter 20 coeff B32 stage 1 */
0346 #define B43_NPHY_TXF_20CO_B1S1          B43_PHY_N(0x0D2) /* TX filter 20 coeff B1 stage 1 */
0347 #define B43_NPHY_TXF_20CO_B32S2         B43_PHY_N(0x0D3) /* TX filter 20 coeff B32 stage 2 */
0348 #define B43_NPHY_TXF_20CO_B1S2          B43_PHY_N(0x0D4) /* TX filter 20 coeff B1 stage 2 */
0349 #define B43_NPHY_SIGFLDTOL          B43_PHY_N(0x0D5) /* Signal fld tolerance */
0350 #define B43_NPHY_TXSERFLD           B43_PHY_N(0x0D6) /* TX service field */
0351 #define B43_NPHY_AFESEQ_RX2TX_PUD       B43_PHY_N(0x0D7) /* AFE seq RX2TX power up/down delay */
0352 #define B43_NPHY_AFESEQ_TX2RX_PUD       B43_PHY_N(0x0D8) /* AFE seq TX2RX power up/down delay */
0353 #define B43_NPHY_TGNSYNC_SCRAMI0        B43_PHY_N(0x0D9) /* TGNsync scram init 0 */
0354 #define B43_NPHY_TGNSYNC_SCRAMI1        B43_PHY_N(0x0DA) /* TGNsync scram init 1 */
0355 #define B43_NPHY_INITSWIZPATTLEG        B43_PHY_N(0x0DB) /* Initial swizzle pattern leg */
0356 #define B43_NPHY_BPHY_CTL3          B43_PHY_N(0x0DC) /* B PHY control 3 */
0357 #define  B43_NPHY_BPHY_CTL3_SCALE       0x00FF /* Scale */
0358 #define  B43_NPHY_BPHY_CTL3_SCALE_SHIFT     0
0359 #define  B43_NPHY_BPHY_CTL3_FSC         0xFF00 /* Frame start count value */
0360 #define  B43_NPHY_BPHY_CTL3_FSC_SHIFT       8
0361 #define B43_NPHY_BPHY_CTL4          B43_PHY_N(0x0DD) /* B PHY control 4 */
0362 #define B43_NPHY_C1_TXBBMULT            B43_PHY_N(0x0DE) /* Core 1 TX BB multiplier */
0363 #define B43_NPHY_C2_TXBBMULT            B43_PHY_N(0x0DF) /* Core 2 TX BB multiplier */
0364 #define B43_NPHY_TXF_40CO_AS0           B43_PHY_N(0x0E1) /* TX filter 40 coeff A stage 0 */
0365 #define B43_NPHY_TXF_40CO_AS1           B43_PHY_N(0x0E2) /* TX filter 40 coeff A stage 1 */
0366 #define B43_NPHY_TXF_40CO_AS2           B43_PHY_N(0x0E3) /* TX filter 40 coeff A stage 2 */
0367 #define B43_NPHY_TXF_40CO_B32S0         B43_PHY_N(0x0E4) /* TX filter 40 coeff B32 stage 0 */
0368 #define B43_NPHY_TXF_40CO_B1S0          B43_PHY_N(0x0E5) /* TX filter 40 coeff B1 stage 0 */
0369 #define B43_NPHY_TXF_40CO_B32S1         B43_PHY_N(0x0E6) /* TX filter 40 coeff B32 stage 1 */
0370 #define B43_NPHY_TXF_40CO_B1S1          B43_PHY_N(0x0E7) /* TX filter 40 coeff B1 stage 1 */
0371 #define B43_NPHY_REV3_RFCTL_OVER0       B43_PHY_N(0x0E7)
0372 #define B43_NPHY_TXF_40CO_B32S2         B43_PHY_N(0x0E8) /* TX filter 40 coeff B32 stage 2 */
0373 #define B43_NPHY_TXF_40CO_B1S2          B43_PHY_N(0x0E9) /* TX filter 40 coeff B1 stage 2 */
0374 #define B43_NPHY_BIST_STAT2         B43_PHY_N(0x0EA) /* BIST status 2 */
0375 #define B43_NPHY_BIST_STAT3         B43_PHY_N(0x0EB) /* BIST status 3 */
0376 #define B43_NPHY_RFCTL_OVER         B43_PHY_N(0x0EC) /* RF control override */
0377 #define B43_NPHY_REV3_RFCTL_OVER1       B43_PHY_N(0x0EC)
0378 #define B43_NPHY_MIMOCFG            B43_PHY_N(0x0ED) /* MIMO config */
0379 #define  B43_NPHY_MIMOCFG_GFMIX         0x0004 /* Greenfield or mixed mode */
0380 #define  B43_NPHY_MIMOCFG_AUTO          0x0100 /* Greenfield/mixed mode auto */
0381 #define B43_NPHY_RADAR_BLNKCTL          B43_PHY_N(0x0EE) /* Radar blank control */
0382 #define B43_NPHY_A0RADAR_FIFOCTL        B43_PHY_N(0x0EF) /* Antenna 0 radar FIFO control */
0383 #define B43_NPHY_A1RADAR_FIFOCTL        B43_PHY_N(0x0F0) /* Antenna 1 radar FIFO control */
0384 #define B43_NPHY_A0RADAR_FIFODAT        B43_PHY_N(0x0F1) /* Antenna 0 radar FIFO data */
0385 #define B43_NPHY_A1RADAR_FIFODAT        B43_PHY_N(0x0F2) /* Antenna 1 radar FIFO data */
0386 #define B43_NPHY_RADAR_THRES0           B43_PHY_N(0x0F3) /* Radar threshold 0 */
0387 #define B43_NPHY_RADAR_THRES1           B43_PHY_N(0x0F4) /* Radar threshold 1 */
0388 #define B43_NPHY_RADAR_THRES0R          B43_PHY_N(0x0F5) /* Radar threshold 0R */
0389 #define B43_NPHY_RADAR_THRES1R          B43_PHY_N(0x0F6) /* Radar threshold 1R */
0390 #define B43_NPHY_CSEN_20IN40_DLEN       B43_PHY_N(0x0F7) /* Carrier sense 20 in 40 dwell length */
0391 #define B43_NPHY_RFCTL_LUT_TRSW_LO1     B43_PHY_N(0x0F8) /* RF control LUT TRSW lower 1 */
0392 #define B43_NPHY_RFCTL_LUT_TRSW_UP1     B43_PHY_N(0x0F9) /* RF control LUT TRSW upper 1 */
0393 #define B43_NPHY_RFCTL_LUT_TRSW_LO2     B43_PHY_N(0x0FA) /* RF control LUT TRSW lower 2 */
0394 #define B43_NPHY_RFCTL_LUT_TRSW_UP2     B43_PHY_N(0x0FB) /* RF control LUT TRSW upper 2 */
0395 #define B43_NPHY_RFCTL_LUT_TRSW_LO3     B43_PHY_N(0x0FC) /* RF control LUT TRSW lower 3 */
0396 #define B43_NPHY_RFCTL_LUT_TRSW_UP3     B43_PHY_N(0x0FD) /* RF control LUT TRSW upper 3 */
0397 #define B43_NPHY_RFCTL_LUT_TRSW_LO4     B43_PHY_N(0x0FE) /* RF control LUT TRSW lower 4 */
0398 #define B43_NPHY_RFCTL_LUT_TRSW_UP4     B43_PHY_N(0x0FF) /* RF control LUT TRSW upper 4 */
0399 #define B43_NPHY_RFCTL_LUT_LNAPA1       B43_PHY_N(0x100) /* RF control LUT LNA PA 1 */
0400 #define B43_NPHY_RFCTL_LUT_LNAPA2       B43_PHY_N(0x101) /* RF control LUT LNA PA 2 */
0401 #define B43_NPHY_RFCTL_LUT_LNAPA3       B43_PHY_N(0x102) /* RF control LUT LNA PA 3 */
0402 #define B43_NPHY_RFCTL_LUT_LNAPA4       B43_PHY_N(0x103) /* RF control LUT LNA PA 4 */
0403 #define B43_NPHY_TGNSYNC_CRCM0          B43_PHY_N(0x104) /* TGNsync CRC mask 0 */
0404 #define B43_NPHY_TGNSYNC_CRCM1          B43_PHY_N(0x105) /* TGNsync CRC mask 1 */
0405 #define B43_NPHY_TGNSYNC_CRCM2          B43_PHY_N(0x106) /* TGNsync CRC mask 2 */
0406 #define B43_NPHY_TGNSYNC_CRCM3          B43_PHY_N(0x107) /* TGNsync CRC mask 3 */
0407 #define B43_NPHY_TGNSYNC_CRCM4          B43_PHY_N(0x108) /* TGNsync CRC mask 4 */
0408 #define B43_NPHY_CRCPOLY            B43_PHY_N(0x109) /* CRC polynomial */
0409 #define B43_NPHY_SIGCNT             B43_PHY_N(0x10A) /* # sig count */
0410 #define B43_NPHY_SIGSTARTBIT_CTL        B43_PHY_N(0x10B) /* Sig start bit control */
0411 #define B43_NPHY_CRCPOLY_ORDER          B43_PHY_N(0x10C) /* CRC polynomial order */
0412 #define B43_NPHY_RFCTL_CST0         B43_PHY_N(0x10D) /* RF control core swap table 0 */
0413 #define B43_NPHY_RFCTL_CST1         B43_PHY_N(0x10E) /* RF control core swap table 1 */
0414 #define B43_NPHY_RFCTL_CST2O            B43_PHY_N(0x10F) /* RF control core swap table 2 + others */
0415 #define B43_NPHY_BPHY_CTL5          B43_PHY_N(0x111) /* B PHY control 5 */
0416 #define B43_NPHY_RFSEQ_LPFBW            B43_PHY_N(0x112) /* RF seq LPF bandwidth */
0417 #define B43_NPHY_TSSIBIAS1          B43_PHY_N(0x114) /* TSSI bias val 1 */
0418 #define B43_NPHY_TSSIBIAS2          B43_PHY_N(0x115) /* TSSI bias val 2 */
0419 #define  B43_NPHY_TSSIBIAS_BIAS         0x00FF /* Bias */
0420 #define  B43_NPHY_TSSIBIAS_BIAS_SHIFT       0
0421 #define  B43_NPHY_TSSIBIAS_VAL          0xFF00 /* Value */
0422 #define  B43_NPHY_TSSIBIAS_VAL_SHIFT        8
0423 #define B43_NPHY_ESTPWR1            B43_PHY_N(0x118) /* Estimated power 1 */
0424 #define B43_NPHY_ESTPWR2            B43_PHY_N(0x119) /* Estimated power 2 */
0425 #define  B43_NPHY_ESTPWR_PWR            0x00FF /* Estimated power */
0426 #define  B43_NPHY_ESTPWR_PWR_SHIFT      0
0427 #define  B43_NPHY_ESTPWR_VALID          0x0100 /* Estimated power valid */
0428 #define B43_NPHY_TSSI_MAXTXFDT          B43_PHY_N(0x11C) /* TSSI max TX frame delay time */
0429 #define  B43_NPHY_TSSI_MAXTXFDT_VAL     0x00FF /* max TX frame delay time */
0430 #define  B43_NPHY_TSSI_MAXTXFDT_VAL_SHIFT   0
0431 #define B43_NPHY_TSSI_MAXTDT            B43_PHY_N(0x11D) /* TSSI max TSSI delay time */
0432 #define  B43_NPHY_TSSI_MAXTDT_VAL       0x00FF /* max TSSI delay time */
0433 #define  B43_NPHY_TSSI_MAXTDT_VAL_SHIFT     0
0434 #define B43_NPHY_ITSSI1             B43_PHY_N(0x11E) /* TSSI idle 1 */
0435 #define B43_NPHY_ITSSI2             B43_PHY_N(0x11F) /* TSSI idle 2 */
0436 #define  B43_NPHY_ITSSI_VAL         0x00FF /* Idle TSSI */
0437 #define  B43_NPHY_ITSSI_VAL_SHIFT       0
0438 #define B43_NPHY_TSSIMODE           B43_PHY_N(0x122) /* TSSI mode */
0439 #define  B43_NPHY_TSSIMODE_EN           0x0001 /* TSSI enable */
0440 #define  B43_NPHY_TSSIMODE_PDEN         0x0002 /* Power det enable */
0441 #define B43_NPHY_RXMACIFM           B43_PHY_N(0x123) /* RX Macif mode */
0442 #define B43_NPHY_CRSIT_COCNT_LO         B43_PHY_N(0x124) /* CRS idle time CRS-on count (low) */
0443 #define B43_NPHY_CRSIT_COCNT_HI         B43_PHY_N(0x125) /* CRS idle time CRS-on count (high) */
0444 #define B43_NPHY_CRSIT_MTCNT_LO         B43_PHY_N(0x126) /* CRS idle time measure time count (low) */
0445 #define B43_NPHY_CRSIT_MTCNT_HI         B43_PHY_N(0x127) /* CRS idle time measure time count (high) */
0446 #define B43_NPHY_SAMTWC             B43_PHY_N(0x128) /* Sample tail wait count */
0447 #define B43_NPHY_IQEST_CMD          B43_PHY_N(0x129) /* I/Q estimate command */
0448 #define  B43_NPHY_IQEST_CMD_START       0x0001 /* Start */
0449 #define  B43_NPHY_IQEST_CMD_MODE        0x0002 /* Mode */
0450 #define B43_NPHY_IQEST_WT           B43_PHY_N(0x12A) /* I/Q estimate wait time */
0451 #define  B43_NPHY_IQEST_WT_VAL          0x00FF /* Wait time */
0452 #define  B43_NPHY_IQEST_WT_VAL_SHIFT        0
0453 #define B43_NPHY_IQEST_SAMCNT           B43_PHY_N(0x12B) /* I/Q estimate sample count */
0454 #define B43_NPHY_IQEST_IQACC_LO0        B43_PHY_N(0x12C) /* I/Q estimate I/Q acc lo 0 */
0455 #define B43_NPHY_IQEST_IQACC_HI0        B43_PHY_N(0x12D) /* I/Q estimate I/Q acc hi 0 */
0456 #define B43_NPHY_IQEST_IPACC_LO0        B43_PHY_N(0x12E) /* I/Q estimate I power acc lo 0 */
0457 #define B43_NPHY_IQEST_IPACC_HI0        B43_PHY_N(0x12F) /* I/Q estimate I power acc hi 0 */
0458 #define B43_NPHY_IQEST_QPACC_LO0        B43_PHY_N(0x130) /* I/Q estimate Q power acc lo 0 */
0459 #define B43_NPHY_IQEST_QPACC_HI0        B43_PHY_N(0x131) /* I/Q estimate Q power acc hi 0 */
0460 #define B43_NPHY_IQEST_IQACC_LO1        B43_PHY_N(0x134) /* I/Q estimate I/Q acc lo 1 */
0461 #define B43_NPHY_IQEST_IQACC_HI1        B43_PHY_N(0x135) /* I/Q estimate I/Q acc hi 1 */
0462 #define B43_NPHY_IQEST_IPACC_LO1        B43_PHY_N(0x136) /* I/Q estimate I power acc lo 1 */
0463 #define B43_NPHY_IQEST_IPACC_HI1        B43_PHY_N(0x137) /* I/Q estimate I power acc hi 1 */
0464 #define B43_NPHY_IQEST_QPACC_LO1        B43_PHY_N(0x138) /* I/Q estimate Q power acc lo 1 */
0465 #define B43_NPHY_IQEST_QPACC_HI1        B43_PHY_N(0x139) /* I/Q estimate Q power acc hi 1 */
0466 #define B43_NPHY_MIMO_CRSTXEXT          B43_PHY_N(0x13A) /* MIMO PHY CRS TX extension */
0467 #define B43_NPHY_PWRDET1            B43_PHY_N(0x13B) /* Power det 1 */
0468 #define B43_NPHY_PWRDET2            B43_PHY_N(0x13C) /* Power det 2 */
0469 #define B43_NPHY_MAXRSSI_DTIME          B43_PHY_N(0x13F) /* RSSI max RSSI delay time */
0470 #define B43_NPHY_PIL_DW0            B43_PHY_N(0x141) /* Pilot data weight 0 */
0471 #define B43_NPHY_PIL_DW1            B43_PHY_N(0x142) /* Pilot data weight 1 */
0472 #define B43_NPHY_PIL_DW2            B43_PHY_N(0x143) /* Pilot data weight 2 */
0473 #define  B43_NPHY_PIL_DW_BPSK           0x000F /* BPSK */
0474 #define  B43_NPHY_PIL_DW_BPSK_SHIFT     0
0475 #define  B43_NPHY_PIL_DW_QPSK           0x00F0 /* QPSK */
0476 #define  B43_NPHY_PIL_DW_QPSK_SHIFT     4
0477 #define  B43_NPHY_PIL_DW_16QAM          0x0F00 /* 16-QAM */
0478 #define  B43_NPHY_PIL_DW_16QAM_SHIFT        8
0479 #define  B43_NPHY_PIL_DW_64QAM          0xF000 /* 64-QAM */
0480 #define  B43_NPHY_PIL_DW_64QAM_SHIFT        12
0481 #define B43_NPHY_FMDEM_CFG          B43_PHY_N(0x144) /* FM demodulation config */
0482 #define B43_NPHY_PHASETR_A0         B43_PHY_N(0x145) /* Phase track alpha 0 */
0483 #define B43_NPHY_PHASETR_A1         B43_PHY_N(0x146) /* Phase track alpha 1 */
0484 #define B43_NPHY_PHASETR_A2         B43_PHY_N(0x147) /* Phase track alpha 2 */
0485 #define B43_NPHY_PHASETR_B0         B43_PHY_N(0x148) /* Phase track beta 0 */
0486 #define B43_NPHY_PHASETR_B1         B43_PHY_N(0x149) /* Phase track beta 1 */
0487 #define B43_NPHY_PHASETR_B2         B43_PHY_N(0x14A) /* Phase track beta 2 */
0488 #define B43_NPHY_PHASETR_CHG0           B43_PHY_N(0x14B) /* Phase track change 0 */
0489 #define B43_NPHY_PHASETR_CHG1           B43_PHY_N(0x14C) /* Phase track change 1 */
0490 #define B43_NPHY_PHASETW_OFF            B43_PHY_N(0x14D) /* Phase track offset */
0491 #define B43_NPHY_RFCTL_DBG          B43_PHY_N(0x14E) /* RF control debug */
0492 #define B43_NPHY_CCK_SHIFTB_REF         B43_PHY_N(0x150) /* CCK shiftbits reference var */
0493 #define B43_NPHY_OVER_DGAIN0            B43_PHY_N(0x152) /* Override digital gain 0 */
0494 #define B43_NPHY_OVER_DGAIN1            B43_PHY_N(0x153) /* Override digital gain 1 */
0495 #define  B43_NPHY_OVER_DGAIN_FDGV       0x0007 /* Force digital gain value */
0496 #define  B43_NPHY_OVER_DGAIN_FDGV_SHIFT     0
0497 #define  B43_NPHY_OVER_DGAIN_FDGEN      0x0008 /* Force digital gain enable */
0498 #define  B43_NPHY_OVER_DGAIN_CCKDGECV       0xFF00 /* CCK digital gain enable count value */
0499 #define  B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT 8
0500 #define B43_NPHY_BIST_STAT4         B43_PHY_N(0x156) /* BIST status 4 */
0501 #define B43_NPHY_RADAR_MAL          B43_PHY_N(0x157) /* Radar MA length */
0502 #define B43_NPHY_RADAR_SRCCTL           B43_PHY_N(0x158) /* Radar search control */
0503 #define B43_NPHY_VLD_DTSIG          B43_PHY_N(0x159) /* VLD data tones sig */
0504 #define B43_NPHY_VLD_DTDAT          B43_PHY_N(0x15A) /* VLD data tones data */
0505 #define B43_NPHY_C1_BPHY_RXIQCA0        B43_PHY_N(0x15B) /* Core 1 B PHY RX I/Q comp A0 */
0506 #define B43_NPHY_C1_BPHY_RXIQCB0        B43_PHY_N(0x15C) /* Core 1 B PHY RX I/Q comp B0 */
0507 #define B43_NPHY_C2_BPHY_RXIQCA1        B43_PHY_N(0x15D) /* Core 2 B PHY RX I/Q comp A1 */
0508 #define B43_NPHY_C2_BPHY_RXIQCB1        B43_PHY_N(0x15E) /* Core 2 B PHY RX I/Q comp B1 */
0509 #define B43_NPHY_FREQGAIN0          B43_PHY_N(0x160) /* Frequency gain 0 */
0510 #define B43_NPHY_FREQGAIN1          B43_PHY_N(0x161) /* Frequency gain 1 */
0511 #define B43_NPHY_FREQGAIN2          B43_PHY_N(0x162) /* Frequency gain 2 */
0512 #define B43_NPHY_FREQGAIN3          B43_PHY_N(0x163) /* Frequency gain 3 */
0513 #define B43_NPHY_FREQGAIN4          B43_PHY_N(0x164) /* Frequency gain 4 */
0514 #define B43_NPHY_FREQGAIN5          B43_PHY_N(0x165) /* Frequency gain 5 */
0515 #define B43_NPHY_FREQGAIN6          B43_PHY_N(0x166) /* Frequency gain 6 */
0516 #define B43_NPHY_FREQGAIN7          B43_PHY_N(0x167) /* Frequency gain 7 */
0517 #define B43_NPHY_FREQGAIN_BYPASS        B43_PHY_N(0x168) /* Frequency gain bypass */
0518 #define B43_NPHY_TRLOSS             B43_PHY_N(0x169) /* TR loss value */
0519 #define B43_NPHY_C1_ADCCLIP         B43_PHY_N(0x16A) /* Core 1 ADC clip */
0520 #define B43_NPHY_C2_ADCCLIP         B43_PHY_N(0x16B) /* Core 2 ADC clip */
0521 #define B43_NPHY_LTRN_OFFGAIN           B43_PHY_N(0x16F) /* LTRN offset gain */
0522 #define B43_NPHY_LTRN_OFF           B43_PHY_N(0x170) /* LTRN offset */
0523 #define B43_NPHY_NRDATAT_WWISE20SIG     B43_PHY_N(0x171) /* # data tones WWiSE 20 sig */
0524 #define B43_NPHY_NRDATAT_WWISE40SIG     B43_PHY_N(0x172) /* # data tones WWiSE 40 sig */
0525 #define B43_NPHY_NRDATAT_TGNSYNC20SIG       B43_PHY_N(0x173) /* # data tones TGNsync 20 sig */
0526 #define B43_NPHY_NRDATAT_TGNSYNC40SIG       B43_PHY_N(0x174) /* # data tones TGNsync 40 sig */
0527 #define B43_NPHY_WWISE_CRCM0            B43_PHY_N(0x175) /* WWiSE CRC mask 0 */
0528 #define B43_NPHY_WWISE_CRCM1            B43_PHY_N(0x176) /* WWiSE CRC mask 1 */
0529 #define B43_NPHY_WWISE_CRCM2            B43_PHY_N(0x177) /* WWiSE CRC mask 2 */
0530 #define B43_NPHY_WWISE_CRCM3            B43_PHY_N(0x178) /* WWiSE CRC mask 3 */
0531 #define B43_NPHY_WWISE_CRCM4            B43_PHY_N(0x179) /* WWiSE CRC mask 4 */
0532 #define B43_NPHY_CHANEST_CDDSH          B43_PHY_N(0x17A) /* Channel estimate CDD shift */
0533 #define B43_NPHY_HTAGC_WCNT         B43_PHY_N(0x17B) /* HT ADC wait counters */
0534 #define B43_NPHY_SQPARM             B43_PHY_N(0x17C) /* SQ params */
0535 #define B43_NPHY_MCSDUP6M           B43_PHY_N(0x17D) /* MCS dup 6M */
0536 #define B43_NPHY_NDATAT_DUP40           B43_PHY_N(0x17E) /* # data tones dup 40 */
0537 #define B43_NPHY_DUP40_TGNSYNC_CYCD     B43_PHY_N(0x17F) /* Dup40 TGNsync cycle data */
0538 #define B43_NPHY_DUP40_GFBL         B43_PHY_N(0x180) /* Dup40 GF format BL address */
0539 #define B43_NPHY_DUP40_BL           B43_PHY_N(0x181) /* Dup40 format BL address */
0540 #define B43_NPHY_LEGDUP_FTA         B43_PHY_N(0x182) /* Legacy dup frm table address */
0541 #define B43_NPHY_PACPROC_DBG            B43_PHY_N(0x183) /* Packet processing debug */
0542 #define B43_NPHY_PIL_CYC1           B43_PHY_N(0x184) /* Pilot cycle counter 1 */
0543 #define B43_NPHY_PIL_CYC2           B43_PHY_N(0x185) /* Pilot cycle counter 2 */
0544 #define B43_NPHY_TXF_20CO_S0A1          B43_PHY_N(0x186) /* TX filter 20 coeff stage 0 A1 */
0545 #define B43_NPHY_TXF_20CO_S0A2          B43_PHY_N(0x187) /* TX filter 20 coeff stage 0 A2 */
0546 #define B43_NPHY_TXF_20CO_S1A1          B43_PHY_N(0x188) /* TX filter 20 coeff stage 1 A1 */
0547 #define B43_NPHY_TXF_20CO_S1A2          B43_PHY_N(0x189) /* TX filter 20 coeff stage 1 A2 */
0548 #define B43_NPHY_TXF_20CO_S2A1          B43_PHY_N(0x18A) /* TX filter 20 coeff stage 2 A1 */
0549 #define B43_NPHY_TXF_20CO_S2A2          B43_PHY_N(0x18B) /* TX filter 20 coeff stage 2 A2 */
0550 #define B43_NPHY_TXF_20CO_S0B1          B43_PHY_N(0x18C) /* TX filter 20 coeff stage 0 B1 */
0551 #define B43_NPHY_TXF_20CO_S0B2          B43_PHY_N(0x18D) /* TX filter 20 coeff stage 0 B2 */
0552 #define B43_NPHY_TXF_20CO_S0B3          B43_PHY_N(0x18E) /* TX filter 20 coeff stage 0 B3 */
0553 #define B43_NPHY_TXF_20CO_S1B1          B43_PHY_N(0x18F) /* TX filter 20 coeff stage 1 B1 */
0554 #define B43_NPHY_TXF_20CO_S1B2          B43_PHY_N(0x190) /* TX filter 20 coeff stage 1 B2 */
0555 #define B43_NPHY_TXF_20CO_S1B3          B43_PHY_N(0x191) /* TX filter 20 coeff stage 1 B3 */
0556 #define B43_NPHY_TXF_20CO_S2B1          B43_PHY_N(0x192) /* TX filter 20 coeff stage 2 B1 */
0557 #define B43_NPHY_TXF_20CO_S2B2          B43_PHY_N(0x193) /* TX filter 20 coeff stage 2 B2 */
0558 #define B43_NPHY_TXF_20CO_S2B3          B43_PHY_N(0x194) /* TX filter 20 coeff stage 2 B3 */
0559 #define B43_NPHY_TXF_40CO_S0A1          B43_PHY_N(0x195) /* TX filter 40 coeff stage 0 A1 */
0560 #define B43_NPHY_TXF_40CO_S0A2          B43_PHY_N(0x196) /* TX filter 40 coeff stage 0 A2 */
0561 #define B43_NPHY_TXF_40CO_S1A1          B43_PHY_N(0x197) /* TX filter 40 coeff stage 1 A1 */
0562 #define B43_NPHY_TXF_40CO_S1A2          B43_PHY_N(0x198) /* TX filter 40 coeff stage 1 A2 */
0563 #define B43_NPHY_TXF_40CO_S2A1          B43_PHY_N(0x199) /* TX filter 40 coeff stage 2 A1 */
0564 #define B43_NPHY_TXF_40CO_S2A2          B43_PHY_N(0x19A) /* TX filter 40 coeff stage 2 A2 */
0565 #define B43_NPHY_TXF_40CO_S0B1          B43_PHY_N(0x19B) /* TX filter 40 coeff stage 0 B1 */
0566 #define B43_NPHY_TXF_40CO_S0B2          B43_PHY_N(0x19C) /* TX filter 40 coeff stage 0 B2 */
0567 #define B43_NPHY_TXF_40CO_S0B3          B43_PHY_N(0x19D) /* TX filter 40 coeff stage 0 B3 */
0568 #define B43_NPHY_TXF_40CO_S1B1          B43_PHY_N(0x19E) /* TX filter 40 coeff stage 1 B1 */
0569 #define B43_NPHY_TXF_40CO_S1B2          B43_PHY_N(0x19F) /* TX filter 40 coeff stage 1 B2 */
0570 #define B43_NPHY_TXF_40CO_S1B3          B43_PHY_N(0x1A0) /* TX filter 40 coeff stage 1 B3 */
0571 #define B43_NPHY_TXF_40CO_S2B1          B43_PHY_N(0x1A1) /* TX filter 40 coeff stage 2 B1 */
0572 #define B43_NPHY_TXF_40CO_S2B2          B43_PHY_N(0x1A2) /* TX filter 40 coeff stage 2 B2 */
0573 #define B43_NPHY_TXF_40CO_S2B3          B43_PHY_N(0x1A3) /* TX filter 40 coeff stage 2 B3 */
0574 #define B43_NPHY_RSSIMC_0I_RSSI_X       B43_PHY_N(0x1A4) /* RSSI multiplication coefficient 0 I RSSI X */
0575 #define B43_NPHY_RSSIMC_0I_RSSI_Y       B43_PHY_N(0x1A5) /* RSSI multiplication coefficient 0 I RSSI Y */
0576 #define B43_NPHY_RSSIMC_0I_RSSI_Z       B43_PHY_N(0x1A6) /* RSSI multiplication coefficient 0 I RSSI Z */
0577 #define B43_NPHY_RSSIMC_0I_TBD          B43_PHY_N(0x1A7) /* RSSI multiplication coefficient 0 I TBD */
0578 #define B43_NPHY_RSSIMC_0I_PWRDET       B43_PHY_N(0x1A8) /* RSSI multiplication coefficient 0 I power det */
0579 #define B43_NPHY_RSSIMC_0I_TSSI         B43_PHY_N(0x1A9) /* RSSI multiplication coefficient 0 I TSSI */
0580 #define B43_NPHY_RSSIMC_0Q_RSSI_X       B43_PHY_N(0x1AA) /* RSSI multiplication coefficient 0 Q RSSI X */
0581 #define B43_NPHY_RSSIMC_0Q_RSSI_Y       B43_PHY_N(0x1AB) /* RSSI multiplication coefficient 0 Q RSSI Y */
0582 #define B43_NPHY_RSSIMC_0Q_RSSI_Z       B43_PHY_N(0x1AC) /* RSSI multiplication coefficient 0 Q RSSI Z */
0583 #define B43_NPHY_RSSIMC_0Q_TBD          B43_PHY_N(0x1AD) /* RSSI multiplication coefficient 0 Q TBD */
0584 #define B43_NPHY_RSSIMC_0Q_PWRDET       B43_PHY_N(0x1AE) /* RSSI multiplication coefficient 0 Q power det */
0585 #define B43_NPHY_RSSIMC_0Q_TSSI         B43_PHY_N(0x1AF) /* RSSI multiplication coefficient 0 Q TSSI */
0586 #define B43_NPHY_RSSIMC_1I_RSSI_X       B43_PHY_N(0x1B0) /* RSSI multiplication coefficient 1 I RSSI X */
0587 #define B43_NPHY_RSSIMC_1I_RSSI_Y       B43_PHY_N(0x1B1) /* RSSI multiplication coefficient 1 I RSSI Y */
0588 #define B43_NPHY_RSSIMC_1I_RSSI_Z       B43_PHY_N(0x1B2) /* RSSI multiplication coefficient 1 I RSSI Z */
0589 #define B43_NPHY_RSSIMC_1I_TBD          B43_PHY_N(0x1B3) /* RSSI multiplication coefficient 1 I TBD */
0590 #define B43_NPHY_RSSIMC_1I_PWRDET       B43_PHY_N(0x1B4) /* RSSI multiplication coefficient 1 I power det */
0591 #define B43_NPHY_RSSIMC_1I_TSSI         B43_PHY_N(0x1B5) /* RSSI multiplication coefficient 1 I TSSI */
0592 #define B43_NPHY_RSSIMC_1Q_RSSI_X       B43_PHY_N(0x1B6) /* RSSI multiplication coefficient 1 Q RSSI X */
0593 #define B43_NPHY_RSSIMC_1Q_RSSI_Y       B43_PHY_N(0x1B7) /* RSSI multiplication coefficient 1 Q RSSI Y */
0594 #define B43_NPHY_RSSIMC_1Q_RSSI_Z       B43_PHY_N(0x1B8) /* RSSI multiplication coefficient 1 Q RSSI Z */
0595 #define B43_NPHY_RSSIMC_1Q_TBD          B43_PHY_N(0x1B9) /* RSSI multiplication coefficient 1 Q TBD */
0596 #define B43_NPHY_RSSIMC_1Q_PWRDET       B43_PHY_N(0x1BA) /* RSSI multiplication coefficient 1 Q power det */
0597 #define B43_NPHY_RSSIMC_1Q_TSSI         B43_PHY_N(0x1BB) /* RSSI multiplication coefficient 1 Q TSSI */
0598 #define B43_NPHY_SAMC_WCNT          B43_PHY_N(0x1BC) /* Sample collect wait counter */
0599 #define B43_NPHY_PTHROUGH_CNT           B43_PHY_N(0x1BD) /* Pass-through counter */
0600 #define B43_NPHY_LTRN_OFF_G20L          B43_PHY_N(0x1C4) /* LTRN offset gain 20L */
0601 #define B43_NPHY_LTRN_OFF_20L           B43_PHY_N(0x1C5) /* LTRN offset 20L */
0602 #define B43_NPHY_LTRN_OFF_G20U          B43_PHY_N(0x1C6) /* LTRN offset gain 20U */
0603 #define B43_NPHY_LTRN_OFF_20U           B43_PHY_N(0x1C7) /* LTRN offset 20U */
0604 #define B43_NPHY_DSSSCCK_GAINSL         B43_PHY_N(0x1C8) /* DSSS/CCK gain settle length */
0605 #define B43_NPHY_GPIO_LOOUT         B43_PHY_N(0x1C9) /* GPIO low out */
0606 #define B43_NPHY_GPIO_HIOUT         B43_PHY_N(0x1CA) /* GPIO high out */
0607 #define B43_NPHY_CRS_CHECK          B43_PHY_N(0x1CB) /* CRS check */
0608 #define B43_NPHY_ML_LOGSS_RAT           B43_PHY_N(0x1CC) /* ML/logss ratio */
0609 #define B43_NPHY_DUPSCALE           B43_PHY_N(0x1CD) /* Dup scale */
0610 #define B43_NPHY_BW1A               B43_PHY_N(0x1CE) /* BW 1A */
0611 #define B43_NPHY_BW2                B43_PHY_N(0x1CF) /* BW 2 */
0612 #define B43_NPHY_BW3                B43_PHY_N(0x1D0) /* BW 3 */
0613 #define B43_NPHY_BW4                B43_PHY_N(0x1D1) /* BW 4 */
0614 #define B43_NPHY_BW5                B43_PHY_N(0x1D2) /* BW 5 */
0615 #define B43_NPHY_BW6                B43_PHY_N(0x1D3) /* BW 6 */
0616 #define B43_NPHY_COALEN0            B43_PHY_N(0x1D4) /* Coarse length 0 */
0617 #define B43_NPHY_COALEN1            B43_PHY_N(0x1D5) /* Coarse length 1 */
0618 #define B43_NPHY_CRSTHRES_1U            B43_PHY_N(0x1D6) /* CRS threshold 1 U */
0619 #define B43_NPHY_CRSTHRES_2U            B43_PHY_N(0x1D7) /* CRS threshold 2 U */
0620 #define B43_NPHY_CRSTHRES_3U            B43_PHY_N(0x1D8) /* CRS threshold 3 U */
0621 #define B43_NPHY_CRSCTL_U           B43_PHY_N(0x1D9) /* CRS control U */
0622 #define B43_NPHY_CRSTHRES_1L            B43_PHY_N(0x1DA) /* CRS threshold 1 L */
0623 #define B43_NPHY_CRSTHRES_2L            B43_PHY_N(0x1DB) /* CRS threshold 2 L */
0624 #define B43_NPHY_CRSTHRES_3L            B43_PHY_N(0x1DC) /* CRS threshold 3 L */
0625 #define B43_NPHY_CRSCTL_L           B43_PHY_N(0x1DD) /* CRS control L */
0626 #define B43_NPHY_STRA_1U            B43_PHY_N(0x1DE) /* STR address 1 U */
0627 #define B43_NPHY_STRA_2U            B43_PHY_N(0x1DF) /* STR address 2 U */
0628 #define B43_NPHY_STRA_1L            B43_PHY_N(0x1E0) /* STR address 1 L */
0629 #define B43_NPHY_STRA_2L            B43_PHY_N(0x1E1) /* STR address 2 L */
0630 #define B43_NPHY_CRSCHECK1          B43_PHY_N(0x1E2) /* CRS check 1 */
0631 #define B43_NPHY_CRSCHECK2          B43_PHY_N(0x1E3) /* CRS check 2 */
0632 #define B43_NPHY_CRSCHECK3          B43_PHY_N(0x1E4) /* CRS check 3 */
0633 #define B43_NPHY_JMPSTP0            B43_PHY_N(0x1E5) /* Jump step 0 */
0634 #define B43_NPHY_JMPSTP1            B43_PHY_N(0x1E6) /* Jump step 1 */
0635 #define B43_NPHY_TXPCTL_CMD         B43_PHY_N(0x1E7) /* TX power control command */
0636 #define  B43_NPHY_TXPCTL_CMD_INIT       0x007F /* Init */
0637 #define  B43_NPHY_TXPCTL_CMD_INIT_SHIFT     0
0638 #define  B43_NPHY_TXPCTL_CMD_COEFF      0x2000 /* Power control coefficients */
0639 #define  B43_NPHY_TXPCTL_CMD_HWPCTLEN       0x4000 /* Hardware TX power control enable */
0640 #define  B43_NPHY_TXPCTL_CMD_PCTLEN     0x8000 /* TX power control enable */
0641 #define B43_NPHY_TXPCTL_N           B43_PHY_N(0x1E8) /* TX power control N num */
0642 #define  B43_NPHY_TXPCTL_N_TSSID        0x00FF /* N TSSI delay */
0643 #define  B43_NPHY_TXPCTL_N_TSSID_SHIFT      0
0644 #define  B43_NPHY_TXPCTL_N_NPTIL2       0x0700 /* N PT integer log2 */
0645 #define  B43_NPHY_TXPCTL_N_NPTIL2_SHIFT     8
0646 #define B43_NPHY_TXPCTL_ITSSI           B43_PHY_N(0x1E9) /* TX power control idle TSSI */
0647 #define  B43_NPHY_TXPCTL_ITSSI_0        0x003F /* Idle TSSI 0 */
0648 #define  B43_NPHY_TXPCTL_ITSSI_0_SHIFT      0
0649 #define  B43_NPHY_TXPCTL_ITSSI_1        0x3F00 /* Idle TSSI 1 */
0650 #define  B43_NPHY_TXPCTL_ITSSI_1_SHIFT      8
0651 #define  B43_NPHY_TXPCTL_ITSSI_BINF     0x8000 /* Raw TSSI offset bin format */
0652 #define B43_NPHY_TXPCTL_TPWR            B43_PHY_N(0x1EA) /* TX power control target power */
0653 #define  B43_NPHY_TXPCTL_TPWR_0         0x00FF /* Power 0 */
0654 #define  B43_NPHY_TXPCTL_TPWR_0_SHIFT       0
0655 #define  B43_NPHY_TXPCTL_TPWR_1         0xFF00 /* Power 1 */
0656 #define  B43_NPHY_TXPCTL_TPWR_1_SHIFT       8
0657 #define B43_NPHY_TXPCTL_BIDX            B43_PHY_N(0x1EB) /* TX power control base index */
0658 #define  B43_NPHY_TXPCTL_BIDX_0         0x007F /* uC base index 0 */
0659 #define  B43_NPHY_TXPCTL_BIDX_0_SHIFT       0
0660 #define  B43_NPHY_TXPCTL_BIDX_1         0x7F00 /* uC base index 1 */
0661 #define  B43_NPHY_TXPCTL_BIDX_1_SHIFT       8
0662 #define  B43_NPHY_TXPCTL_BIDX_LOAD      0x8000 /* Load base index */
0663 #define B43_NPHY_TXPCTL_PIDX            B43_PHY_N(0x1EC) /* TX power control power index */
0664 #define  B43_NPHY_TXPCTL_PIDX_0         0x007F /* uC power index 0 */
0665 #define  B43_NPHY_TXPCTL_PIDX_0_SHIFT       0
0666 #define  B43_NPHY_TXPCTL_PIDX_1         0x7F00 /* uC power index 1 */
0667 #define  B43_NPHY_TXPCTL_PIDX_1_SHIFT       8
0668 #define B43_NPHY_C1_TXPCTL_STAT         B43_PHY_N(0x1ED) /* Core 1 TX power control status */
0669 #define B43_NPHY_C2_TXPCTL_STAT         B43_PHY_N(0x1EE) /* Core 2 TX power control status */
0670 #define  B43_NPHY_TXPCTL_STAT_EST       0x00FF /* Estimated power */
0671 #define  B43_NPHY_TXPCTL_STAT_EST_SHIFT     0
0672 #define  B43_NPHY_TXPCTL_STAT_BIDX      0x7F00 /* Base index */
0673 #define  B43_NPHY_TXPCTL_STAT_BIDX_SHIFT    8
0674 #define  B43_NPHY_TXPCTL_STAT_ESTVALID      0x8000 /* Estimated power valid */
0675 #define B43_NPHY_SMALLSGS_LEN           B43_PHY_N(0x1EF) /* Small sig gain settle length */
0676 #define B43_NPHY_PHYSTAT_GAIN0          B43_PHY_N(0x1F0) /* PHY stats gain info 0 */
0677 #define B43_NPHY_PHYSTAT_GAIN1          B43_PHY_N(0x1F1) /* PHY stats gain info 1 */
0678 #define B43_NPHY_PHYSTAT_FREQEST        B43_PHY_N(0x1F2) /* PHY stats frequency estimate */
0679 #define B43_NPHY_PHYSTAT_ADVRET         B43_PHY_N(0x1F3) /* PHY stats ADV retard */
0680 #define B43_NPHY_PHYLB_MODE         B43_PHY_N(0x1F4) /* PHY loopback mode */
0681 #define B43_NPHY_TONE_MIDX20_1          B43_PHY_N(0x1F5) /* Tone map index 20/1 */
0682 #define B43_NPHY_TONE_MIDX20_2          B43_PHY_N(0x1F6) /* Tone map index 20/2 */
0683 #define B43_NPHY_TONE_MIDX20_3          B43_PHY_N(0x1F7) /* Tone map index 20/3 */
0684 #define B43_NPHY_TONE_MIDX40_1          B43_PHY_N(0x1F8) /* Tone map index 40/1 */
0685 #define B43_NPHY_TONE_MIDX40_2          B43_PHY_N(0x1F9) /* Tone map index 40/2 */
0686 #define B43_NPHY_TONE_MIDX40_3          B43_PHY_N(0x1FA) /* Tone map index 40/3 */
0687 #define B43_NPHY_TONE_MIDX40_4          B43_PHY_N(0x1FB) /* Tone map index 40/4 */
0688 #define B43_NPHY_PILTONE_MIDX1          B43_PHY_N(0x1FC) /* Pilot tone map index 1 */
0689 #define B43_NPHY_PILTONE_MIDX2          B43_PHY_N(0x1FD) /* Pilot tone map index 2 */
0690 #define B43_NPHY_PILTONE_MIDX3          B43_PHY_N(0x1FE) /* Pilot tone map index 3 */
0691 #define B43_NPHY_TXRIFS_FRDEL           B43_PHY_N(0x1FF) /* TX RIFS frame delay */
0692 #define B43_NPHY_AFESEQ_RX2TX_PUD_40M       B43_PHY_N(0x200) /* AFE seq rx2tx power up/down delay 40M */
0693 #define B43_NPHY_AFESEQ_TX2RX_PUD_40M       B43_PHY_N(0x201) /* AFE seq tx2rx power up/down delay 40M */
0694 #define B43_NPHY_AFESEQ_RX2TX_PUD_20M       B43_PHY_N(0x202) /* AFE seq rx2tx power up/down delay 20M */
0695 #define B43_NPHY_AFESEQ_TX2RX_PUD_20M       B43_PHY_N(0x203) /* AFE seq tx2rx power up/down delay 20M */
0696 #define B43_NPHY_RX_SIGCTL          B43_PHY_N(0x204) /* RX signal control */
0697 #define B43_NPHY_RXPIL_CYCNT0           B43_PHY_N(0x205) /* RX pilot cycle counter 0 */
0698 #define B43_NPHY_RXPIL_CYCNT1           B43_PHY_N(0x206) /* RX pilot cycle counter 1 */
0699 #define B43_NPHY_RXPIL_CYCNT2           B43_PHY_N(0x207) /* RX pilot cycle counter 2 */
0700 #define B43_NPHY_AFESEQ_RX2TX_PUD_10M       B43_PHY_N(0x208) /* AFE seq rx2tx power up/down delay 10M */
0701 #define B43_NPHY_AFESEQ_TX2RX_PUD_10M       B43_PHY_N(0x209) /* AFE seq tx2rx power up/down delay 10M */
0702 #define B43_NPHY_DSSSCCK_CRSEXTL        B43_PHY_N(0x20A) /* DSSS/CCK CRS extension length */
0703 #define B43_NPHY_ML_LOGSS_RATSLOPE      B43_PHY_N(0x20B) /* ML/logss ratio slope */
0704 #define B43_NPHY_RIFS_SRCTL         B43_PHY_N(0x20C) /* RIFS search timeout length */
0705 #define B43_NPHY_TXREALFD           B43_PHY_N(0x20D) /* TX real frame delay */
0706 #define B43_NPHY_HPANT_SWTHRES          B43_PHY_N(0x20E) /* High power antenna switch threshold */
0707 #define B43_NPHY_EDCRS_ASSTHRES0        B43_PHY_N(0x210) /* ED CRS assert threshold 0 */
0708 #define B43_NPHY_EDCRS_ASSTHRES1        B43_PHY_N(0x211) /* ED CRS assert threshold 1 */
0709 #define B43_NPHY_EDCRS_DEASSTHRES0      B43_PHY_N(0x212) /* ED CRS deassert threshold 0 */
0710 #define B43_NPHY_EDCRS_DEASSTHRES1      B43_PHY_N(0x213) /* ED CRS deassert threshold 1 */
0711 #define B43_NPHY_STR_WTIME20U           B43_PHY_N(0x214) /* STR wait time 20U */
0712 #define B43_NPHY_STR_WTIME20L           B43_PHY_N(0x215) /* STR wait time 20L */
0713 #define B43_NPHY_TONE_MIDX657M          B43_PHY_N(0x216) /* Tone map index 657M */
0714 #define B43_NPHY_HTSIGTONES         B43_PHY_N(0x217) /* HT signal tones */
0715 #define B43_NPHY_RSSI1              B43_PHY_N(0x219) /* RSSI value 1 */
0716 #define B43_NPHY_RSSI2              B43_PHY_N(0x21A) /* RSSI value 2 */
0717 #define B43_NPHY_CHAN_ESTHANG           B43_PHY_N(0x21D) /* Channel estimate hang */
0718 #define B43_NPHY_FINERX2_CGC            B43_PHY_N(0x221) /* Fine RX 2 clock gate control */
0719 #define  B43_NPHY_FINERX2_CGC_DECGC     0x0008 /* Decode gated clocks */
0720 #define B43_NPHY_TXPCTL_INIT            B43_PHY_N(0x222) /* TX power control init */
0721 #define  B43_NPHY_TXPCTL_INIT_PIDXI1        0x00FF /* Power index init 1 */
0722 #define  B43_NPHY_TXPCTL_INIT_PIDXI1_SHIFT  0
0723 #define B43_NPHY_ED_CRSEN           B43_PHY_N(0x223)
0724 #define B43_NPHY_ED_CRS40ASSERTTHRESH0      B43_PHY_N(0x224)
0725 #define B43_NPHY_ED_CRS40ASSERTTHRESH1      B43_PHY_N(0x225)
0726 #define B43_NPHY_ED_CRS40DEASSERTTHRESH0    B43_PHY_N(0x226)
0727 #define B43_NPHY_ED_CRS40DEASSERTTHRESH1    B43_PHY_N(0x227)
0728 #define B43_NPHY_ED_CRS20LASSERTTHRESH0     B43_PHY_N(0x228)
0729 #define B43_NPHY_ED_CRS20LASSERTTHRESH1     B43_PHY_N(0x229)
0730 #define B43_NPHY_ED_CRS20LDEASSERTTHRESH0   B43_PHY_N(0x22A)
0731 #define B43_NPHY_ED_CRS20LDEASSERTTHRESH1   B43_PHY_N(0x22B)
0732 #define B43_NPHY_ED_CRS20UASSERTTHRESH0     B43_PHY_N(0x22C)
0733 #define B43_NPHY_ED_CRS20UASSERTTHRESH1     B43_PHY_N(0x22D)
0734 #define B43_NPHY_ED_CRS20UDEASSERTTHRESH0   B43_PHY_N(0x22E)
0735 #define B43_NPHY_ED_CRS20UDEASSERTTHRESH1   B43_PHY_N(0x22F)
0736 #define B43_NPHY_ED_CRS             B43_PHY_N(0x230)
0737 #define B43_NPHY_TIMEOUTEN          B43_PHY_N(0x231)
0738 #define B43_NPHY_OFDMPAYDECODETIMEOUTLEN    B43_PHY_N(0x232)
0739 #define B43_NPHY_CCKPAYDECODETIMEOUTLEN     B43_PHY_N(0x233)
0740 #define B43_NPHY_NONPAYDECODETIMEOUTLEN     B43_PHY_N(0x234)
0741 #define B43_NPHY_TIMEOUTSTATUS          B43_PHY_N(0x235)
0742 #define B43_NPHY_RFCTRLCORE0GPIO0       B43_PHY_N(0x236)
0743 #define B43_NPHY_RFCTRLCORE0GPIO1       B43_PHY_N(0x237)
0744 #define B43_NPHY_RFCTRLCORE0GPIO2       B43_PHY_N(0x238)
0745 #define B43_NPHY_RFCTRLCORE0GPIO3       B43_PHY_N(0x239)
0746 #define B43_NPHY_RFCTRLCORE1GPIO0       B43_PHY_N(0x23A)
0747 #define B43_NPHY_RFCTRLCORE1GPIO1       B43_PHY_N(0x23B)
0748 #define B43_NPHY_RFCTRLCORE1GPIO2       B43_PHY_N(0x23C)
0749 #define B43_NPHY_RFCTRLCORE1GPIO3       B43_PHY_N(0x23D)
0750 #define B43_NPHY_BPHYTESTCONTROL        B43_PHY_N(0x23E)
0751 /* REV3+ */
0752 #define B43_NPHY_FORCEFRONT0            B43_PHY_N(0x23F)
0753 #define B43_NPHY_FORCEFRONT1            B43_PHY_N(0x240)
0754 #define B43_NPHY_NORMVARHYSTTH          B43_PHY_N(0x241)
0755 #define B43_NPHY_TXCCKERROR         B43_PHY_N(0x242)
0756 #define B43_NPHY_AFESEQINITDACGAIN      B43_PHY_N(0x243)
0757 #define B43_NPHY_TXANTSWLUT         B43_PHY_N(0x244)
0758 #define B43_NPHY_CORECONFIG         B43_PHY_N(0x245)
0759 #define B43_NPHY_ANTENNADIVDWELLTIME        B43_PHY_N(0x246)
0760 #define B43_NPHY_ANTENNACCKDIVDWELLTIME     B43_PHY_N(0x247)
0761 #define B43_NPHY_ANTENNADIVBACKOFFGAIN      B43_PHY_N(0x248)
0762 #define B43_NPHY_ANTENNADIVMINGAIN      B43_PHY_N(0x249)
0763 #define B43_NPHY_BRDSEL_NORMVARHYSTTH       B43_PHY_N(0x24A)
0764 #define B43_NPHY_RXANTSWITCHCTRL        B43_PHY_N(0x24B)
0765 #define B43_NPHY_ENERGYDROPTIMEOUTLEN2      B43_PHY_N(0x24C)
0766 #define B43_NPHY_ML_LOG_TXEVM0          B43_PHY_N(0x250)
0767 #define B43_NPHY_ML_LOG_TXEVM1          B43_PHY_N(0x251)
0768 #define B43_NPHY_ML_LOG_TXEVM2          B43_PHY_N(0x252)
0769 #define B43_NPHY_ML_LOG_TXEVM3          B43_PHY_N(0x253)
0770 #define B43_NPHY_ML_LOG_TXEVM4          B43_PHY_N(0x254)
0771 #define B43_NPHY_ML_LOG_TXEVM5          B43_PHY_N(0x255)
0772 #define B43_NPHY_ML_LOG_TXEVM6          B43_PHY_N(0x256)
0773 #define B43_NPHY_ML_LOG_TXEVM7          B43_PHY_N(0x257)
0774 #define B43_NPHY_ML_SCALE_TWEAK         B43_PHY_N(0x258)
0775 #define B43_NPHY_MLUA               B43_PHY_N(0x259)
0776 #define B43_NPHY_ZFUA               B43_PHY_N(0x25A)
0777 #define B43_NPHY_CHANUPSYM01            B43_PHY_N(0x25B)
0778 #define B43_NPHY_CHANUPSYM2         B43_PHY_N(0x25C)
0779 #define B43_NPHY_RXSTRNFILT20NUM00      B43_PHY_N(0x25D)
0780 #define B43_NPHY_RXSTRNFILT20NUM01      B43_PHY_N(0x25E)
0781 #define B43_NPHY_RXSTRNFILT20NUM02      B43_PHY_N(0x25F)
0782 #define B43_NPHY_RXSTRNFILT20DEN00      B43_PHY_N(0x260)
0783 #define B43_NPHY_RXSTRNFILT20DEN01      B43_PHY_N(0x261)
0784 #define B43_NPHY_RXSTRNFILT20NUM10      B43_PHY_N(0x262)
0785 #define B43_NPHY_RXSTRNFILT20NUM11      B43_PHY_N(0x263)
0786 #define B43_NPHY_RXSTRNFILT20NUM12      B43_PHY_N(0x264)
0787 #define B43_NPHY_RXSTRNFILT20DEN10      B43_PHY_N(0x265)
0788 #define B43_NPHY_RXSTRNFILT20DEN11      B43_PHY_N(0x266)
0789 #define B43_NPHY_RXSTRNFILT40NUM00      B43_PHY_N(0x267)
0790 #define B43_NPHY_RXSTRNFILT40NUM01      B43_PHY_N(0x268)
0791 #define B43_NPHY_RXSTRNFILT40NUM02      B43_PHY_N(0x269)
0792 #define B43_NPHY_RXSTRNFILT40DEN00      B43_PHY_N(0x26A)
0793 #define B43_NPHY_RXSTRNFILT40DEN01      B43_PHY_N(0x26B)
0794 #define B43_NPHY_RXSTRNFILT40NUM10      B43_PHY_N(0x26C)
0795 #define B43_NPHY_RXSTRNFILT40NUM11      B43_PHY_N(0x26D)
0796 #define B43_NPHY_RXSTRNFILT40NUM12      B43_PHY_N(0x26E)
0797 #define B43_NPHY_RXSTRNFILT40DEN10      B43_PHY_N(0x26F)
0798 #define B43_NPHY_RXSTRNFILT40DEN11      B43_PHY_N(0x270)
0799 #define B43_NPHY_CRSHIGHPOWTHRESHOLD1       B43_PHY_N(0x271)
0800 #define B43_NPHY_CRSHIGHPOWTHRESHOLD2       B43_PHY_N(0x272)
0801 #define B43_NPHY_CRSHIGHLOWPOWTHRESHOLD     B43_PHY_N(0x273)
0802 #define B43_NPHY_CRSHIGHPOWTHRESHOLD1L      B43_PHY_N(0x274)
0803 #define B43_NPHY_CRSHIGHPOWTHRESHOLD2L      B43_PHY_N(0x275)
0804 #define B43_NPHY_CRSHIGHLOWPOWTHRESHOLDL    B43_PHY_N(0x276)
0805 #define B43_NPHY_CRSHIGHPOWTHRESHOLD1U      B43_PHY_N(0x277)
0806 #define B43_NPHY_CRSHIGHPOWTHRESHOLD2U      B43_PHY_N(0x278)
0807 #define B43_NPHY_CRSHIGHLOWPOWTHRESHOLDU    B43_PHY_N(0x279)
0808 #define B43_NPHY_CRSACIDETECTTHRESH     B43_PHY_N(0x27A)
0809 #define B43_NPHY_CRSACIDETECTTHRESHL        B43_PHY_N(0x27B)
0810 #define B43_NPHY_CRSACIDETECTTHRESHU        B43_PHY_N(0x27C)
0811 #define B43_NPHY_CRSMINPOWER0           B43_PHY_N(0x27D)
0812 #define B43_NPHY_CRSMINPOWER1           B43_PHY_N(0x27E)
0813 #define B43_NPHY_CRSMINPOWER2           B43_PHY_N(0x27F)
0814 #define B43_NPHY_CRSMINPOWERL0          B43_PHY_N(0x280)
0815 #define B43_NPHY_CRSMINPOWERL1          B43_PHY_N(0x281)
0816 #define B43_NPHY_CRSMINPOWERL2          B43_PHY_N(0x282)
0817 #define B43_NPHY_CRSMINPOWERU0          B43_PHY_N(0x283)
0818 #define B43_NPHY_CRSMINPOWERU1          B43_PHY_N(0x284)
0819 #define B43_NPHY_CRSMINPOWERU2          B43_PHY_N(0x285)
0820 #define B43_NPHY_STRPARAM           B43_PHY_N(0x286)
0821 #define B43_NPHY_STRPARAML          B43_PHY_N(0x287)
0822 #define B43_NPHY_STRPARAMU          B43_PHY_N(0x288)
0823 #define B43_NPHY_BPHYCRSMINPOWER0       B43_PHY_N(0x289)
0824 #define B43_NPHY_BPHYCRSMINPOWER1       B43_PHY_N(0x28A)
0825 #define B43_NPHY_BPHYCRSMINPOWER2       B43_PHY_N(0x28B)
0826 #define B43_NPHY_BPHYFILTDEN0COEF       B43_PHY_N(0x28C)
0827 #define B43_NPHY_BPHYFILTDEN1COEF       B43_PHY_N(0x28D)
0828 #define B43_NPHY_BPHYFILTDEN2COEF       B43_PHY_N(0x28E)
0829 #define B43_NPHY_BPHYFILTNUM0COEF       B43_PHY_N(0x28F)
0830 #define B43_NPHY_BPHYFILTNUM1COEF       B43_PHY_N(0x290)
0831 #define B43_NPHY_BPHYFILTNUM2COEF       B43_PHY_N(0x291)
0832 #define B43_NPHY_BPHYFILTNUM01COEF2     B43_PHY_N(0x292)
0833 #define B43_NPHY_BPHYFILTBYPASS         B43_PHY_N(0x293)
0834 #define B43_NPHY_SGILTRNOFFSET          B43_PHY_N(0x294)
0835 #define B43_NPHY_RADAR_T2_MIN           B43_PHY_N(0x295)
0836 #define B43_NPHY_TXPWRCTRLDAMPING       B43_PHY_N(0x296)
0837 #define B43_NPHY_PAPD_EN0           B43_PHY_N(0x297) /* PAPD Enable0 TBD */
0838 #define B43_NPHY_EPS_TABLE_ADJ0         B43_PHY_N(0x298) /* EPS Table Adj0 TBD */
0839 #define B43_NPHY_EPS_OVERRIDEI_0        B43_PHY_N(0x299)
0840 #define B43_NPHY_EPS_OVERRIDEQ_0        B43_PHY_N(0x29A)
0841 #define B43_NPHY_PAPD_EN1           B43_PHY_N(0x29B) /* PAPD Enable1 TBD */
0842 #define B43_NPHY_EPS_TABLE_ADJ1         B43_PHY_N(0x29C) /* EPS Table Adj1 TBD */
0843 #define B43_NPHY_EPS_OVERRIDEI_1        B43_PHY_N(0x29D)
0844 #define B43_NPHY_EPS_OVERRIDEQ_1        B43_PHY_N(0x29E)
0845 #define B43_NPHY_PAPD_CAL_ADDRESS       B43_PHY_N(0x29F)
0846 #define B43_NPHY_PAPD_CAL_YREFEPSILON       B43_PHY_N(0x2A0)
0847 #define B43_NPHY_PAPD_CAL_SETTLE        B43_PHY_N(0x2A1)
0848 #define B43_NPHY_PAPD_CAL_CORRELATE     B43_PHY_N(0x2A2)
0849 #define B43_NPHY_PAPD_CAL_SHIFTS0       B43_PHY_N(0x2A3)
0850 #define B43_NPHY_PAPD_CAL_SHIFTS1       B43_PHY_N(0x2A4)
0851 #define B43_NPHY_SAMPLE_START_ADDR      B43_PHY_N(0x2A5)
0852 #define B43_NPHY_RADAR_ADC_TO_DBM       B43_PHY_N(0x2A6)
0853 #define B43_NPHY_REV3_C2_INITGAIN_A     B43_PHY_N(0x2A7)
0854 #define B43_NPHY_REV3_C2_INITGAIN_B     B43_PHY_N(0x2A8)
0855 #define B43_NPHY_REV3_C2_CLIP_HIGAIN_A      B43_PHY_N(0x2A9)
0856 #define B43_NPHY_REV3_C2_CLIP_HIGAIN_B      B43_PHY_N(0x2AA)
0857 #define B43_NPHY_REV3_C2_CLIP_MEDGAIN_A     B43_PHY_N(0x2AB)
0858 #define B43_NPHY_REV3_C2_CLIP_MEDGAIN_B     B43_PHY_N(0x2AC)
0859 #define B43_NPHY_REV3_C2_CLIP_LOGAIN_A      B43_PHY_N(0x2AD)
0860 #define B43_NPHY_REV3_C2_CLIP_LOGAIN_B      B43_PHY_N(0x2AE)
0861 #define B43_NPHY_REV3_C2_CLIP2_GAIN_A       B43_PHY_N(0x2AF)
0862 #define B43_NPHY_REV3_C2_CLIP2_GAIN_B       B43_PHY_N(0x2B0)
0863 
0864 #define B43_NPHY_REV7_RF_CTL_MISC_REG3      B43_PHY_N(0x340)
0865 #define B43_NPHY_REV7_RF_CTL_MISC_REG4      B43_PHY_N(0x341)
0866 #define B43_NPHY_REV7_RF_CTL_OVER3      B43_PHY_N(0x342)
0867 #define B43_NPHY_REV7_RF_CTL_OVER4      B43_PHY_N(0x343)
0868 #define B43_NPHY_REV7_RF_CTL_MISC_REG5      B43_PHY_N(0x344)
0869 #define B43_NPHY_REV7_RF_CTL_MISC_REG6      B43_PHY_N(0x345)
0870 #define B43_NPHY_REV7_RF_CTL_OVER5      B43_PHY_N(0x346)
0871 #define B43_NPHY_REV7_RF_CTL_OVER6      B43_PHY_N(0x347)
0872 
0873 #define B43_PHY_B_BBCFG             B43_PHY_N_BMODE(0x001) /* BB config */
0874 #define  B43_PHY_B_BBCFG_RSTCCA         0x4000 /* Reset CCA */
0875 #define  B43_PHY_B_BBCFG_RSTRX          0x8000 /* Reset RX */
0876 #define B43_PHY_B_TEST              B43_PHY_N_BMODE(0x00A)
0877 
0878 struct b43_wldev;
0879 
0880 enum b43_nphy_spur_avoid {
0881     B43_SPUR_AVOID_DISABLE,
0882     B43_SPUR_AVOID_AUTO,
0883     B43_SPUR_AVOID_FORCE,
0884 };
0885 
0886 struct b43_chanspec {
0887     u16 center_freq;
0888     enum nl80211_channel_type channel_type;
0889 };
0890 
0891 struct b43_phy_n_iq_comp {
0892     s16 a0;
0893     s16 b0;
0894     s16 a1;
0895     s16 b1;
0896 };
0897 
0898 struct b43_phy_n_rssical_cache {
0899     u16 rssical_radio_regs_2G[2];
0900     u16 rssical_phy_regs_2G[12];
0901 
0902     u16 rssical_radio_regs_5G[2];
0903     u16 rssical_phy_regs_5G[12];
0904 };
0905 
0906 struct b43_phy_n_cal_cache {
0907     u16 txcal_radio_regs_2G[8];
0908     u16 txcal_coeffs_2G[8];
0909     struct b43_phy_n_iq_comp rxcal_coeffs_2G;
0910 
0911     u16 txcal_radio_regs_5G[8];
0912     u16 txcal_coeffs_5G[8];
0913     struct b43_phy_n_iq_comp rxcal_coeffs_5G;
0914 };
0915 
0916 struct b43_phy_n_txpwrindex {
0917     s8 index;
0918     s8 index_internal;
0919     s8 index_internal_save;
0920     u16 AfectrlOverride;
0921     u16 AfeCtrlDacGain;
0922     u16 rad_gain;
0923     u8 bbmult;
0924     u16 iqcomp_a;
0925     u16 iqcomp_b;
0926     u16 locomp;
0927 };
0928 
0929 struct b43_phy_n_pwr_ctl_info {
0930     u8 idle_tssi_2g;
0931     u8 idle_tssi_5g;
0932 };
0933 
0934 struct b43_phy_n {
0935     u8 antsel_type;
0936     u8 cal_orig_pwr_idx[2];
0937     u8 measure_hold;
0938     u8 phyrxchain;
0939     u8 hw_phyrxchain;
0940     u8 hw_phytxchain;
0941     u8 perical;
0942     u32 deaf_count;
0943     u32 rxcalparams;
0944     bool hang_avoid;
0945     bool mute;
0946     u16 papd_epsilon_offset[2];
0947     s32 preamble_override;
0948     u32 bb_mult_save;
0949 
0950     bool gain_boost;
0951     bool elna_gain_config;
0952     bool band5g_pwrgain;
0953     bool use_int_tx_iq_lo_cal;
0954     bool lpf_bw_overrode_for_sample_play;
0955 
0956     u8 mphase_cal_phase_id;
0957     u16 mphase_txcal_cmdidx;
0958     u16 mphase_txcal_numcmds;
0959     u16 mphase_txcal_bestcoeffs[11];
0960 
0961     bool txpwrctrl;
0962     bool pwg_gain_5ghz;
0963     u8 tx_pwr_idx[2];
0964     s8 tx_power_offset[101];
0965     u16 adj_pwr_tbl[84];
0966     u16 txcal_bbmult;
0967     u16 txiqlocal_bestc[11];
0968     bool txiqlocal_coeffsvalid;
0969     struct b43_phy_n_txpwrindex txpwrindex[2];
0970     struct b43_phy_n_pwr_ctl_info pwr_ctl_info[2];
0971     struct b43_chanspec txiqlocal_chanspec;
0972     struct b43_ppr tx_pwr_max_ppr;
0973     u16 tx_pwr_last_recalc_freq;
0974     int tx_pwr_last_recalc_limit;
0975 
0976     u8 txrx_chain;
0977     u16 tx_rx_cal_phy_saveregs[11];
0978     u16 tx_rx_cal_radio_saveregs[22];
0979 
0980     u16 rfctrl_intc1_save;
0981     u16 rfctrl_intc2_save;
0982 
0983     u16 classifier_state;
0984     u16 clip_state[2];
0985 
0986     enum b43_nphy_spur_avoid spur_avoid;
0987     bool aband_spurwar_en;
0988     bool gband_spurwar_en;
0989 
0990     bool ipa2g_on;
0991     struct b43_chanspec iqcal_chanspec_2G;
0992     struct b43_chanspec rssical_chanspec_2G;
0993 
0994     bool ipa5g_on;
0995     struct b43_chanspec iqcal_chanspec_5G;
0996     struct b43_chanspec rssical_chanspec_5G;
0997 
0998     struct b43_phy_n_rssical_cache rssical_cache;
0999     struct b43_phy_n_cal_cache cal_cache;
1000     bool crsminpwr_adjusted;
1001     bool noisevars_adjusted;
1002 };
1003 
1004 
1005 struct b43_phy_operations;
1006 extern const struct b43_phy_operations b43_phyops_n;
1007 
1008 #endif /* B43_NPHY_H_ */
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