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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 
0004   Broadcom B43 wireless driver
0005   IEEE 802.11n HT-PHY support
0006 
0007   Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com>
0008 
0009 
0010 */
0011 
0012 #include <linux/slab.h>
0013 
0014 #include "b43.h"
0015 #include "phy_ht.h"
0016 #include "tables_phy_ht.h"
0017 #include "radio_2059.h"
0018 #include "main.h"
0019 
0020 /* Force values to keep compatibility with wl */
0021 enum ht_rssi_type {
0022     HT_RSSI_W1 = 0,
0023     HT_RSSI_W2 = 1,
0024     HT_RSSI_NB = 2,
0025     HT_RSSI_IQ = 3,
0026     HT_RSSI_TSSI_2G = 4,
0027     HT_RSSI_TSSI_5G = 5,
0028     HT_RSSI_TBD = 6,
0029 };
0030 
0031 /**************************************************
0032  * Radio 2059.
0033  **************************************************/
0034 
0035 static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
0036             const struct b43_phy_ht_channeltab_e_radio2059 *e)
0037 {
0038     static const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3, };
0039     u16 r;
0040     int core;
0041 
0042     b43_radio_write(dev, 0x16, e->radio_syn16);
0043     b43_radio_write(dev, 0x17, e->radio_syn17);
0044     b43_radio_write(dev, 0x22, e->radio_syn22);
0045     b43_radio_write(dev, 0x25, e->radio_syn25);
0046     b43_radio_write(dev, 0x27, e->radio_syn27);
0047     b43_radio_write(dev, 0x28, e->radio_syn28);
0048     b43_radio_write(dev, 0x29, e->radio_syn29);
0049     b43_radio_write(dev, 0x2c, e->radio_syn2c);
0050     b43_radio_write(dev, 0x2d, e->radio_syn2d);
0051     b43_radio_write(dev, 0x37, e->radio_syn37);
0052     b43_radio_write(dev, 0x41, e->radio_syn41);
0053     b43_radio_write(dev, 0x43, e->radio_syn43);
0054     b43_radio_write(dev, 0x47, e->radio_syn47);
0055 
0056     for (core = 0; core < 3; core++) {
0057         r = routing[core];
0058         b43_radio_write(dev, r | 0x4a, e->radio_rxtx4a);
0059         b43_radio_write(dev, r | 0x58, e->radio_rxtx58);
0060         b43_radio_write(dev, r | 0x5a, e->radio_rxtx5a);
0061         b43_radio_write(dev, r | 0x6a, e->radio_rxtx6a);
0062         b43_radio_write(dev, r | 0x6d, e->radio_rxtx6d);
0063         b43_radio_write(dev, r | 0x6e, e->radio_rxtx6e);
0064         b43_radio_write(dev, r | 0x92, e->radio_rxtx92);
0065         b43_radio_write(dev, r | 0x98, e->radio_rxtx98);
0066     }
0067 
0068     udelay(50);
0069 
0070     /* Calibration */
0071     b43_radio_mask(dev, R2059_RFPLL_MISC_EN, ~0x1);
0072     b43_radio_mask(dev, R2059_RFPLL_MISC_CAL_RESETN, ~0x4);
0073     b43_radio_set(dev, R2059_RFPLL_MISC_CAL_RESETN, 0x4);
0074     b43_radio_set(dev, R2059_RFPLL_MISC_EN, 0x1);
0075 
0076     udelay(300);
0077 }
0078 
0079 /* Calibrate resistors in LPF of PLL? */
0080 static void b43_radio_2059_rcal(struct b43_wldev *dev)
0081 {
0082     /* Enable */
0083     b43_radio_set(dev, R2059_C3 | R2059_RCAL_CONFIG, 0x1);
0084     usleep_range(10, 20);
0085 
0086     b43_radio_set(dev, R2059_C3 | 0x0BF, 0x1);
0087     b43_radio_maskset(dev, R2059_C3 | 0x19B, 0x3, 0x2);
0088 
0089     /* Start */
0090     b43_radio_set(dev, R2059_C3 | R2059_RCAL_CONFIG, 0x2);
0091     usleep_range(100, 200);
0092 
0093     /* Stop */
0094     b43_radio_mask(dev, R2059_C3 | R2059_RCAL_CONFIG, ~0x2);
0095 
0096     if (!b43_radio_wait_value(dev, R2059_C3 | R2059_RCAL_STATUS, 1, 1, 100,
0097                   1000000))
0098         b43err(dev->wl, "Radio 0x2059 rcal timeout\n");
0099 
0100     /* Disable */
0101     b43_radio_mask(dev, R2059_C3 | R2059_RCAL_CONFIG, ~0x1);
0102 
0103     b43_radio_set(dev, 0xa, 0x60);
0104 }
0105 
0106 /* Calibrate the internal RC oscillator? */
0107 static void b43_radio_2057_rccal(struct b43_wldev *dev)
0108 {
0109     static const u16 radio_values[3][2] = {
0110         { 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 },
0111     };
0112     int i;
0113 
0114     for (i = 0; i < 3; i++) {
0115         b43_radio_write(dev, R2059_RCCAL_MASTER, radio_values[i][0]);
0116         b43_radio_write(dev, R2059_RCCAL_X1, 0x6E);
0117         b43_radio_write(dev, R2059_RCCAL_TRC0, radio_values[i][1]);
0118 
0119         /* Start */
0120         b43_radio_write(dev, R2059_RCCAL_START_R1_Q1_P1, 0x55);
0121 
0122         /* Wait */
0123         if (!b43_radio_wait_value(dev, R2059_RCCAL_DONE_OSCCAP, 2, 2,
0124                       500, 5000000))
0125             b43err(dev->wl, "Radio 0x2059 rccal timeout\n");
0126 
0127         /* Stop */
0128         b43_radio_write(dev, R2059_RCCAL_START_R1_Q1_P1, 0x15);
0129     }
0130 
0131     b43_radio_mask(dev, R2059_RCCAL_MASTER, ~0x1);
0132 }
0133 
0134 static void b43_radio_2059_init_pre(struct b43_wldev *dev)
0135 {
0136     b43_phy_mask(dev, B43_PHY_HT_RF_CTL_CMD, ~B43_PHY_HT_RF_CTL_CMD_CHIP0_PU);
0137     b43_phy_set(dev, B43_PHY_HT_RF_CTL_CMD, B43_PHY_HT_RF_CTL_CMD_FORCE);
0138     b43_phy_mask(dev, B43_PHY_HT_RF_CTL_CMD, ~B43_PHY_HT_RF_CTL_CMD_FORCE);
0139     b43_phy_set(dev, B43_PHY_HT_RF_CTL_CMD, B43_PHY_HT_RF_CTL_CMD_CHIP0_PU);
0140 }
0141 
0142 static void b43_radio_2059_init(struct b43_wldev *dev)
0143 {
0144     static const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3 };
0145     int i;
0146 
0147     /* Prepare (reset?) radio */
0148     b43_radio_2059_init_pre(dev);
0149 
0150     r2059_upload_inittabs(dev);
0151 
0152     for (i = 0; i < ARRAY_SIZE(routing); i++)
0153         b43_radio_set(dev, routing[i] | 0x146, 0x3);
0154 
0155     /* Post init starts below */
0156 
0157     b43_radio_set(dev, R2059_RFPLL_MISC_CAL_RESETN, 0x0078);
0158     b43_radio_set(dev, R2059_XTAL_CONFIG2, 0x0080);
0159     msleep(2);
0160     b43_radio_mask(dev, R2059_RFPLL_MISC_CAL_RESETN, ~0x0078);
0161     b43_radio_mask(dev, R2059_XTAL_CONFIG2, ~0x0080);
0162 
0163     if (1) { /* FIXME */
0164         b43_radio_2059_rcal(dev);
0165         b43_radio_2057_rccal(dev);
0166     }
0167 
0168     b43_radio_mask(dev, R2059_RFPLL_MASTER, ~0x0008);
0169 }
0170 
0171 /**************************************************
0172  * RF
0173  **************************************************/
0174 
0175 static void b43_phy_ht_force_rf_sequence(struct b43_wldev *dev, u16 rf_seq)
0176 {
0177     u8 i;
0178 
0179     u16 save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE);
0180     b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE, 0x3);
0181 
0182     b43_phy_set(dev, B43_PHY_HT_RF_SEQ_TRIG, rf_seq);
0183     for (i = 0; i < 200; i++) {
0184         if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & rf_seq)) {
0185             i = 0;
0186             break;
0187         }
0188         msleep(1);
0189     }
0190     if (i)
0191         b43err(dev->wl, "Forcing RF sequence timeout\n");
0192 
0193     b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode);
0194 }
0195 
0196 static void b43_phy_ht_pa_override(struct b43_wldev *dev, bool enable)
0197 {
0198     struct b43_phy_ht *htphy = dev->phy.ht;
0199     static const u16 regs[3] = { B43_PHY_HT_RF_CTL_INT_C1,
0200                      B43_PHY_HT_RF_CTL_INT_C2,
0201                      B43_PHY_HT_RF_CTL_INT_C3 };
0202     int i;
0203 
0204     if (enable) {
0205         for (i = 0; i < 3; i++)
0206             b43_phy_write(dev, regs[i], htphy->rf_ctl_int_save[i]);
0207     } else {
0208         for (i = 0; i < 3; i++)
0209             htphy->rf_ctl_int_save[i] = b43_phy_read(dev, regs[i]);
0210         /* TODO: Does 5GHz band use different value (not 0x0400)? */
0211         for (i = 0; i < 3; i++)
0212             b43_phy_write(dev, regs[i], 0x0400);
0213     }
0214 }
0215 
0216 /**************************************************
0217  * Various PHY ops
0218  **************************************************/
0219 
0220 static u16 b43_phy_ht_classifier(struct b43_wldev *dev, u16 mask, u16 val)
0221 {
0222     u16 tmp;
0223     u16 allowed = B43_PHY_HT_CLASS_CTL_CCK_EN |
0224               B43_PHY_HT_CLASS_CTL_OFDM_EN |
0225               B43_PHY_HT_CLASS_CTL_WAITED_EN;
0226 
0227     tmp = b43_phy_read(dev, B43_PHY_HT_CLASS_CTL);
0228     tmp &= allowed;
0229     tmp &= ~mask;
0230     tmp |= (val & mask);
0231     b43_phy_maskset(dev, B43_PHY_HT_CLASS_CTL, ~allowed, tmp);
0232 
0233     return tmp;
0234 }
0235 
0236 static void b43_phy_ht_reset_cca(struct b43_wldev *dev)
0237 {
0238     u16 bbcfg;
0239 
0240     b43_phy_force_clock(dev, true);
0241     bbcfg = b43_phy_read(dev, B43_PHY_HT_BBCFG);
0242     b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg | B43_PHY_HT_BBCFG_RSTCCA);
0243     udelay(1);
0244     b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg & ~B43_PHY_HT_BBCFG_RSTCCA);
0245     b43_phy_force_clock(dev, false);
0246 
0247     b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
0248 }
0249 
0250 static void b43_phy_ht_zero_extg(struct b43_wldev *dev)
0251 {
0252     u8 i, j;
0253     static const u16 base[] = { 0x40, 0x60, 0x80 };
0254 
0255     for (i = 0; i < ARRAY_SIZE(base); i++) {
0256         for (j = 0; j < 4; j++)
0257             b43_phy_write(dev, B43_PHY_EXTG(base[i] + j), 0);
0258     }
0259 
0260     for (i = 0; i < ARRAY_SIZE(base); i++)
0261         b43_phy_write(dev, B43_PHY_EXTG(base[i] + 0xc), 0);
0262 }
0263 
0264 /* Some unknown AFE (Analog Frondned) op */
0265 static void b43_phy_ht_afe_unk1(struct b43_wldev *dev)
0266 {
0267     u8 i;
0268 
0269     static const u16 ctl_regs[3][2] = {
0270         { B43_PHY_HT_AFE_C1_OVER, B43_PHY_HT_AFE_C1 },
0271         { B43_PHY_HT_AFE_C2_OVER, B43_PHY_HT_AFE_C2 },
0272         { B43_PHY_HT_AFE_C3_OVER, B43_PHY_HT_AFE_C3},
0273     };
0274 
0275     for (i = 0; i < 3; i++) {
0276         /* TODO: verify masks&sets */
0277         b43_phy_set(dev, ctl_regs[i][1], 0x4);
0278         b43_phy_set(dev, ctl_regs[i][0], 0x4);
0279         b43_phy_mask(dev, ctl_regs[i][1], ~0x1);
0280         b43_phy_set(dev, ctl_regs[i][0], 0x1);
0281         b43_httab_write(dev, B43_HTTAB16(8, 5 + (i * 0x10)), 0);
0282         b43_phy_mask(dev, ctl_regs[i][0], ~0x4);
0283     }
0284 }
0285 
0286 static void b43_phy_ht_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
0287 {
0288     clip_st[0] = b43_phy_read(dev, B43_PHY_HT_C1_CLIP1THRES);
0289     clip_st[1] = b43_phy_read(dev, B43_PHY_HT_C2_CLIP1THRES);
0290     clip_st[2] = b43_phy_read(dev, B43_PHY_HT_C3_CLIP1THRES);
0291 }
0292 
0293 static void b43_phy_ht_bphy_init(struct b43_wldev *dev)
0294 {
0295     unsigned int i;
0296     u16 val;
0297 
0298     val = 0x1E1F;
0299     for (i = 0; i < 16; i++) {
0300         b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
0301         val -= 0x202;
0302     }
0303     val = 0x3E3F;
0304     for (i = 0; i < 16; i++) {
0305         b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
0306         val -= 0x202;
0307     }
0308     b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
0309 }
0310 
0311 static void b43_phy_ht_bphy_reset(struct b43_wldev *dev, bool reset)
0312 {
0313     u16 tmp;
0314 
0315     tmp = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
0316     b43_write16(dev, B43_MMIO_PSM_PHY_HDR,
0317             tmp | B43_PSM_HDR_MAC_PHY_FORCE_CLK);
0318 
0319     /* Put BPHY in or take it out of the reset */
0320     if (reset)
0321         b43_phy_set(dev, B43_PHY_B_BBCFG,
0322                 B43_PHY_B_BBCFG_RSTCCA | B43_PHY_B_BBCFG_RSTRX);
0323     else
0324         b43_phy_mask(dev, B43_PHY_B_BBCFG,
0325                  (u16)~(B43_PHY_B_BBCFG_RSTCCA |
0326                     B43_PHY_B_BBCFG_RSTRX));
0327 
0328     b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp);
0329 }
0330 
0331 /**************************************************
0332  * Samples
0333  **************************************************/
0334 
0335 static void b43_phy_ht_stop_playback(struct b43_wldev *dev)
0336 {
0337     struct b43_phy_ht *phy_ht = dev->phy.ht;
0338     u16 tmp;
0339     int i;
0340 
0341     tmp = b43_phy_read(dev, B43_PHY_HT_SAMP_STAT);
0342     if (tmp & 0x1)
0343         b43_phy_set(dev, B43_PHY_HT_SAMP_CMD, B43_PHY_HT_SAMP_CMD_STOP);
0344     else if (tmp & 0x2)
0345         b43_phy_mask(dev, B43_PHY_HT_IQLOCAL_CMDGCTL, 0x7FFF);
0346 
0347     b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0x0004);
0348 
0349     for (i = 0; i < 3; i++) {
0350         if (phy_ht->bb_mult_save[i] >= 0) {
0351             b43_httab_write(dev, B43_HTTAB16(13, 0x63 + i * 4),
0352                     phy_ht->bb_mult_save[i]);
0353             b43_httab_write(dev, B43_HTTAB16(13, 0x67 + i * 4),
0354                     phy_ht->bb_mult_save[i]);
0355         }
0356     }
0357 }
0358 
0359 static u16 b43_phy_ht_load_samples(struct b43_wldev *dev)
0360 {
0361     int i;
0362     u16 len = 20 << 3;
0363 
0364     b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, 0x4400);
0365 
0366     for (i = 0; i < len; i++) {
0367         b43_phy_write(dev, B43_PHY_HT_TABLE_DATAHI, 0);
0368         b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, 0);
0369     }
0370 
0371     return len;
0372 }
0373 
0374 static void b43_phy_ht_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
0375                    u16 wait)
0376 {
0377     struct b43_phy_ht *phy_ht = dev->phy.ht;
0378     u16 save_seq_mode;
0379     int i;
0380 
0381     for (i = 0; i < 3; i++) {
0382         if (phy_ht->bb_mult_save[i] < 0)
0383             phy_ht->bb_mult_save[i] = b43_httab_read(dev, B43_HTTAB16(13, 0x63 + i * 4));
0384     }
0385 
0386     b43_phy_write(dev, B43_PHY_HT_SAMP_DEP_CNT, samps - 1);
0387     if (loops != 0xFFFF)
0388         loops--;
0389     b43_phy_write(dev, B43_PHY_HT_SAMP_LOOP_CNT, loops);
0390     b43_phy_write(dev, B43_PHY_HT_SAMP_WAIT_CNT, wait);
0391 
0392     save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE);
0393     b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE,
0394             B43_PHY_HT_RF_SEQ_MODE_CA_OVER);
0395 
0396     /* TODO: find out mask bits! Do we need more function arguments? */
0397     b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0);
0398     b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0);
0399     b43_phy_mask(dev, B43_PHY_HT_IQLOCAL_CMDGCTL, ~0);
0400     b43_phy_set(dev, B43_PHY_HT_SAMP_CMD, 0x1);
0401 
0402     for (i = 0; i < 100; i++) {
0403         if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & 1)) {
0404             i = 0;
0405             break;
0406         }
0407         udelay(10);
0408     }
0409     if (i)
0410         b43err(dev->wl, "run samples timeout\n");
0411 
0412     b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode);
0413 }
0414 
0415 static void b43_phy_ht_tx_tone(struct b43_wldev *dev)
0416 {
0417     u16 samp;
0418 
0419     samp = b43_phy_ht_load_samples(dev);
0420     b43_phy_ht_run_samples(dev, samp, 0xFFFF, 0);
0421 }
0422 
0423 /**************************************************
0424  * RSSI
0425  **************************************************/
0426 
0427 static void b43_phy_ht_rssi_select(struct b43_wldev *dev, u8 core_sel,
0428                    enum ht_rssi_type rssi_type)
0429 {
0430     static const u16 ctl_regs[3][2] = {
0431         { B43_PHY_HT_AFE_C1, B43_PHY_HT_AFE_C1_OVER, },
0432         { B43_PHY_HT_AFE_C2, B43_PHY_HT_AFE_C2_OVER, },
0433         { B43_PHY_HT_AFE_C3, B43_PHY_HT_AFE_C3_OVER, },
0434     };
0435     static const u16 radio_r[] = { R2059_C1, R2059_C2, R2059_C3, };
0436     int core;
0437 
0438     if (core_sel == 0) {
0439         b43err(dev->wl, "RSSI selection for core off not implemented yet\n");
0440     } else {
0441         for (core = 0; core < 3; core++) {
0442             /* Check if caller requested a one specific core */
0443             if ((core_sel == 1 && core != 0) ||
0444                 (core_sel == 2 && core != 1) ||
0445                 (core_sel == 3 && core != 2))
0446                 continue;
0447 
0448             switch (rssi_type) {
0449             case HT_RSSI_TSSI_2G:
0450                 b43_phy_set(dev, ctl_regs[core][0], 0x3 << 8);
0451                 b43_phy_set(dev, ctl_regs[core][0], 0x3 << 10);
0452                 b43_phy_set(dev, ctl_regs[core][1], 0x1 << 9);
0453                 b43_phy_set(dev, ctl_regs[core][1], 0x1 << 10);
0454 
0455                 b43_radio_set(dev, R2059_C3 | 0xbf, 0x1);
0456                 b43_radio_write(dev, radio_r[core] | 0x159,
0457                         0x11);
0458                 break;
0459             default:
0460                 b43err(dev->wl, "RSSI selection for type %d not implemented yet\n",
0461                        rssi_type);
0462             }
0463         }
0464     }
0465 }
0466 
0467 static void b43_phy_ht_poll_rssi(struct b43_wldev *dev, enum ht_rssi_type type,
0468                  s32 *buf, u8 nsamp)
0469 {
0470     u16 phy_regs_values[12];
0471     static const u16 phy_regs_to_save[] = {
0472         B43_PHY_HT_AFE_C1, B43_PHY_HT_AFE_C1_OVER,
0473         0x848, 0x841,
0474         B43_PHY_HT_AFE_C2, B43_PHY_HT_AFE_C2_OVER,
0475         0x868, 0x861,
0476         B43_PHY_HT_AFE_C3, B43_PHY_HT_AFE_C3_OVER,
0477         0x888, 0x881,
0478     };
0479     u16 tmp[3];
0480     int i;
0481 
0482     for (i = 0; i < 12; i++)
0483         phy_regs_values[i] = b43_phy_read(dev, phy_regs_to_save[i]);
0484 
0485     b43_phy_ht_rssi_select(dev, 5, type);
0486 
0487     for (i = 0; i < 6; i++)
0488         buf[i] = 0;
0489 
0490     for (i = 0; i < nsamp; i++) {
0491         tmp[0] = b43_phy_read(dev, B43_PHY_HT_RSSI_C1);
0492         tmp[1] = b43_phy_read(dev, B43_PHY_HT_RSSI_C2);
0493         tmp[2] = b43_phy_read(dev, B43_PHY_HT_RSSI_C3);
0494 
0495         buf[0] += ((s8)((tmp[0] & 0x3F) << 2)) >> 2;
0496         buf[1] += ((s8)(((tmp[0] >> 8) & 0x3F) << 2)) >> 2;
0497         buf[2] += ((s8)((tmp[1] & 0x3F) << 2)) >> 2;
0498         buf[3] += ((s8)(((tmp[1] >> 8) & 0x3F) << 2)) >> 2;
0499         buf[4] += ((s8)((tmp[2] & 0x3F) << 2)) >> 2;
0500         buf[5] += ((s8)(((tmp[2] >> 8) & 0x3F) << 2)) >> 2;
0501     }
0502 
0503     for (i = 0; i < 12; i++)
0504         b43_phy_write(dev, phy_regs_to_save[i], phy_regs_values[i]);
0505 }
0506 
0507 /**************************************************
0508  * Tx/Rx
0509  **************************************************/
0510 
0511 static void b43_phy_ht_tx_power_fix(struct b43_wldev *dev)
0512 {
0513     int i;
0514 
0515     for (i = 0; i < 3; i++) {
0516         u16 mask;
0517         u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8));
0518 
0519         if (0) /* FIXME */
0520             mask = 0x2 << (i * 4);
0521         else
0522             mask = 0;
0523         b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask);
0524 
0525         b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16);
0526         b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)),
0527                 tmp & 0xFF);
0528         b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)),
0529                 tmp & 0xFF);
0530     }
0531 }
0532 
0533 static void b43_phy_ht_tx_power_ctl(struct b43_wldev *dev, bool enable)
0534 {
0535     struct b43_phy_ht *phy_ht = dev->phy.ht;
0536     u16 en_bits = B43_PHY_HT_TXPCTL_CMD_C1_COEFF |
0537               B43_PHY_HT_TXPCTL_CMD_C1_HWPCTLEN |
0538               B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN;
0539     static const u16 cmd_regs[3] = { B43_PHY_HT_TXPCTL_CMD_C1,
0540                      B43_PHY_HT_TXPCTL_CMD_C2,
0541                      B43_PHY_HT_TXPCTL_CMD_C3 };
0542     static const u16 status_regs[3] = { B43_PHY_HT_TX_PCTL_STATUS_C1,
0543                         B43_PHY_HT_TX_PCTL_STATUS_C2,
0544                         B43_PHY_HT_TX_PCTL_STATUS_C3 };
0545     int i;
0546 
0547     if (!enable) {
0548         if (b43_phy_read(dev, B43_PHY_HT_TXPCTL_CMD_C1) & en_bits) {
0549             /* We disable enabled TX pwr ctl, save it's state */
0550             for (i = 0; i < 3; i++)
0551                 phy_ht->tx_pwr_idx[i] =
0552                     b43_phy_read(dev, status_regs[i]);
0553         }
0554         b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1, ~en_bits);
0555     } else {
0556         b43_phy_set(dev, B43_PHY_HT_TXPCTL_CMD_C1, en_bits);
0557 
0558         if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) {
0559             for (i = 0; i < 3; i++)
0560                 b43_phy_write(dev, cmd_regs[i], 0x32);
0561         }
0562 
0563         for (i = 0; i < 3; i++)
0564             if (phy_ht->tx_pwr_idx[i] <=
0565                 B43_PHY_HT_TXPCTL_CMD_C1_INIT)
0566                 b43_phy_write(dev, cmd_regs[i],
0567                           phy_ht->tx_pwr_idx[i]);
0568     }
0569 
0570     phy_ht->tx_pwr_ctl = enable;
0571 }
0572 
0573 static void b43_phy_ht_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
0574 {
0575     struct b43_phy_ht *phy_ht = dev->phy.ht;
0576     static const u16 base[] = { 0x840, 0x860, 0x880 };
0577     u16 save_regs[3][3];
0578     s32 rssi_buf[6];
0579     int core;
0580 
0581     for (core = 0; core < 3; core++) {
0582         save_regs[core][1] = b43_phy_read(dev, base[core] + 6);
0583         save_regs[core][2] = b43_phy_read(dev, base[core] + 7);
0584         save_regs[core][0] = b43_phy_read(dev, base[core] + 0);
0585 
0586         b43_phy_write(dev, base[core] + 6, 0);
0587         b43_phy_mask(dev, base[core] + 7, ~0xF); /* 0xF? Or just 0x6? */
0588         b43_phy_set(dev, base[core] + 0, 0x0400);
0589         b43_phy_set(dev, base[core] + 0, 0x1000);
0590     }
0591 
0592     b43_phy_ht_tx_tone(dev);
0593     udelay(20);
0594     b43_phy_ht_poll_rssi(dev, HT_RSSI_TSSI_2G, rssi_buf, 1);
0595     b43_phy_ht_stop_playback(dev);
0596     b43_phy_ht_reset_cca(dev);
0597 
0598     phy_ht->idle_tssi[0] = rssi_buf[0] & 0xff;
0599     phy_ht->idle_tssi[1] = rssi_buf[2] & 0xff;
0600     phy_ht->idle_tssi[2] = rssi_buf[4] & 0xff;
0601 
0602     for (core = 0; core < 3; core++) {
0603         b43_phy_write(dev, base[core] + 0, save_regs[core][0]);
0604         b43_phy_write(dev, base[core] + 6, save_regs[core][1]);
0605         b43_phy_write(dev, base[core] + 7, save_regs[core][2]);
0606     }
0607 }
0608 
0609 static void b43_phy_ht_tssi_setup(struct b43_wldev *dev)
0610 {
0611     static const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3, };
0612     int core;
0613 
0614     /* 0x159 is probably TX_SSI_MUX or TSSIG (by comparing to N-PHY) */
0615     for (core = 0; core < 3; core++) {
0616         b43_radio_set(dev, 0x8bf, 0x1);
0617         b43_radio_write(dev, routing[core] | 0x0159, 0x0011);
0618     }
0619 }
0620 
0621 static void b43_phy_ht_tx_power_ctl_setup(struct b43_wldev *dev)
0622 {
0623     struct b43_phy_ht *phy_ht = dev->phy.ht;
0624     struct ssb_sprom *sprom = dev->dev->bus_sprom;
0625 
0626     u8 *idle = phy_ht->idle_tssi;
0627     u8 target[3];
0628     s16 a1[3], b0[3], b1[3];
0629 
0630     u16 freq = dev->phy.chandef->chan->center_freq;
0631     int i, c;
0632 
0633     if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {
0634         for (c = 0; c < 3; c++) {
0635             target[c] = sprom->core_pwr_info[c].maxpwr_2g;
0636             a1[c] = sprom->core_pwr_info[c].pa_2g[0];
0637             b0[c] = sprom->core_pwr_info[c].pa_2g[1];
0638             b1[c] = sprom->core_pwr_info[c].pa_2g[2];
0639         }
0640     } else if (freq >= 4900 && freq < 5100) {
0641         for (c = 0; c < 3; c++) {
0642             target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
0643             a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
0644             b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
0645             b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
0646         }
0647     } else if (freq >= 5100 && freq < 5500) {
0648         for (c = 0; c < 3; c++) {
0649             target[c] = sprom->core_pwr_info[c].maxpwr_5g;
0650             a1[c] = sprom->core_pwr_info[c].pa_5g[0];
0651             b0[c] = sprom->core_pwr_info[c].pa_5g[1];
0652             b1[c] = sprom->core_pwr_info[c].pa_5g[2];
0653         }
0654     } else if (freq >= 5500) {
0655         for (c = 0; c < 3; c++) {
0656             target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
0657             a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
0658             b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
0659             b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
0660         }
0661     } else {
0662         target[0] = target[1] = target[2] = 52;
0663         a1[0] = a1[1] = a1[2] = -424;
0664         b0[0] = b0[1] = b0[2] = 5612;
0665         b1[0] = b1[1] = b1[2] = -1393;
0666     }
0667 
0668     b43_phy_set(dev, B43_PHY_HT_TSSIMODE, B43_PHY_HT_TSSIMODE_EN);
0669     b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1,
0670              ~B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN & 0xFFFF);
0671 
0672     /* TODO: Does it depend on sprom->fem.ghz2.tssipos? */
0673     b43_phy_set(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI, 0x4000);
0674 
0675     b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1,
0676             ~B43_PHY_HT_TXPCTL_CMD_C1_INIT, 0x19);
0677     b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C2,
0678             ~B43_PHY_HT_TXPCTL_CMD_C2_INIT, 0x19);
0679     b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C3,
0680             ~B43_PHY_HT_TXPCTL_CMD_C3_INIT, 0x19);
0681 
0682     b43_phy_set(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI,
0683             B43_PHY_HT_TXPCTL_IDLE_TSSI_BINF);
0684 
0685     b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI,
0686             ~B43_PHY_HT_TXPCTL_IDLE_TSSI_C1,
0687             idle[0] << B43_PHY_HT_TXPCTL_IDLE_TSSI_C1_SHIFT);
0688     b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI,
0689             ~B43_PHY_HT_TXPCTL_IDLE_TSSI_C2,
0690             idle[1] << B43_PHY_HT_TXPCTL_IDLE_TSSI_C2_SHIFT);
0691     b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI2,
0692             ~B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3,
0693             idle[2] << B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3_SHIFT);
0694 
0695     b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_N, ~B43_PHY_HT_TXPCTL_N_TSSID,
0696             0xf0);
0697     b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_N, ~B43_PHY_HT_TXPCTL_N_NPTIL2,
0698             0x3 << B43_PHY_HT_TXPCTL_N_NPTIL2_SHIFT);
0699 #if 0
0700     /* TODO: what to mask/set? */
0701     b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1, 0x800, 0)
0702     b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1, 0x400, 0)
0703 #endif
0704 
0705     b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR,
0706             ~B43_PHY_HT_TXPCTL_TARG_PWR_C1,
0707             target[0] << B43_PHY_HT_TXPCTL_TARG_PWR_C1_SHIFT);
0708     b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR,
0709             ~B43_PHY_HT_TXPCTL_TARG_PWR_C2 & 0xFFFF,
0710             target[1] << B43_PHY_HT_TXPCTL_TARG_PWR_C2_SHIFT);
0711     b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR2,
0712             ~B43_PHY_HT_TXPCTL_TARG_PWR2_C3,
0713             target[2] << B43_PHY_HT_TXPCTL_TARG_PWR2_C3_SHIFT);
0714 
0715     for (c = 0; c < 3; c++) {
0716         s32 num, den, pwr;
0717         u32 regval[64];
0718 
0719         for (i = 0; i < 64; i++) {
0720             num = 8 * (16 * b0[c] + b1[c] * i);
0721             den = 32768 + a1[c] * i;
0722             pwr = max((4 * num + den / 2) / den, -8);
0723             regval[i] = pwr;
0724         }
0725         b43_httab_write_bulk(dev, B43_HTTAB16(26 + c, 0), 64, regval);
0726     }
0727 }
0728 
0729 /**************************************************
0730  * Channel switching ops.
0731  **************************************************/
0732 
0733 static void b43_phy_ht_spur_avoid(struct b43_wldev *dev,
0734                   struct ieee80211_channel *new_channel)
0735 {
0736     struct bcma_device *core = dev->dev->bdev;
0737     int spuravoid = 0;
0738 
0739     /* Check for 13 and 14 is just a guess, we don't have enough logs. */
0740     if (new_channel->hw_value == 13 || new_channel->hw_value == 14)
0741         spuravoid = 1;
0742     bcma_core_pll_ctl(core, B43_BCMA_CLKCTLST_PHY_PLL_REQ, 0, false);
0743     bcma_pmu_spuravoid_pllupdate(&core->bus->drv_cc, spuravoid);
0744     bcma_core_pll_ctl(core,
0745               B43_BCMA_CLKCTLST_80211_PLL_REQ |
0746               B43_BCMA_CLKCTLST_PHY_PLL_REQ,
0747               B43_BCMA_CLKCTLST_80211_PLL_ST |
0748               B43_BCMA_CLKCTLST_PHY_PLL_ST, false);
0749 
0750     b43_mac_switch_freq(dev, spuravoid);
0751 
0752     b43_wireless_core_phy_pll_reset(dev);
0753 
0754     if (spuravoid)
0755         b43_phy_set(dev, B43_PHY_HT_BBCFG, B43_PHY_HT_BBCFG_RSTRX);
0756     else
0757         b43_phy_mask(dev, B43_PHY_HT_BBCFG,
0758                 ~B43_PHY_HT_BBCFG_RSTRX & 0xFFFF);
0759 
0760     b43_phy_ht_reset_cca(dev);
0761 }
0762 
0763 static void b43_phy_ht_channel_setup(struct b43_wldev *dev,
0764                 const struct b43_phy_ht_channeltab_e_phy *e,
0765                 struct ieee80211_channel *new_channel)
0766 {
0767     if (new_channel->band == NL80211_BAND_5GHZ) {
0768         /* Switch to 2 GHz for a moment to access B-PHY regs */
0769         b43_phy_mask(dev, B43_PHY_HT_BANDCTL, ~B43_PHY_HT_BANDCTL_5GHZ);
0770 
0771         b43_phy_ht_bphy_reset(dev, true);
0772 
0773         /* Switch to 5 GHz */
0774         b43_phy_set(dev, B43_PHY_HT_BANDCTL, B43_PHY_HT_BANDCTL_5GHZ);
0775     } else {
0776         /* Switch to 2 GHz */
0777         b43_phy_mask(dev, B43_PHY_HT_BANDCTL, ~B43_PHY_HT_BANDCTL_5GHZ);
0778 
0779         b43_phy_ht_bphy_reset(dev, false);
0780     }
0781 
0782     b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1);
0783     b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2);
0784     b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3);
0785     b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4);
0786     b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5);
0787     b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6);
0788 
0789     if (new_channel->hw_value == 14) {
0790         b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN, 0);
0791         b43_phy_set(dev, B43_PHY_HT_TEST, 0x0800);
0792     } else {
0793         b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN,
0794                       B43_PHY_HT_CLASS_CTL_OFDM_EN);
0795         if (new_channel->band == NL80211_BAND_2GHZ)
0796             b43_phy_mask(dev, B43_PHY_HT_TEST, ~0x840);
0797     }
0798 
0799     if (1) /* TODO: On N it's for early devices only, what about HT? */
0800         b43_phy_ht_tx_power_fix(dev);
0801 
0802     b43_phy_ht_spur_avoid(dev, new_channel);
0803 
0804     b43_phy_write(dev, 0x017e, 0x3830);
0805 }
0806 
0807 static int b43_phy_ht_set_channel(struct b43_wldev *dev,
0808                   struct ieee80211_channel *channel,
0809                   enum nl80211_channel_type channel_type)
0810 {
0811     struct b43_phy *phy = &dev->phy;
0812 
0813     const struct b43_phy_ht_channeltab_e_radio2059 *chent_r2059 = NULL;
0814 
0815     if (phy->radio_ver == 0x2059) {
0816         chent_r2059 = b43_phy_ht_get_channeltab_e_r2059(dev,
0817                             channel->center_freq);
0818         if (!chent_r2059)
0819             return -ESRCH;
0820     } else {
0821         return -ESRCH;
0822     }
0823 
0824     /* TODO: In case of N-PHY some bandwidth switching goes here */
0825 
0826     if (phy->radio_ver == 0x2059) {
0827         b43_radio_2059_channel_setup(dev, chent_r2059);
0828         b43_phy_ht_channel_setup(dev, &(chent_r2059->phy_regs),
0829                      channel);
0830     } else {
0831         return -ESRCH;
0832     }
0833 
0834     return 0;
0835 }
0836 
0837 /**************************************************
0838  * Basic PHY ops.
0839  **************************************************/
0840 
0841 static int b43_phy_ht_op_allocate(struct b43_wldev *dev)
0842 {
0843     struct b43_phy_ht *phy_ht;
0844 
0845     phy_ht = kzalloc(sizeof(*phy_ht), GFP_KERNEL);
0846     if (!phy_ht)
0847         return -ENOMEM;
0848     dev->phy.ht = phy_ht;
0849 
0850     return 0;
0851 }
0852 
0853 static void b43_phy_ht_op_prepare_structs(struct b43_wldev *dev)
0854 {
0855     struct b43_phy *phy = &dev->phy;
0856     struct b43_phy_ht *phy_ht = phy->ht;
0857     int i;
0858 
0859     memset(phy_ht, 0, sizeof(*phy_ht));
0860 
0861     phy_ht->tx_pwr_ctl = true;
0862     for (i = 0; i < 3; i++)
0863         phy_ht->tx_pwr_idx[i] = B43_PHY_HT_TXPCTL_CMD_C1_INIT + 1;
0864 
0865     for (i = 0; i < 3; i++)
0866         phy_ht->bb_mult_save[i] = -1;
0867 }
0868 
0869 static int b43_phy_ht_op_init(struct b43_wldev *dev)
0870 {
0871     struct b43_phy_ht *phy_ht = dev->phy.ht;
0872     u16 tmp;
0873     u16 clip_state[3];
0874     bool saved_tx_pwr_ctl;
0875 
0876     if (dev->dev->bus_type != B43_BUS_BCMA) {
0877         b43err(dev->wl, "HT-PHY is supported only on BCMA bus!\n");
0878         return -EOPNOTSUPP;
0879     }
0880 
0881     b43_phy_ht_tables_init(dev);
0882 
0883     b43_phy_mask(dev, 0x0be, ~0x2);
0884     b43_phy_set(dev, 0x23f, 0x7ff);
0885     b43_phy_set(dev, 0x240, 0x7ff);
0886     b43_phy_set(dev, 0x241, 0x7ff);
0887 
0888     b43_phy_ht_zero_extg(dev);
0889 
0890     b43_phy_mask(dev, B43_PHY_EXTG(0), ~0x3);
0891 
0892     b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0);
0893     b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0);
0894     b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0);
0895 
0896     b43_phy_write(dev, B43_PHY_EXTG(0x103), 0x20);
0897     b43_phy_write(dev, B43_PHY_EXTG(0x101), 0x20);
0898     b43_phy_write(dev, 0x20d, 0xb8);
0899     b43_phy_write(dev, B43_PHY_EXTG(0x14f), 0xc8);
0900     b43_phy_write(dev, 0x70, 0x50);
0901     b43_phy_write(dev, 0x1ff, 0x30);
0902 
0903     if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ)
0904         b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN, 0);
0905     else
0906         b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN,
0907                       B43_PHY_HT_CLASS_CTL_CCK_EN);
0908 
0909     b43_phy_set(dev, 0xb1, 0x91);
0910     b43_phy_write(dev, 0x32f, 0x0003);
0911     b43_phy_write(dev, 0x077, 0x0010);
0912     b43_phy_write(dev, 0x0b4, 0x0258);
0913     b43_phy_mask(dev, 0x17e, ~0x4000);
0914 
0915     b43_phy_write(dev, 0x0b9, 0x0072);
0916 
0917     b43_httab_write_few(dev, B43_HTTAB16(7, 0x14e), 2, 0x010f, 0x010f);
0918     b43_httab_write_few(dev, B43_HTTAB16(7, 0x15e), 2, 0x010f, 0x010f);
0919     b43_httab_write_few(dev, B43_HTTAB16(7, 0x16e), 2, 0x010f, 0x010f);
0920 
0921     b43_phy_ht_afe_unk1(dev);
0922 
0923     b43_httab_write_few(dev, B43_HTTAB16(7, 0x130), 9, 0x777, 0x111, 0x111,
0924                 0x777, 0x111, 0x111, 0x777, 0x111, 0x111);
0925 
0926     b43_httab_write(dev, B43_HTTAB16(7, 0x120), 0x0777);
0927     b43_httab_write(dev, B43_HTTAB16(7, 0x124), 0x0777);
0928 
0929     b43_httab_write(dev, B43_HTTAB16(8, 0x00), 0x02);
0930     b43_httab_write(dev, B43_HTTAB16(8, 0x10), 0x02);
0931     b43_httab_write(dev, B43_HTTAB16(8, 0x20), 0x02);
0932 
0933     b43_httab_write_few(dev, B43_HTTAB16(8, 0x08), 4,
0934                 0x8e, 0x96, 0x96, 0x96);
0935     b43_httab_write_few(dev, B43_HTTAB16(8, 0x18), 4,
0936                 0x8f, 0x9f, 0x9f, 0x9f);
0937     b43_httab_write_few(dev, B43_HTTAB16(8, 0x28), 4,
0938                 0x8f, 0x9f, 0x9f, 0x9f);
0939 
0940     b43_httab_write_few(dev, B43_HTTAB16(8, 0x0c), 4, 0x2, 0x2, 0x2, 0x2);
0941     b43_httab_write_few(dev, B43_HTTAB16(8, 0x1c), 4, 0x2, 0x2, 0x2, 0x2);
0942     b43_httab_write_few(dev, B43_HTTAB16(8, 0x2c), 4, 0x2, 0x2, 0x2, 0x2);
0943 
0944     b43_phy_maskset(dev, 0x0280, 0xff00, 0x3e);
0945     b43_phy_maskset(dev, 0x0283, 0xff00, 0x3e);
0946     b43_phy_maskset(dev, B43_PHY_OFDM(0x0141), 0xff00, 0x46);
0947     b43_phy_maskset(dev, 0x0283, 0xff00, 0x40);
0948 
0949     b43_httab_write_few(dev, B43_HTTAB16(00, 0x8), 4,
0950                 0x09, 0x0e, 0x13, 0x18);
0951     b43_httab_write_few(dev, B43_HTTAB16(01, 0x8), 4,
0952                 0x09, 0x0e, 0x13, 0x18);
0953     /* TODO: Did wl mean 2 instead of 40? */
0954     b43_httab_write_few(dev, B43_HTTAB16(40, 0x8), 4,
0955                 0x09, 0x0e, 0x13, 0x18);
0956 
0957     b43_phy_maskset(dev, B43_PHY_OFDM(0x24), 0x3f, 0xd);
0958     b43_phy_maskset(dev, B43_PHY_OFDM(0x64), 0x3f, 0xd);
0959     b43_phy_maskset(dev, B43_PHY_OFDM(0xa4), 0x3f, 0xd);
0960 
0961     b43_phy_set(dev, B43_PHY_EXTG(0x060), 0x1);
0962     b43_phy_set(dev, B43_PHY_EXTG(0x064), 0x1);
0963     b43_phy_set(dev, B43_PHY_EXTG(0x080), 0x1);
0964     b43_phy_set(dev, B43_PHY_EXTG(0x084), 0x1);
0965 
0966     /* Copy some tables entries */
0967     tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x144));
0968     b43_httab_write(dev, B43_HTTAB16(7, 0x14a), tmp);
0969     tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x154));
0970     b43_httab_write(dev, B43_HTTAB16(7, 0x15a), tmp);
0971     tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x164));
0972     b43_httab_write(dev, B43_HTTAB16(7, 0x16a), tmp);
0973 
0974     /* Reset CCA */
0975     b43_phy_force_clock(dev, true);
0976     tmp = b43_phy_read(dev, B43_PHY_HT_BBCFG);
0977     b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp | B43_PHY_HT_BBCFG_RSTCCA);
0978     b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp & ~B43_PHY_HT_BBCFG_RSTCCA);
0979     b43_phy_force_clock(dev, false);
0980 
0981     b43_mac_phy_clock_set(dev, true);
0982 
0983     b43_phy_ht_pa_override(dev, false);
0984     b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RX2TX);
0985     b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
0986     b43_phy_ht_pa_override(dev, true);
0987 
0988     /* TODO: Should we restore it? Or store it in global PHY info? */
0989     b43_phy_ht_classifier(dev, 0, 0);
0990     b43_phy_ht_read_clip_detection(dev, clip_state);
0991 
0992     if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ)
0993         b43_phy_ht_bphy_init(dev);
0994 
0995     b43_httab_write_bulk(dev, B43_HTTAB32(0x1a, 0xc0),
0996             B43_HTTAB_1A_C0_LATE_SIZE, b43_httab_0x1a_0xc0_late);
0997 
0998     saved_tx_pwr_ctl = phy_ht->tx_pwr_ctl;
0999     b43_phy_ht_tx_power_fix(dev);
1000     b43_phy_ht_tx_power_ctl(dev, false);
1001     b43_phy_ht_tx_power_ctl_idle_tssi(dev);
1002     b43_phy_ht_tx_power_ctl_setup(dev);
1003     b43_phy_ht_tssi_setup(dev);
1004     b43_phy_ht_tx_power_ctl(dev, saved_tx_pwr_ctl);
1005 
1006     return 0;
1007 }
1008 
1009 static void b43_phy_ht_op_free(struct b43_wldev *dev)
1010 {
1011     struct b43_phy *phy = &dev->phy;
1012     struct b43_phy_ht *phy_ht = phy->ht;
1013 
1014     kfree(phy_ht);
1015     phy->ht = NULL;
1016 }
1017 
1018 /* https://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
1019 static void b43_phy_ht_op_software_rfkill(struct b43_wldev *dev,
1020                     bool blocked)
1021 {
1022     if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
1023         b43err(dev->wl, "MAC not suspended\n");
1024 
1025     if (blocked) {
1026         b43_phy_mask(dev, B43_PHY_HT_RF_CTL_CMD,
1027                  ~B43_PHY_HT_RF_CTL_CMD_CHIP0_PU);
1028     } else {
1029         if (dev->phy.radio_ver == 0x2059)
1030             b43_radio_2059_init(dev);
1031         else
1032             B43_WARN_ON(1);
1033 
1034         b43_switch_channel(dev, dev->phy.channel);
1035     }
1036 }
1037 
1038 static void b43_phy_ht_op_switch_analog(struct b43_wldev *dev, bool on)
1039 {
1040     if (on) {
1041         b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00cd);
1042         b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x0000);
1043         b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00cd);
1044         b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x0000);
1045         b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00cd);
1046         b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x0000);
1047     } else {
1048         b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x07ff);
1049         b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00fd);
1050         b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x07ff);
1051         b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00fd);
1052         b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x07ff);
1053         b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00fd);
1054     }
1055 }
1056 
1057 static int b43_phy_ht_op_switch_channel(struct b43_wldev *dev,
1058                     unsigned int new_channel)
1059 {
1060     struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
1061     enum nl80211_channel_type channel_type =
1062         cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
1063 
1064     if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {
1065         if ((new_channel < 1) || (new_channel > 14))
1066             return -EINVAL;
1067     } else {
1068         return -EINVAL;
1069     }
1070 
1071     return b43_phy_ht_set_channel(dev, channel, channel_type);
1072 }
1073 
1074 static unsigned int b43_phy_ht_op_get_default_chan(struct b43_wldev *dev)
1075 {
1076     if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ)
1077         return 11;
1078     return 36;
1079 }
1080 
1081 /**************************************************
1082  * R/W ops.
1083  **************************************************/
1084 
1085 static void b43_phy_ht_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
1086                  u16 set)
1087 {
1088     b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
1089     b43_write16(dev, B43_MMIO_PHY_DATA,
1090             (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
1091 }
1092 
1093 static u16 b43_phy_ht_op_radio_read(struct b43_wldev *dev, u16 reg)
1094 {
1095     /* HT-PHY needs 0x200 for read access */
1096     reg |= 0x200;
1097 
1098     b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, reg);
1099     return b43_read16(dev, B43_MMIO_RADIO24_DATA);
1100 }
1101 
1102 static void b43_phy_ht_op_radio_write(struct b43_wldev *dev, u16 reg,
1103                       u16 value)
1104 {
1105     b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, reg);
1106     b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
1107 }
1108 
1109 static enum b43_txpwr_result
1110 b43_phy_ht_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi)
1111 {
1112     return B43_TXPWR_RES_DONE;
1113 }
1114 
1115 static void b43_phy_ht_op_adjust_txpower(struct b43_wldev *dev)
1116 {
1117 }
1118 
1119 /**************************************************
1120  * PHY ops struct.
1121  **************************************************/
1122 
1123 const struct b43_phy_operations b43_phyops_ht = {
1124     .allocate       = b43_phy_ht_op_allocate,
1125     .free           = b43_phy_ht_op_free,
1126     .prepare_structs    = b43_phy_ht_op_prepare_structs,
1127     .init           = b43_phy_ht_op_init,
1128     .phy_maskset        = b43_phy_ht_op_maskset,
1129     .radio_read     = b43_phy_ht_op_radio_read,
1130     .radio_write        = b43_phy_ht_op_radio_write,
1131     .software_rfkill    = b43_phy_ht_op_software_rfkill,
1132     .switch_analog      = b43_phy_ht_op_switch_analog,
1133     .switch_channel     = b43_phy_ht_op_switch_channel,
1134     .get_default_chan   = b43_phy_ht_op_get_default_chan,
1135     .recalc_txpower     = b43_phy_ht_op_recalc_txpower,
1136     .adjust_txpower     = b43_phy_ht_op_adjust_txpower,
1137 };
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