broadcom/b43/dma.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef B43_DMA_H_
0003 #define B43_DMA_H_
0004
0005 #include <linux/err.h>
0006
0007 #include "b43.h"
0008
0009
0010 /* DMA-Interrupt reasons. */
0011 #define B43_DMAIRQ_FATALMASK    ((1 << 10) | (1 << 11) | (1 << 12) \
0012                      | (1 << 14) | (1 << 15))
0013 #define B43_DMAIRQ_RDESC_UFLOW      (1 << 13)
0014 #define B43_DMAIRQ_RX_DONE      (1 << 16)
0015
0016 /*** 32-bit DMA Engine. ***/
0017
0018 /* 32-bit DMA controller registers. */
0019 #define B43_DMA32_TXCTL             0x00
0020 #define     B43_DMA32_TXENABLE          0x00000001
0021 #define     B43_DMA32_TXSUSPEND         0x00000002
0022 #define     B43_DMA32_TXLOOPBACK        0x00000004
0023 #define     B43_DMA32_TXFLUSH           0x00000010
0024 #define     B43_DMA32_TXPARITYDISABLE       0x00000800
0025 #define     B43_DMA32_TXADDREXT_MASK        0x00030000
0026 #define     B43_DMA32_TXADDREXT_SHIFT       16
0027 #define B43_DMA32_TXRING                0x04
0028 #define B43_DMA32_TXINDEX               0x08
0029 #define B43_DMA32_TXSTATUS              0x0C
0030 #define     B43_DMA32_TXDPTR            0x00000FFF
0031 #define     B43_DMA32_TXSTATE           0x0000F000
0032 #define         B43_DMA32_TXSTAT_DISABLED   0x00000000
0033 #define         B43_DMA32_TXSTAT_ACTIVE 0x00001000
0034 #define         B43_DMA32_TXSTAT_IDLEWAIT   0x00002000
0035 #define         B43_DMA32_TXSTAT_STOPPED    0x00003000
0036 #define         B43_DMA32_TXSTAT_SUSP   0x00004000
0037 #define     B43_DMA32_TXERROR           0x000F0000
0038 #define         B43_DMA32_TXERR_NOERR   0x00000000
0039 #define         B43_DMA32_TXERR_PROT    0x00010000
0040 #define         B43_DMA32_TXERR_UNDERRUN    0x00020000
0041 #define         B43_DMA32_TXERR_BUFREAD 0x00030000
0042 #define         B43_DMA32_TXERR_DESCREAD    0x00040000
0043 #define     B43_DMA32_TXACTIVE          0xFFF00000
0044 #define B43_DMA32_RXCTL             0x10
0045 #define     B43_DMA32_RXENABLE          0x00000001
0046 #define     B43_DMA32_RXFROFF_MASK      0x000000FE
0047 #define     B43_DMA32_RXFROFF_SHIFT     1
0048 #define     B43_DMA32_RXDIRECTFIFO      0x00000100
0049 #define     B43_DMA32_RXPARITYDISABLE       0x00000800
0050 #define     B43_DMA32_RXADDREXT_MASK        0x00030000
0051 #define     B43_DMA32_RXADDREXT_SHIFT       16
0052 #define B43_DMA32_RXRING                0x14
0053 #define B43_DMA32_RXINDEX               0x18
0054 #define B43_DMA32_RXSTATUS              0x1C
0055 #define     B43_DMA32_RXDPTR            0x00000FFF
0056 #define     B43_DMA32_RXSTATE           0x0000F000
0057 #define         B43_DMA32_RXSTAT_DISABLED   0x00000000
0058 #define         B43_DMA32_RXSTAT_ACTIVE 0x00001000
0059 #define         B43_DMA32_RXSTAT_IDLEWAIT   0x00002000
0060 #define         B43_DMA32_RXSTAT_STOPPED    0x00003000
0061 #define     B43_DMA32_RXERROR           0x000F0000
0062 #define         B43_DMA32_RXERR_NOERR   0x00000000
0063 #define         B43_DMA32_RXERR_PROT    0x00010000
0064 #define         B43_DMA32_RXERR_OVERFLOW    0x00020000
0065 #define         B43_DMA32_RXERR_BUFWRITE    0x00030000
0066 #define         B43_DMA32_RXERR_DESCREAD    0x00040000
0067 #define     B43_DMA32_RXACTIVE          0xFFF00000
0068
0069 /* 32-bit DMA descriptor. */
0070 struct b43_dmadesc32 {
0071     __le32 control;
0072     __le32 address;
0073 } __packed;
0074 #define B43_DMA32_DCTL_BYTECNT      0x00001FFF
0075 #define B43_DMA32_DCTL_ADDREXT_MASK     0x00030000
0076 #define B43_DMA32_DCTL_ADDREXT_SHIFT    16
0077 #define B43_DMA32_DCTL_DTABLEEND        0x10000000
0078 #define B43_DMA32_DCTL_IRQ          0x20000000
0079 #define B43_DMA32_DCTL_FRAMEEND     0x40000000
0080 #define B43_DMA32_DCTL_FRAMESTART       0x80000000
0081
0082 /*** 64-bit DMA Engine. ***/
0083
0084 /* 64-bit DMA controller registers. */
0085 #define B43_DMA64_TXCTL             0x00
0086 #define     B43_DMA64_TXENABLE          0x00000001
0087 #define     B43_DMA64_TXSUSPEND         0x00000002
0088 #define     B43_DMA64_TXLOOPBACK        0x00000004
0089 #define     B43_DMA64_TXFLUSH           0x00000010
0090 #define     B43_DMA64_TXPARITYDISABLE       0x00000800
0091 #define     B43_DMA64_TXADDREXT_MASK        0x00030000
0092 #define     B43_DMA64_TXADDREXT_SHIFT       16
0093 #define B43_DMA64_TXINDEX               0x04
0094 #define B43_DMA64_TXRINGLO              0x08
0095 #define B43_DMA64_TXRINGHI              0x0C
0096 #define B43_DMA64_TXSTATUS              0x10
0097 #define     B43_DMA64_TXSTATDPTR        0x00001FFF
0098 #define     B43_DMA64_TXSTAT            0xF0000000
0099 #define         B43_DMA64_TXSTAT_DISABLED   0x00000000
0100 #define         B43_DMA64_TXSTAT_ACTIVE 0x10000000
0101 #define         B43_DMA64_TXSTAT_IDLEWAIT   0x20000000
0102 #define         B43_DMA64_TXSTAT_STOPPED    0x30000000
0103 #define         B43_DMA64_TXSTAT_SUSP   0x40000000
0104 #define B43_DMA64_TXERROR               0x14
0105 #define     B43_DMA64_TXERRDPTR         0x0001FFFF
0106 #define     B43_DMA64_TXERR         0xF0000000
0107 #define         B43_DMA64_TXERR_NOERR   0x00000000
0108 #define         B43_DMA64_TXERR_PROT    0x10000000
0109 #define         B43_DMA64_TXERR_UNDERRUN    0x20000000
0110 #define         B43_DMA64_TXERR_TRANSFER    0x30000000
0111 #define         B43_DMA64_TXERR_DESCREAD    0x40000000
0112 #define         B43_DMA64_TXERR_CORE    0x50000000
0113 #define B43_DMA64_RXCTL             0x20
0114 #define     B43_DMA64_RXENABLE          0x00000001
0115 #define     B43_DMA64_RXFROFF_MASK      0x000000FE
0116 #define     B43_DMA64_RXFROFF_SHIFT     1
0117 #define     B43_DMA64_RXDIRECTFIFO      0x00000100
0118 #define     B43_DMA64_RXPARITYDISABLE       0x00000800
0119 #define     B43_DMA64_RXADDREXT_MASK        0x00030000
0120 #define     B43_DMA64_RXADDREXT_SHIFT       16
0121 #define B43_DMA64_RXINDEX               0x24
0122 #define B43_DMA64_RXRINGLO              0x28
0123 #define B43_DMA64_RXRINGHI              0x2C
0124 #define B43_DMA64_RXSTATUS              0x30
0125 #define     B43_DMA64_RXSTATDPTR        0x00001FFF
0126 #define     B43_DMA64_RXSTAT            0xF0000000
0127 #define         B43_DMA64_RXSTAT_DISABLED   0x00000000
0128 #define         B43_DMA64_RXSTAT_ACTIVE 0x10000000
0129 #define         B43_DMA64_RXSTAT_IDLEWAIT   0x20000000
0130 #define         B43_DMA64_RXSTAT_STOPPED    0x30000000
0131 #define         B43_DMA64_RXSTAT_SUSP   0x40000000
0132 #define B43_DMA64_RXERROR               0x34
0133 #define     B43_DMA64_RXERRDPTR         0x0001FFFF
0134 #define     B43_DMA64_RXERR         0xF0000000
0135 #define         B43_DMA64_RXERR_NOERR   0x00000000
0136 #define         B43_DMA64_RXERR_PROT    0x10000000
0137 #define         B43_DMA64_RXERR_UNDERRUN    0x20000000
0138 #define         B43_DMA64_RXERR_TRANSFER    0x30000000
0139 #define         B43_DMA64_RXERR_DESCREAD    0x40000000
0140 #define         B43_DMA64_RXERR_CORE    0x50000000
0141
0142 /* 64-bit DMA descriptor. */
0143 struct b43_dmadesc64 {
0144     __le32 control0;
0145     __le32 control1;
0146     __le32 address_low;
0147     __le32 address_high;
0148 } __packed;
0149 #define B43_DMA64_DCTL0_DTABLEEND       0x10000000
0150 #define B43_DMA64_DCTL0_IRQ         0x20000000
0151 #define B43_DMA64_DCTL0_FRAMEEND        0x40000000
0152 #define B43_DMA64_DCTL0_FRAMESTART      0x80000000
0153 #define B43_DMA64_DCTL1_BYTECNT     0x00001FFF
0154 #define B43_DMA64_DCTL1_ADDREXT_MASK    0x00030000
0155 #define B43_DMA64_DCTL1_ADDREXT_SHIFT   16
0156
0157 struct b43_dmadesc_generic {
0158     union {
0159         struct b43_dmadesc32 dma32;
0160         struct b43_dmadesc64 dma64;
0161     } __packed;
0162 } __packed;
0163
0164 /* Misc DMA constants */
0165 #define B43_DMA32_RINGMEMSIZE       4096
0166 #define B43_DMA64_RINGMEMSIZE       8192
0167 /* Offset of frame with actual data */
0168 #define B43_DMA0_RX_FW598_FO        38
0169 #define B43_DMA0_RX_FW351_FO        30
0170
0171 /* DMA engine tuning knobs */
0172 #define B43_TXRING_SLOTS        256
0173 #define B43_RXRING_SLOTS        256
0174 #define B43_DMA0_RX_FW598_BUFSIZE   (B43_DMA0_RX_FW598_FO + IEEE80211_MAX_FRAME_LEN)
0175 #define B43_DMA0_RX_FW351_BUFSIZE   (B43_DMA0_RX_FW351_FO + IEEE80211_MAX_FRAME_LEN)
0176
0177 /* Pointer poison */
0178 #define B43_DMA_PTR_POISON      ((void *)ERR_PTR(-ENOMEM))
0179 #define b43_dma_ptr_is_poisoned(ptr)    (unlikely((ptr) == B43_DMA_PTR_POISON))
0180
0181
0182 struct sk_buff;
0183 struct b43_private;
0184 struct b43_txstatus;
0185
0186 struct b43_dmadesc_meta {
0187     /* The kernel DMA-able buffer. */
0188     struct sk_buff *skb;
0189     /* DMA base bus-address of the descriptor buffer. */
0190     dma_addr_t dmaaddr;
0191     /* ieee80211 TX status. Only used once per 802.11 frag. */
0192     bool is_last_fragment;
0193 };
0194
0195 struct b43_dmaring;
0196
0197 /* Lowlevel DMA operations that differ between 32bit and 64bit DMA. */
0198 struct b43_dma_ops {
0199     struct b43_dmadesc_generic *(*idx2desc) (struct b43_dmaring * ring,
0200                          int slot,
0201                          struct b43_dmadesc_meta **
0202                          meta);
0203     void (*fill_descriptor) (struct b43_dmaring * ring,
0204                  struct b43_dmadesc_generic * desc,
0205                  dma_addr_t dmaaddr, u16 bufsize, int start,
0206                  int end, int irq);
0207     void (*poke_tx) (struct b43_dmaring * ring, int slot);
0208     void (*tx_suspend) (struct b43_dmaring * ring);
0209     void (*tx_resume) (struct b43_dmaring * ring);
0210     int (*get_current_rxslot) (struct b43_dmaring * ring);
0211     void (*set_current_rxslot) (struct b43_dmaring * ring, int slot);
0212 };
0213
0214 enum b43_dmatype {
0215     B43_DMA_30BIT   = 30,
0216     B43_DMA_32BIT   = 32,
0217     B43_DMA_64BIT   = 64,
0218 };
0219
0220 enum b43_addrtype {
0221     B43_DMA_ADDR_LOW,
0222     B43_DMA_ADDR_HIGH,
0223     B43_DMA_ADDR_EXT,
0224 };
0225
0226 struct b43_dmaring {
0227     /* Lowlevel DMA ops. */
0228     const struct b43_dma_ops *ops;
0229     /* Kernel virtual base address of the ring memory. */
0230     void *descbase;
0231     /* Meta data about all descriptors. */
0232     struct b43_dmadesc_meta *meta;
0233     /* Cache of TX headers for each TX frame.
0234      * This is to avoid an allocation on each TX.
0235      * This is NULL for an RX ring.
0236      */
0237     u8 *txhdr_cache;
0238     /* (Unadjusted) DMA base bus-address of the ring memory. */
0239     dma_addr_t dmabase;
0240     /* Number of descriptor slots in the ring. */
0241     int nr_slots;
0242     /* Number of used descriptor slots. */
0243     int used_slots;
0244     /* Currently used slot in the ring. */
0245     int current_slot;
0246     /* Frameoffset in octets. */
0247     u32 frameoffset;
0248     /* Descriptor buffer size. */
0249     u16 rx_buffersize;
0250     /* The MMIO base register of the DMA controller. */
0251     u16 mmio_base;
0252     /* DMA controller index number (0-5). */
0253     int index;
0254     /* Boolean. Is this a TX ring? */
0255     bool tx;
0256     /* The type of DMA engine used. */
0257     enum b43_dmatype type;
0258     /* Boolean. Is this ring stopped at ieee80211 level? */
0259     bool stopped;
0260     /* The QOS priority assigned to this ring. Only used for TX rings.
0261      * This is the mac80211 "queue" value. */
0262     u8 queue_prio;
0263     struct b43_wldev *dev;
0264 #ifdef CONFIG_B43_DEBUG
0265     /* Maximum number of used slots. */
0266     int max_used_slots;
0267     /* Last time we injected a ring overflow. */
0268     unsigned long last_injected_overflow;
0269     /* Statistics: Number of successfully transmitted packets */
0270     u64 nr_succeed_tx_packets;
0271     /* Statistics: Number of failed TX packets */
0272     u64 nr_failed_tx_packets;
0273     /* Statistics: Total number of TX plus all retries. */
0274     u64 nr_total_packet_tries;
0275 #endif /* CONFIG_B43_DEBUG */
0276 };
0277
0278 static inline u32 b43_dma_read(struct b43_dmaring *ring, u16 offset)
0279 {
0280     return b43_read32(ring->dev, ring->mmio_base + offset);
0281 }
0282
0283 static inline void b43_dma_write(struct b43_dmaring *ring, u16 offset, u32 value)
0284 {
0285     b43_write32(ring->dev, ring->mmio_base + offset, value);
0286 }
0287
0288 int b43_dma_init(struct b43_wldev *dev);
0289 void b43_dma_free(struct b43_wldev *dev);
0290
0291 void b43_dma_tx_suspend(struct b43_wldev *dev);
0292 void b43_dma_tx_resume(struct b43_wldev *dev);
0293
0294 int b43_dma_tx(struct b43_wldev *dev,
0295            struct sk_buff *skb);
0296 void b43_dma_handle_txstatus(struct b43_wldev *dev,
0297                  const struct b43_txstatus *status);
0298
0299 void b43_dma_handle_rx_overflow(struct b43_dmaring *ring);
0300
0301 void b43_dma_rx(struct b43_dmaring *ring);
0302
0303 void b43_dma_direct_fifo_rx(struct b43_wldev *dev,
0304                 unsigned int engine_index, bool enable);
0305
0306 #endif /* B43_DMA_H_ */