ath/wcn36xx/txrx.h

0001 /*
0002  * Copyright (c) 2013 Eugene Krasnikov <k.eugene.e@gmail.com>
0003  *
0004  * Permission to use, copy, modify, and/or distribute this software for any
0005  * purpose with or without fee is hereby granted, provided that the above
0006  * copyright notice and this permission notice appear in all copies.
0007  *
0008  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0009  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0010  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
0011  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0012  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
0013  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
0014  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0015  */
0016
0017 #ifndef _TXRX_H_
0018 #define _TXRX_H_
0019
0020 #include <linux/etherdevice.h>
0021 #include "wcn36xx.h"
0022
0023 /* TODO describe all properties */
0024 #define WCN36XX_802_11_HEADER_LEN   24
0025 #define WCN36XX_BMU_WQ_TX       25
0026 #define WCN36XX_TID         7
0027 /* broadcast wq ID */
0028 #define WCN36XX_TX_B_WQ_ID      0xA
0029 #define WCN36XX_TX_U_WQ_ID      0x9
0030 /* bd_rate */
0031 #define WCN36XX_BD_RATE_DATA 0
0032 #define WCN36XX_BD_RATE_MGMT 2
0033 #define WCN36XX_BD_RATE_CTRL 3
0034
0035 enum wcn36xx_txbd_ssn_type {
0036     WCN36XX_TXBD_SSN_FILL_HOST = 0,
0037     WCN36XX_TXBD_SSN_FILL_DPU_NON_QOS = 1,
0038     WCN36XX_TXBD_SSN_FILL_DPU_QOS = 2,
0039 };
0040
0041 struct wcn36xx_pdu {
0042     u32 dpu_fb:8;
0043     u32 adu_fb:8;
0044     u32 pdu_id:16;
0045
0046     /* 0x04*/
0047     u32 tail_pdu_idx:16;
0048     u32 head_pdu_idx:16;
0049
0050     /* 0x08*/
0051     u32 pdu_count:7;
0052     u32 mpdu_data_off:9;
0053     u32 mpdu_header_off:8;
0054     u32 mpdu_header_len:8;
0055
0056     /* 0x0c*/
0057     u32 reserved4:8;
0058     u32 tid:4;
0059     u32 bd_ssn:2;
0060     u32 reserved3:2;
0061     u32 mpdu_len:16;
0062 };
0063
0064 struct wcn36xx_rx_bd {
0065     u32 bdt:2;
0066     u32 ft:1;
0067     u32 dpu_ne:1;
0068     u32 rx_key_id:3;
0069     u32 ub:1;
0070     u32 rmf:1;
0071     u32 uma_bypass:1;
0072     u32 csr11:1;
0073     u32 reserved0:1;
0074     u32 scan_learn:1;
0075     u32 rx_ch:4;
0076     u32 rtsf:1;
0077     u32 bsf:1;
0078     u32 a2hf:1;
0079     u32 st_auf:1;
0080     u32 dpu_sign:3;
0081     u32 dpu_rf:8;
0082
0083     struct wcn36xx_pdu pdu;
0084
0085     /* 0x14*/
0086     u32 addr3:8;
0087     u32 addr2:8;
0088     u32 addr1:8;
0089     u32 dpu_desc_idx:8;
0090
0091     /* 0x18*/
0092     u32 rxp_flags:23;
0093     u32 rate_id:9;
0094
0095     u32 phy_stat0;
0096     u32 phy_stat1;
0097
0098     /* 0x24 */
0099     u32 rx_times;
0100
0101     u32 pmi_cmd[6];
0102
0103     /* 0x40 */
0104     u32 reserved7:4;
0105     u32 reorder_slot_id:6;
0106     u32 reorder_fwd_id:6;
0107     u32 reserved6:12;
0108     u32 reorder_code:4;
0109
0110     /* 0x44 */
0111     u32 exp_seq_num:12;
0112     u32 cur_seq_num:12;
0113     u32 rf_band:2;
0114     u32 fr_type_subtype:6;
0115
0116     /* 0x48 */
0117     u32 msdu_size:16;
0118     u32 sub_fr_id:4;
0119     u32 proc_order:4;
0120     u32 reserved9:4;
0121     u32 aef:1;
0122     u32 lsf:1;
0123     u32 esf:1;
0124     u32 asf:1;
0125 };
0126
0127 struct wcn36xx_tx_bd {
0128     u32 bdt:2;
0129     u32 ft:1;
0130     u32 dpu_ne:1;
0131     u32 fw_tx_comp:1;
0132     u32 tx_comp:1;
0133     u32 reserved1:1;
0134     u32 ub:1;
0135     u32 rmf:1;
0136     u32 reserved0:12;
0137     u32 dpu_sign:3;
0138     u32 dpu_rf:8;
0139
0140     struct wcn36xx_pdu pdu;
0141
0142     /* 0x14*/
0143     u32 reserved5:7;
0144     u32 queue_id:5;
0145     u32 bd_rate:2;
0146     u32 ack_policy:2;
0147     u32 sta_index:8;
0148     u32 dpu_desc_idx:8;
0149
0150     u32 tx_bd_sign;
0151     u32 reserved6;
0152     u32 dxe_start_time;
0153     u32 dxe_end_time;
0154
0155     /*u32   tcp_udp_start_off:10;
0156     u32 header_cks:16;
0157     u32 reserved7:6;*/
0158 };
0159
0160 struct wcn36xx_sta;
0161 struct wcn36xx;
0162
0163 int  wcn36xx_rx_skb(struct wcn36xx *wcn, struct sk_buff *skb);
0164 int wcn36xx_start_tx(struct wcn36xx *wcn,
0165              struct wcn36xx_sta *sta_priv,
0166              struct sk_buff *skb);
0167 void wcn36xx_process_tx_rate(struct ani_global_class_a_stats_info *stats, struct rate_info *info);
0168
0169 #endif  /* _TXRX_H_ */