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OSCL-LXR
 
 

     

0001 /*
0002  * Copyright (c) 2013 Eugene Krasnikov <k.eugene.e@gmail.com>
0003  *
0004  * Permission to use, copy, modify, and/or distribute this software for any
0005  * purpose with or without fee is hereby granted, provided that the above
0006  * copyright notice and this permission notice appear in all copies.
0007  *
0008  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0009  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0010  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
0011  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0012  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
0013  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
0014  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0015  */
0016 
0017 #ifndef _DXE_H_
0018 #define _DXE_H_
0019 
0020 #include "wcn36xx.h"
0021 
0022 /*
0023 TX_LOW  = DMA0
0024 TX_HIGH = DMA4
0025 RX_LOW  = DMA1
0026 RX_HIGH = DMA3
0027 H2H_TEST_RX_TX = DMA2
0028 */
0029 
0030 /* DXE registers */
0031 #define WCN36XX_DXE_MEM_REG         0
0032 
0033 #define WCN36XX_CCU_DXE_INT_SELECT_RIVA     0x310
0034 #define WCN36XX_CCU_DXE_INT_SELECT_PRONTO   0x10dc
0035 
0036 /* Descriptor valid */
0037 #define WCN36xx_DXE_CTRL_VLD        BIT(0)
0038 /* End of packet */
0039 #define WCN36xx_DXE_CTRL_EOP        BIT(3)
0040 /* BD handling bit */
0041 #define WCN36xx_DXE_CTRL_BDH        BIT(4)
0042 /* Source is a queue */
0043 #define WCN36xx_DXE_CTRL_SIQ        BIT(5)
0044 /* Destination is a queue */
0045 #define WCN36xx_DXE_CTRL_DIQ        BIT(6)
0046 /* Pointer address is a queue */
0047 #define WCN36xx_DXE_CTRL_PIQ        BIT(7)
0048 /* Release PDU when done */
0049 #define WCN36xx_DXE_CTRL_PDU_REL    BIT(8)
0050 /* STOP channel processing */
0051 #define WCN36xx_DXE_CTRL_STOP       BIT(16)
0052 /* INT on descriptor done */
0053 #define WCN36xx_DXE_CTRL_INT        BIT(17)
0054 /* Endian byte swap enable */
0055 #define WCN36xx_DXE_CTRL_SWAP       BIT(20)
0056 /* Master endianness */
0057 #define WCN36xx_DXE_CTRL_ENDIANNESS BIT(21)
0058 
0059 /* Transfer type */
0060 #define WCN36xx_DXE_CTRL_XTYPE_SHIFT 1
0061 #define WCN36xx_DXE_CTRL_XTYPE_MASK GENMASK(2, WCN36xx_DXE_CTRL_XTYPE_SHIFT)
0062 #define WCN36xx_DXE_CTRL_XTYPE_SET(x)   ((x) << WCN36xx_DXE_CTRL_XTYPE_SHIFT)
0063 
0064 /* BMU Threshold select */
0065 #define WCN36xx_DXE_CTRL_BTHLD_SEL_SHIFT 9
0066 #define WCN36xx_DXE_CTRL_BTHLD_SEL_MASK GENMASK(12, WCN36xx_DXE_CTRL_BTHLD_SEL_SHIFT)
0067 #define WCN36xx_DXE_CTRL_BTHLD_SEL_SET(x) ((x) << WCN36xx_DXE_CTRL_BTHLD_SEL_SHIFT)
0068 
0069 /* Priority */
0070 #define WCN36xx_DXE_CTRL_PRIO_SHIFT 13
0071 #define WCN36xx_DXE_CTRL_PRIO_MASK GENMASK(15, WCN36xx_DXE_CTRL_PRIO_SHIFT)
0072 #define WCN36xx_DXE_CTRL_PRIO_SET(x) ((x) << WCN36xx_DXE_CTRL_PRIO_SHIFT)
0073 
0074 /* BD Template index */
0075 #define WCN36xx_DXE_CTRL_BDT_IDX_SHIFT 18
0076 #define WCN36xx_DXE_CTRL_BDT_IDX_MASK GENMASK(19, WCN36xx_DXE_CTRL_BDT_IDX_SHIFT)
0077 #define WCN36xx_DXE_CTRL_BDT_IDX_SET(x) ((x) << WCN36xx_DXE_CTRL_BDT_IDX_SHIFT)
0078 
0079 /* Transfer types: */
0080 /* Host to host */
0081 #define WCN36xx_DXE_XTYPE_H2H (0)
0082 /* Host to BMU */
0083 #define WCN36xx_DXE_XTYPE_H2B (2)
0084 /* BMU to host */
0085 #define WCN36xx_DXE_XTYPE_B2H (3)
0086 
0087 #define WCN36XX_DXE_CTRL_TX_L   (WCN36xx_DXE_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \
0088     WCN36xx_DXE_CTRL_DIQ | WCN36xx_DXE_CTRL_BTHLD_SEL_SET(5) | \
0089     WCN36xx_DXE_CTRL_PRIO_SET(4) | WCN36xx_DXE_CTRL_INT | \
0090     WCN36xx_DXE_CTRL_SWAP | WCN36xx_DXE_CTRL_ENDIANNESS)
0091 
0092 #define WCN36XX_DXE_CTRL_TX_H    (WCN36xx_DXE_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \
0093     WCN36xx_DXE_CTRL_DIQ | WCN36xx_DXE_CTRL_BTHLD_SEL_SET(7) | \
0094     WCN36xx_DXE_CTRL_PRIO_SET(6) | WCN36xx_DXE_CTRL_INT | \
0095     WCN36xx_DXE_CTRL_SWAP | WCN36xx_DXE_CTRL_ENDIANNESS)
0096 
0097 #define WCN36XX_DXE_CTRL_RX_L   (WCN36xx_DXE_CTRL_VLD | \
0098     WCN36xx_DXE_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_B2H) | \
0099     WCN36xx_DXE_CTRL_EOP | WCN36xx_DXE_CTRL_SIQ | \
0100     WCN36xx_DXE_CTRL_PDU_REL | WCN36xx_DXE_CTRL_BTHLD_SEL_SET(6) | \
0101     WCN36xx_DXE_CTRL_PRIO_SET(5) | WCN36xx_DXE_CTRL_INT | \
0102     WCN36xx_DXE_CTRL_SWAP)
0103 
0104 #define WCN36XX_DXE_CTRL_RX_H   (WCN36xx_DXE_CTRL_VLD | \
0105     WCN36xx_DXE_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_B2H) | \
0106     WCN36xx_DXE_CTRL_EOP | WCN36xx_DXE_CTRL_SIQ | \
0107     WCN36xx_DXE_CTRL_PDU_REL |  WCN36xx_DXE_CTRL_BTHLD_SEL_SET(8) | \
0108     WCN36xx_DXE_CTRL_PRIO_SET(6) | WCN36xx_DXE_CTRL_INT | \
0109     WCN36xx_DXE_CTRL_SWAP)
0110 
0111 #define WCN36XX_DXE_CTRL_TX_H_BD    (WCN36xx_DXE_CTRL_VLD | \
0112     WCN36xx_DXE_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \
0113     WCN36xx_DXE_CTRL_DIQ | WCN36xx_DXE_CTRL_BTHLD_SEL_SET(7) | \
0114     WCN36xx_DXE_CTRL_PRIO_SET(6) | WCN36xx_DXE_CTRL_SWAP | \
0115     WCN36xx_DXE_CTRL_ENDIANNESS)
0116 
0117 #define WCN36XX_DXE_CTRL_TX_H_SKB   (WCN36xx_DXE_CTRL_VLD | \
0118     WCN36xx_DXE_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \
0119     WCN36xx_DXE_CTRL_EOP | WCN36xx_DXE_CTRL_DIQ | \
0120     WCN36xx_DXE_CTRL_BTHLD_SEL_SET(7) | WCN36xx_DXE_CTRL_PRIO_SET(6) | \
0121     WCN36xx_DXE_CTRL_INT | WCN36xx_DXE_CTRL_SWAP | \
0122     WCN36xx_DXE_CTRL_ENDIANNESS)
0123 
0124 #define WCN36XX_DXE_CTRL_TX_L_BD     (WCN36xx_DXE_CTRL_VLD | \
0125     WCN36xx_DXE_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \
0126     WCN36xx_DXE_CTRL_DIQ | WCN36xx_DXE_CTRL_BTHLD_SEL_SET(5) | \
0127     WCN36xx_DXE_CTRL_PRIO_SET(4) | WCN36xx_DXE_CTRL_SWAP | \
0128     WCN36xx_DXE_CTRL_ENDIANNESS)
0129 
0130 #define WCN36XX_DXE_CTRL_TX_L_SKB   (WCN36xx_DXE_CTRL_VLD | \
0131     WCN36xx_DXE_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \
0132     WCN36xx_DXE_CTRL_EOP | WCN36xx_DXE_CTRL_DIQ | \
0133     WCN36xx_DXE_CTRL_BTHLD_SEL_SET(5) | WCN36xx_DXE_CTRL_PRIO_SET(4) | \
0134     WCN36xx_DXE_CTRL_INT | WCN36xx_DXE_CTRL_SWAP | \
0135     WCN36xx_DXE_CTRL_ENDIANNESS)
0136 
0137 /* TODO This must calculated properly but not hardcoded */
0138 #define WCN36XX_DXE_WQ_TX_L         0x17
0139 #define WCN36XX_DXE_WQ_TX_H         0x17
0140 #define WCN36XX_DXE_WQ_RX_L         0xB
0141 #define WCN36XX_DXE_WQ_RX_H         0x4
0142 
0143 /* Channel enable or restart */
0144 #define WCN36xx_DXE_CH_CTRL_EN          BIT(0)
0145 /* End of packet bit */
0146 #define WCN36xx_DXE_CH_CTRL_EOP         BIT(3)
0147 /* BD Handling bit */
0148 #define WCN36xx_DXE_CH_CTRL_BDH         BIT(4)
0149 /* Source is queue */
0150 #define WCN36xx_DXE_CH_CTRL_SIQ         BIT(5)
0151 /* Destination is queue */
0152 #define WCN36xx_DXE_CH_CTRL_DIQ         BIT(6)
0153 /* Pointer descriptor is queue */
0154 #define WCN36xx_DXE_CH_CTRL_PIQ         BIT(7)
0155 /* Relase PDU when done */
0156 #define WCN36xx_DXE_CH_CTRL_PDU_REL     BIT(8)
0157 /* Stop channel processing */
0158 #define WCN36xx_DXE_CH_CTRL_STOP        BIT(16)
0159 /* Enable external descriptor interrupt */
0160 #define WCN36xx_DXE_CH_CTRL_INE_ED      BIT(17)
0161 /* Enable channel interrupt on errors */
0162 #define WCN36xx_DXE_CH_CTRL_INE_ERR     BIT(18)
0163 /* Enable Channel interrupt when done */
0164 #define WCN36xx_DXE_CH_CTRL_INE_DONE    BIT(19)
0165 /* External descriptor enable */
0166 #define WCN36xx_DXE_CH_CTRL_EDEN        BIT(20)
0167 /* Wait for valid bit */
0168 #define WCN36xx_DXE_CH_CTRL_EDVEN       BIT(21)
0169 /* Endianness is little endian*/
0170 #define WCN36xx_DXE_CH_CTRL_ENDIANNESS  BIT(26)
0171 /* Abort transfer */
0172 #define WCN36xx_DXE_CH_CTRL_ABORT       BIT(27)
0173 /* Long descriptor format */
0174 #define WCN36xx_DXE_CH_CTRL_DFMT        BIT(28)
0175 /* Endian byte swap enable */
0176 #define WCN36xx_DXE_CH_CTRL_SWAP        BIT(31)
0177 
0178 /* Transfer type */
0179 #define WCN36xx_DXE_CH_CTRL_XTYPE_SHIFT 1
0180 #define WCN36xx_DXE_CH_CTRL_XTYPE_MASK GENMASK(2, WCN36xx_DXE_CH_CTRL_XTYPE_SHIFT)
0181 #define WCN36xx_DXE_CH_CTRL_XTYPE_SET(x)    ((x) << WCN36xx_DXE_CH_CTRL_XTYPE_SHIFT)
0182 
0183 /* Channel BMU Threshold select */
0184 #define WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SHIFT 9
0185 #define WCN36xx_DXE_CH_CTRL_BTHLD_SEL_MASK GENMASK(12, WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SHIFT)
0186 #define WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SET(x) ((x) << WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SHIFT)
0187 
0188 /* Channel Priority */
0189 #define WCN36xx_DXE_CH_CTRL_PRIO_SHIFT 13
0190 #define WCN36xx_DXE_CH_CTRL_PRIO_MASK GENMASK(15, WCN36xx_DXE_CH_CTRL_PRIO_SHIFT)
0191 #define WCN36xx_DXE_CH_CTRL_PRIO_SET(x) ((x) << WCN36xx_DXE_CH_CTRL_PRIO_SHIFT)
0192 
0193 /* Counter select */
0194 #define WCN36xx_DXE_CH_CTRL_SEL_SHIFT 22
0195 #define WCN36xx_DXE_CH_CTRL_SEL_MASK GENMASK(25, WCN36xx_DXE_CH_CTRL_SEL_SHIFT)
0196 #define WCN36xx_DXE_CH_CTRL_SEL_SET(x)  ((x) << WCN36xx_DXE_CH_CTRL_SEL_SHIFT)
0197 
0198 /* Channel BD template index */
0199 #define WCN36xx_DXE_CH_CTRL_BDT_IDX_SHIFT 29
0200 #define WCN36xx_DXE_CH_CTRL_BDT_IDX_MASK GENMASK(30, WCN36xx_DXE_CH_CTRL_BDT_IDX_SHIFT)
0201 #define WCN36xx_DXE_CH_CTRL_BDT_IDX_SET(x)  ((x) << WCN36xx_DXE_CH_CTRL_BDT_IDX_SHIFT)
0202 
0203 /* DXE default control register values */
0204 #define WCN36XX_DXE_CH_DEFAULT_CTL_RX_L (WCN36xx_DXE_CH_CTRL_EN | \
0205         WCN36xx_DXE_CH_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_B2H) | \
0206         WCN36xx_DXE_CH_CTRL_EOP | WCN36xx_DXE_CH_CTRL_SIQ | \
0207         WCN36xx_DXE_CH_CTRL_PDU_REL | WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SET(6) | \
0208         WCN36xx_DXE_CH_CTRL_PRIO_SET(5) | WCN36xx_DXE_CH_CTRL_INE_ED | \
0209         WCN36xx_DXE_CH_CTRL_INE_ERR | WCN36xx_DXE_CH_CTRL_INE_DONE | \
0210         WCN36xx_DXE_CH_CTRL_EDEN | WCN36xx_DXE_CH_CTRL_EDVEN | \
0211         WCN36xx_DXE_CH_CTRL_SEL_SET(1) | WCN36xx_DXE_CH_CTRL_ENDIANNESS | \
0212         WCN36xx_DXE_CH_CTRL_SWAP)
0213 
0214 #define WCN36XX_DXE_CH_DEFAULT_CTL_RX_H (WCN36xx_DXE_CH_CTRL_EN | \
0215         WCN36xx_DXE_CH_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_B2H) | \
0216         WCN36xx_DXE_CH_CTRL_EOP | WCN36xx_DXE_CH_CTRL_SIQ | \
0217         WCN36xx_DXE_CH_CTRL_PDU_REL | WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SET(8) | \
0218         WCN36xx_DXE_CH_CTRL_PRIO_SET(6) | WCN36xx_DXE_CH_CTRL_INE_ED | \
0219         WCN36xx_DXE_CH_CTRL_INE_ERR | WCN36xx_DXE_CH_CTRL_INE_DONE | \
0220         WCN36xx_DXE_CH_CTRL_EDEN | WCN36xx_DXE_CH_CTRL_EDVEN | \
0221         WCN36xx_DXE_CH_CTRL_SEL_SET(3) | WCN36xx_DXE_CH_CTRL_ENDIANNESS | \
0222         WCN36xx_DXE_CH_CTRL_SWAP)
0223 
0224 #define WCN36XX_DXE_CH_DEFAULT_CTL_TX_H (WCN36xx_DXE_CH_CTRL_EN | \
0225         WCN36xx_DXE_CH_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \
0226         WCN36xx_DXE_CH_CTRL_EOP | WCN36xx_DXE_CH_CTRL_DIQ | \
0227         WCN36xx_DXE_CH_CTRL_PDU_REL | WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SET(7) | \
0228         WCN36xx_DXE_CH_CTRL_PRIO_SET(6) | WCN36xx_DXE_CH_CTRL_INE_ED | \
0229         WCN36xx_DXE_CH_CTRL_INE_ERR | WCN36xx_DXE_CH_CTRL_INE_DONE | \
0230         WCN36xx_DXE_CH_CTRL_EDEN | WCN36xx_DXE_CH_CTRL_EDVEN | \
0231         WCN36xx_DXE_CH_CTRL_SEL_SET(4) | WCN36xx_DXE_CH_CTRL_ENDIANNESS | \
0232         WCN36xx_DXE_CH_CTRL_SWAP)
0233 
0234 #define WCN36XX_DXE_CH_DEFAULT_CTL_TX_L (WCN36xx_DXE_CH_CTRL_EN | \
0235         WCN36xx_DXE_CH_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \
0236         WCN36xx_DXE_CH_CTRL_EOP | WCN36xx_DXE_CH_CTRL_DIQ | \
0237         WCN36xx_DXE_CH_CTRL_PDU_REL | WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SET(5) | \
0238         WCN36xx_DXE_CH_CTRL_PRIO_SET(4) | WCN36xx_DXE_CH_CTRL_INE_ED | \
0239         WCN36xx_DXE_CH_CTRL_INE_ERR | WCN36xx_DXE_CH_CTRL_INE_DONE | \
0240         WCN36xx_DXE_CH_CTRL_EDEN | WCN36xx_DXE_CH_CTRL_EDVEN | \
0241         WCN36xx_DXE_CH_CTRL_SEL_SET(0) | WCN36xx_DXE_CH_CTRL_ENDIANNESS | \
0242         WCN36xx_DXE_CH_CTRL_SWAP)
0243 
0244 /* Common DXE registers */
0245 #define WCN36XX_DXE_MEM_CSR         (WCN36XX_DXE_MEM_REG + 0x00)
0246 #define WCN36XX_DXE_REG_CSR_RESET       (WCN36XX_DXE_MEM_REG + 0x00)
0247 #define WCN36XX_DXE_ENCH_ADDR           (WCN36XX_DXE_MEM_REG + 0x04)
0248 #define WCN36XX_DXE_REG_CH_EN           (WCN36XX_DXE_MEM_REG + 0x08)
0249 #define WCN36XX_DXE_REG_CH_DONE         (WCN36XX_DXE_MEM_REG + 0x0C)
0250 #define WCN36XX_DXE_REG_CH_ERR          (WCN36XX_DXE_MEM_REG + 0x10)
0251 #define WCN36XX_DXE_INT_MASK_REG        (WCN36XX_DXE_MEM_REG + 0x18)
0252 #define WCN36XX_DXE_INT_SRC_RAW_REG     (WCN36XX_DXE_MEM_REG + 0x20)
0253     /* #define WCN36XX_DXE_INT_CH6_MASK 0x00000040 */
0254     /* #define WCN36XX_DXE_INT_CH5_MASK 0x00000020 */
0255     #define WCN36XX_DXE_INT_CH4_MASK    0x00000010
0256     #define WCN36XX_DXE_INT_CH3_MASK    0x00000008
0257     /* #define WCN36XX_DXE_INT_CH2_MASK 0x00000004 */
0258     #define WCN36XX_DXE_INT_CH1_MASK    0x00000002
0259     #define WCN36XX_DXE_INT_CH0_MASK    0x00000001
0260 #define WCN36XX_DXE_0_INT_CLR           (WCN36XX_DXE_MEM_REG + 0x30)
0261 #define WCN36XX_DXE_0_INT_ED_CLR        (WCN36XX_DXE_MEM_REG + 0x34)
0262 #define WCN36XX_DXE_0_INT_DONE_CLR      (WCN36XX_DXE_MEM_REG + 0x38)
0263 #define WCN36XX_DXE_0_INT_ERR_CLR       (WCN36XX_DXE_MEM_REG + 0x3C)
0264 
0265 #define WCN36XX_CH_STAT_INT_DONE_MASK   0x00008000
0266 #define WCN36XX_CH_STAT_INT_ERR_MASK    0x00004000
0267 #define WCN36XX_CH_STAT_INT_ED_MASK     0x00002000
0268 
0269 #define WCN36XX_DXE_0_CH0_STATUS        (WCN36XX_DXE_MEM_REG + 0x404)
0270 #define WCN36XX_DXE_0_CH1_STATUS        (WCN36XX_DXE_MEM_REG + 0x444)
0271 #define WCN36XX_DXE_0_CH2_STATUS        (WCN36XX_DXE_MEM_REG + 0x484)
0272 #define WCN36XX_DXE_0_CH3_STATUS        (WCN36XX_DXE_MEM_REG + 0x4C4)
0273 #define WCN36XX_DXE_0_CH4_STATUS        (WCN36XX_DXE_MEM_REG + 0x504)
0274 
0275 #define WCN36XX_DXE_REG_RESET           0x5c89
0276 
0277 /* Temporary BMU Workqueue 4 */
0278 #define WCN36XX_DXE_BMU_WQ_RX_LOW       0xB
0279 #define WCN36XX_DXE_BMU_WQ_RX_HIGH      0x4
0280 /* DMA channel offset */
0281 #define WCN36XX_DXE_TX_LOW_OFFSET       0x400
0282 #define WCN36XX_DXE_TX_HIGH_OFFSET      0x500
0283 #define WCN36XX_DXE_RX_LOW_OFFSET       0x440
0284 #define WCN36XX_DXE_RX_HIGH_OFFSET      0x4C0
0285 
0286 /* Address of the next DXE descriptor */
0287 #define WCN36XX_DXE_CH_NEXT_DESC_ADDR       0x001C
0288 #define WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_L  (WCN36XX_DXE_MEM_REG + \
0289                          WCN36XX_DXE_TX_LOW_OFFSET + \
0290                          WCN36XX_DXE_CH_NEXT_DESC_ADDR)
0291 #define WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_H  (WCN36XX_DXE_MEM_REG + \
0292                          WCN36XX_DXE_TX_HIGH_OFFSET + \
0293                          WCN36XX_DXE_CH_NEXT_DESC_ADDR)
0294 #define WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_L  (WCN36XX_DXE_MEM_REG + \
0295                          WCN36XX_DXE_RX_LOW_OFFSET + \
0296                          WCN36XX_DXE_CH_NEXT_DESC_ADDR)
0297 #define WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_H  (WCN36XX_DXE_MEM_REG + \
0298                          WCN36XX_DXE_RX_HIGH_OFFSET + \
0299                          WCN36XX_DXE_CH_NEXT_DESC_ADDR)
0300 
0301 /* DXE Descriptor source address */
0302 #define WCN36XX_DXE_CH_SRC_ADDR         0x000C
0303 #define WCN36XX_DXE_CH_SRC_ADDR_RX_L        (WCN36XX_DXE_MEM_REG + \
0304                          WCN36XX_DXE_RX_LOW_OFFSET + \
0305                          WCN36XX_DXE_CH_SRC_ADDR)
0306 #define WCN36XX_DXE_CH_SRC_ADDR_RX_H        (WCN36XX_DXE_MEM_REG + \
0307                          WCN36XX_DXE_RX_HIGH_OFFSET + \
0308                          WCN36XX_DXE_CH_SRC_ADDR)
0309 
0310 /* DXE Descriptor address destination address */
0311 #define WCN36XX_DXE_CH_DEST_ADDR        0x0014
0312 #define WCN36XX_DXE_CH_DEST_ADDR_TX_L       (WCN36XX_DXE_MEM_REG + \
0313                          WCN36XX_DXE_TX_LOW_OFFSET + \
0314                          WCN36XX_DXE_CH_DEST_ADDR)
0315 #define WCN36XX_DXE_CH_DEST_ADDR_TX_H       (WCN36XX_DXE_MEM_REG + \
0316                          WCN36XX_DXE_TX_HIGH_OFFSET + \
0317                          WCN36XX_DXE_CH_DEST_ADDR)
0318 #define WCN36XX_DXE_CH_DEST_ADDR_RX_L       (WCN36XX_DXE_MEM_REG + \
0319                          WCN36XX_DXE_RX_LOW_OFFSET + \
0320                          WCN36XX_DXE_CH_DEST_ADDR)
0321 #define WCN36XX_DXE_CH_DEST_ADDR_RX_H       (WCN36XX_DXE_MEM_REG + \
0322                          WCN36XX_DXE_RX_HIGH_OFFSET + \
0323                          WCN36XX_DXE_CH_DEST_ADDR)
0324 
0325 /* Interrupt status */
0326 #define WCN36XX_DXE_CH_STATUS_REG_ADDR      0x0004
0327 #define WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_L (WCN36XX_DXE_MEM_REG + \
0328                          WCN36XX_DXE_TX_LOW_OFFSET + \
0329                          WCN36XX_DXE_CH_STATUS_REG_ADDR)
0330 #define WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_H (WCN36XX_DXE_MEM_REG + \
0331                          WCN36XX_DXE_TX_HIGH_OFFSET + \
0332                          WCN36XX_DXE_CH_STATUS_REG_ADDR)
0333 #define WCN36XX_DXE_CH_STATUS_REG_ADDR_RX_L (WCN36XX_DXE_MEM_REG + \
0334                          WCN36XX_DXE_RX_LOW_OFFSET + \
0335                          WCN36XX_DXE_CH_STATUS_REG_ADDR)
0336 #define WCN36XX_DXE_CH_STATUS_REG_ADDR_RX_H (WCN36XX_DXE_MEM_REG + \
0337                          WCN36XX_DXE_RX_HIGH_OFFSET + \
0338                          WCN36XX_DXE_CH_STATUS_REG_ADDR)
0339 
0340 
0341 /* DXE default control register */
0342 #define WCN36XX_DXE_REG_CTL_RX_L        (WCN36XX_DXE_MEM_REG + \
0343                          WCN36XX_DXE_RX_LOW_OFFSET)
0344 #define WCN36XX_DXE_REG_CTL_RX_H        (WCN36XX_DXE_MEM_REG + \
0345                          WCN36XX_DXE_RX_HIGH_OFFSET)
0346 #define WCN36XX_DXE_REG_CTL_TX_H        (WCN36XX_DXE_MEM_REG + \
0347                          WCN36XX_DXE_TX_HIGH_OFFSET)
0348 #define WCN36XX_DXE_REG_CTL_TX_L        (WCN36XX_DXE_MEM_REG + \
0349                          WCN36XX_DXE_TX_LOW_OFFSET)
0350 
0351 #define WCN36XX_SMSM_WLAN_TX_ENABLE     0x00000400
0352 #define WCN36XX_SMSM_WLAN_TX_RINGS_EMPTY    0x00000200
0353 
0354 
0355 /* Interrupt control channel mask */
0356 #define WCN36XX_INT_MASK_CHAN_TX_L      0x00000001
0357 #define WCN36XX_INT_MASK_CHAN_RX_L      0x00000002
0358 #define WCN36XX_INT_MASK_CHAN_RX_H      0x00000008
0359 #define WCN36XX_INT_MASK_CHAN_TX_H      0x00000010
0360 
0361 #define WCN36XX_BD_CHUNK_SIZE           128
0362 
0363 #define WCN36XX_PKT_SIZE            0xF20
0364 enum wcn36xx_dxe_ch_type {
0365     WCN36XX_DXE_CH_TX_L,
0366     WCN36XX_DXE_CH_TX_H,
0367     WCN36XX_DXE_CH_RX_L,
0368     WCN36XX_DXE_CH_RX_H
0369 };
0370 
0371 /* amount of descriptors per channel */
0372 enum wcn36xx_dxe_ch_desc_num {
0373     WCN36XX_DXE_CH_DESC_NUMB_TX_L       = 128,
0374     WCN36XX_DXE_CH_DESC_NUMB_TX_H       = 10,
0375     WCN36XX_DXE_CH_DESC_NUMB_RX_L       = 512,
0376     WCN36XX_DXE_CH_DESC_NUMB_RX_H       = 40
0377 };
0378 
0379 /**
0380  * struct wcn36xx_dxe_desc - describes descriptor of one DXE buffer
0381  *
0382  * @ctrl: is a union that consists of following bits:
0383  * union {
0384  *  u32 valid       :1; //0 = DMA stop, 1 = DMA continue with this
0385  *                  //descriptor
0386  *  u32 transfer_type   :2; //0 = Host to Host space
0387  *  u32 eop     :1; //End of Packet
0388  *  u32 bd_handling :1; //if transferType = Host to BMU, then 0
0389  *                  // means first 128 bytes contain BD, and 1
0390  *                  // means create new empty BD
0391  *  u32 siq     :1; // SIQ
0392  *  u32 diq     :1; // DIQ
0393  *  u32 pdu_rel     :1; //0 = don't release BD and PDUs when done,
0394  *                  // 1 = release them
0395  *  u32 bthld_sel   :4; //BMU Threshold Select
0396  *  u32 prio        :3; //Specifies the priority level to use for
0397  *                  // the transfer
0398  *  u32 stop_channel    :1; //1 = DMA stops processing further, channel
0399  *                  //requires re-enabling after this
0400  *  u32 intr        :1; //Interrupt on Descriptor Done
0401  *  u32 rsvd        :1; //reserved
0402  *  u32 size        :14;//14 bits used - ignored for BMU transfers,
0403  *                  //only used for host to host transfers?
0404  * } ctrl;
0405  */
0406 struct wcn36xx_dxe_desc {
0407     u32 ctrl;
0408     u32 fr_len;
0409 
0410     u32 src_addr_l;
0411     u32 dst_addr_l;
0412     u32 phy_next_l;
0413     u32 src_addr_h;
0414     u32 dst_addr_h;
0415     u32 phy_next_h;
0416 } __packed;
0417 
0418 /* DXE Control block */
0419 struct wcn36xx_dxe_ctl {
0420     struct wcn36xx_dxe_ctl  *next;
0421     struct wcn36xx_dxe_desc *desc;
0422     unsigned int        desc_phy_addr;
0423     int         ctl_blk_order;
0424     struct sk_buff      *skb;
0425     void            *bd_cpu_addr;
0426     dma_addr_t      bd_phy_addr;
0427 };
0428 
0429 struct wcn36xx_dxe_ch {
0430     spinlock_t          lock;   /* protects head/tail ptrs */
0431     enum wcn36xx_dxe_ch_type    ch_type;
0432     void                *cpu_addr;
0433     dma_addr_t          dma_addr;
0434     enum wcn36xx_dxe_ch_desc_num    desc_num;
0435     /* DXE control block ring */
0436     struct wcn36xx_dxe_ctl      *head_blk_ctl;
0437     struct wcn36xx_dxe_ctl      *tail_blk_ctl;
0438 
0439     /* DXE channel specific configs */
0440     u32             dxe_wq;
0441     u32             ctrl_bd;
0442     u32             ctrl_skb;
0443     u32             reg_ctrl;
0444     u32             def_ctrl;
0445 };
0446 
0447 /* Memory Pool for BD headers */
0448 struct wcn36xx_dxe_mem_pool {
0449     int     chunk_size;
0450     void        *virt_addr;
0451     dma_addr_t  phy_addr;
0452 };
0453 
0454 struct wcn36xx_tx_bd;
0455 struct wcn36xx_vif;
0456 int wcn36xx_dxe_allocate_mem_pools(struct wcn36xx *wcn);
0457 void wcn36xx_dxe_free_mem_pools(struct wcn36xx *wcn);
0458 void wcn36xx_dxe_rx_frame(struct wcn36xx *wcn);
0459 int wcn36xx_dxe_alloc_ctl_blks(struct wcn36xx *wcn);
0460 void wcn36xx_dxe_free_ctl_blks(struct wcn36xx *wcn);
0461 int wcn36xx_dxe_init(struct wcn36xx *wcn);
0462 void wcn36xx_dxe_deinit(struct wcn36xx *wcn);
0463 int wcn36xx_dxe_init_channels(struct wcn36xx *wcn);
0464 int wcn36xx_dxe_tx_frame(struct wcn36xx *wcn,
0465              struct wcn36xx_vif *vif_priv,
0466              struct wcn36xx_tx_bd *bd,
0467              struct sk_buff *skb,
0468              bool is_low);
0469 int wcn36xx_dxe_tx_flush(struct wcn36xx *wcn);
0470 void wcn36xx_dxe_tx_ack_ind(struct wcn36xx *wcn, u32 status);
0471 #endif  /* _DXE_H_ */
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