ath/carl9170/eeprom.h

0001 /*
0002  * Shared Atheros AR9170 Header
0003  *
0004  * EEPROM layout
0005  *
0006  * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
0007  *
0008  * This program is free software; you can redistribute it and/or modify
0009  * it under the terms of the GNU General Public License as published by
0010  * the Free Software Foundation; either version 2 of the License, or
0011  * (at your option) any later version.
0012  *
0013  * This program is distributed in the hope that it will be useful,
0014  * but WITHOUT ANY WARRANTY; without even the implied warranty of
0015  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
0016  * GNU General Public License for more details.
0017  *
0018  * You should have received a copy of the GNU General Public License
0019  * along with this program; see the file COPYING.  If not, see
0020  * http://www.gnu.org/licenses/.
0021  *
0022  * This file incorporates work covered by the following copyright and
0023  * permission notice:
0024  *    Copyright (c) 2007-2008 Atheros Communications, Inc.
0025  *
0026  *    Permission to use, copy, modify, and/or distribute this software for any
0027  *    purpose with or without fee is hereby granted, provided that the above
0028  *    copyright notice and this permission notice appear in all copies.
0029  *
0030  *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0031  *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0032  *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0033  *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0034  *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0035  *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0036  *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0037  */
0038 #ifndef __CARL9170_SHARED_EEPROM_H
0039 #define __CARL9170_SHARED_EEPROM_H
0040
0041 #define AR9170_EEPROM_START     0x1600
0042
0043 #define AR5416_MAX_CHAINS       2
0044 #define AR5416_MODAL_SPURS      5
0045
0046 struct ar9170_eeprom_modal {
0047     __le32  antCtrlChain[AR5416_MAX_CHAINS];
0048     __le32  antCtrlCommon;
0049     s8  antennaGainCh[AR5416_MAX_CHAINS];
0050     u8  switchSettling;
0051     u8  txRxAttenCh[AR5416_MAX_CHAINS];
0052     u8  rxTxMarginCh[AR5416_MAX_CHAINS];
0053     s8  adcDesiredSize;
0054     s8  pgaDesiredSize;
0055     u8  xlnaGainCh[AR5416_MAX_CHAINS];
0056     u8  txEndToXpaOff;
0057     u8  txEndToRxOn;
0058     u8  txFrameToXpaOn;
0059     u8  thresh62;
0060     s8  noiseFloorThreshCh[AR5416_MAX_CHAINS];
0061     u8  xpdGain;
0062     u8  xpd;
0063     s8  iqCalICh[AR5416_MAX_CHAINS];
0064     s8  iqCalQCh[AR5416_MAX_CHAINS];
0065     u8  pdGainOverlap;
0066     u8  ob;
0067     u8  db;
0068     u8  xpaBiasLvl;
0069     u8  pwrDecreaseFor2Chain;
0070     u8  pwrDecreaseFor3Chain;
0071     u8  txFrameToDataStart;
0072     u8  txFrameToPaOn;
0073     u8  ht40PowerIncForPdadc;
0074     u8  bswAtten[AR5416_MAX_CHAINS];
0075     u8  bswMargin[AR5416_MAX_CHAINS];
0076     u8  swSettleHt40;
0077     u8  reserved[22];
0078     struct spur_channel {
0079         __le16 spurChan;
0080         u8  spurRangeLow;
0081         u8  spurRangeHigh;
0082     } __packed spur_channels[AR5416_MODAL_SPURS];
0083 } __packed;
0084
0085 #define AR5416_NUM_PD_GAINS     4
0086 #define AR5416_PD_GAIN_ICEPTS       5
0087
0088 struct ar9170_calibration_data_per_freq {
0089     u8  pwr_pdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
0090     u8  vpd_pdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
0091 } __packed;
0092
0093 #define AR5416_NUM_5G_CAL_PIERS     8
0094 #define AR5416_NUM_2G_CAL_PIERS     4
0095
0096 #define AR5416_NUM_5G_TARGET_PWRS   8
0097 #define AR5416_NUM_2G_CCK_TARGET_PWRS   3
0098 #define AR5416_NUM_2G_OFDM_TARGET_PWRS  4
0099 #define AR5416_MAX_NUM_TGT_PWRS     8
0100
0101 struct ar9170_calibration_target_power_legacy {
0102     u8  freq;
0103     u8  power[4];
0104 } __packed;
0105
0106 struct ar9170_calibration_target_power_ht {
0107     u8  freq;
0108     u8  power[8];
0109 } __packed;
0110
0111 #define AR5416_NUM_CTLS         24
0112
0113 struct ar9170_calctl_edges {
0114     u8  channel;
0115 #define AR9170_CALCTL_EDGE_FLAGS    0xC0
0116     u8  power_flags;
0117 } __packed;
0118
0119 #define AR5416_NUM_BAND_EDGES       8
0120
0121 struct ar9170_calctl_data {
0122     struct ar9170_calctl_edges
0123         control_edges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
0124 } __packed;
0125
0126 struct ar9170_eeprom {
0127     __le16  length;
0128     __le16  checksum;
0129     __le16  version;
0130     u8  operating_flags;
0131 #define AR9170_OPFLAG_5GHZ      1
0132 #define AR9170_OPFLAG_2GHZ      2
0133     u8  misc;
0134     __le16  reg_domain[2];
0135     u8  mac_address[6];
0136     u8  rx_mask;
0137     u8  tx_mask;
0138     __le16  rf_silent;
0139     __le16  bluetooth_options;
0140     __le16  device_capabilities;
0141     __le32  build_number;
0142     u8  deviceType;
0143     u8  reserved[33];
0144
0145     u8  customer_data[64];
0146
0147     struct ar9170_eeprom_modal
0148         modal_header[2];
0149
0150     u8  cal_freq_pier_5G[AR5416_NUM_5G_CAL_PIERS];
0151     u8  cal_freq_pier_2G[AR5416_NUM_2G_CAL_PIERS];
0152
0153     struct ar9170_calibration_data_per_freq
0154         cal_pier_data_5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS],
0155         cal_pier_data_2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
0156
0157     /* power calibration data */
0158     struct ar9170_calibration_target_power_legacy
0159         cal_tgt_pwr_5G[AR5416_NUM_5G_TARGET_PWRS];
0160     struct ar9170_calibration_target_power_ht
0161         cal_tgt_pwr_5G_ht20[AR5416_NUM_5G_TARGET_PWRS],
0162         cal_tgt_pwr_5G_ht40[AR5416_NUM_5G_TARGET_PWRS];
0163
0164     struct ar9170_calibration_target_power_legacy
0165         cal_tgt_pwr_2G_cck[AR5416_NUM_2G_CCK_TARGET_PWRS],
0166         cal_tgt_pwr_2G_ofdm[AR5416_NUM_2G_OFDM_TARGET_PWRS];
0167     struct ar9170_calibration_target_power_ht
0168         cal_tgt_pwr_2G_ht20[AR5416_NUM_2G_OFDM_TARGET_PWRS],
0169         cal_tgt_pwr_2G_ht40[AR5416_NUM_2G_OFDM_TARGET_PWRS];
0170
0171     /* conformance testing limits */
0172     u8  ctl_index[AR5416_NUM_CTLS];
0173     struct ar9170_calctl_data
0174         ctl_data[AR5416_NUM_CTLS];
0175
0176     u8  pad;
0177     __le16  subsystem_id;
0178 } __packed;
0179
0180 #define AR9170_LED_MODE_POWER_ON        0x0001
0181 #define AR9170_LED_MODE_RESERVED        0x0002
0182 #define AR9170_LED_MODE_DISABLE_STATE       0x0004
0183 #define AR9170_LED_MODE_OFF_IN_PSM      0x0008
0184
0185 /* AR9170_LED_MODE BIT is set */
0186 #define AR9170_LED_MODE_FREQUENCY_S     4
0187 #define AR9170_LED_MODE_FREQUENCY       0x0030
0188 #define AR9170_LED_MODE_FREQUENCY_1HZ       0x0000
0189 #define AR9170_LED_MODE_FREQUENCY_0_5HZ     0x0010
0190 #define AR9170_LED_MODE_FREQUENCY_0_25HZ    0x0020
0191 #define AR9170_LED_MODE_FREQUENCY_0_125HZ   0x0030
0192
0193 /* AR9170_LED_MODE BIT is not set */
0194 #define AR9170_LED_MODE_CONN_STATE_S        4
0195 #define AR9170_LED_MODE_CONN_STATE      0x0030
0196 #define AR9170_LED_MODE_CONN_STATE_FORCE_OFF    0x0000
0197 #define AR9170_LED_MODE_CONN_STATE_FORCE_ON 0x0010
0198 /* Idle off / Active on */
0199 #define AR9170_LED_MODE_CONN_STATE_IOFF_AON 0x0020
0200 /* Idle on / Active off */
0201 #define AR9170_LED_MODE_CONN_STATE_ION_AOFF 0x0010
0202
0203 #define AR9170_LED_MODE_MODE            0x0040
0204 #define AR9170_LED_MODE_RESERVED2       0x0080
0205
0206 #define AR9170_LED_MODE_TON_SCAN_S      8
0207 #define AR9170_LED_MODE_TON_SCAN        0x0f00
0208
0209 #define AR9170_LED_MODE_TOFF_SCAN_S     12
0210 #define AR9170_LED_MODE_TOFF_SCAN       0xf000
0211
0212 struct ar9170_led_mode {
0213     __le16 led;
0214 };
0215
0216 #endif /* __CARL9170_SHARED_EEPROM_H */