ath/ath9k/main.c

0001 /*
0002  * Copyright (c) 2008-2011 Atheros Communications Inc.
0003  *
0004  * Permission to use, copy, modify, and/or distribute this software for any
0005  * purpose with or without fee is hereby granted, provided that the above
0006  * copyright notice and this permission notice appear in all copies.
0007  *
0008  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0009  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0010  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0011  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0012  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0013  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0014  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0015  */
0016
0017 #include <linux/nl80211.h>
0018 #include <linux/delay.h>
0019 #include "ath9k.h"
0020 #include "btcoex.h"
0021
0022 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
0023             u32 queues, bool drop);
0024
0025 u8 ath9k_parse_mpdudensity(u8 mpdudensity)
0026 {
0027     /*
0028      * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
0029      *   0 for no restriction
0030      *   1 for 1/4 us
0031      *   2 for 1/2 us
0032      *   3 for 1 us
0033      *   4 for 2 us
0034      *   5 for 4 us
0035      *   6 for 8 us
0036      *   7 for 16 us
0037      */
0038     switch (mpdudensity) {
0039     case 0:
0040         return 0;
0041     case 1:
0042     case 2:
0043     case 3:
0044         /* Our lower layer calculations limit our precision to
0045            1 microsecond */
0046         return 1;
0047     case 4:
0048         return 2;
0049     case 5:
0050         return 4;
0051     case 6:
0052         return 8;
0053     case 7:
0054         return 16;
0055     default:
0056         return 0;
0057     }
0058 }
0059
0060 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq,
0061                      bool sw_pending)
0062 {
0063     bool pending = false;
0064
0065     spin_lock_bh(&txq->axq_lock);
0066
0067     if (txq->axq_depth) {
0068         pending = true;
0069         goto out;
0070     }
0071
0072     if (!sw_pending)
0073         goto out;
0074
0075     if (txq->mac80211_qnum >= 0) {
0076         struct ath_acq *acq;
0077
0078         acq = &sc->cur_chan->acq[txq->mac80211_qnum];
0079         if (!list_empty(&acq->acq_new) || !list_empty(&acq->acq_old))
0080             pending = true;
0081     }
0082 out:
0083     spin_unlock_bh(&txq->axq_lock);
0084     return pending;
0085 }
0086
0087 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
0088 {
0089     unsigned long flags;
0090     bool ret;
0091
0092     spin_lock_irqsave(&sc->sc_pm_lock, flags);
0093     ret = ath9k_hw_setpower(sc->sc_ah, mode);
0094     spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
0095
0096     return ret;
0097 }
0098
0099 void ath_ps_full_sleep(struct timer_list *t)
0100 {
0101     struct ath_softc *sc = from_timer(sc, t, sleep_timer);
0102     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
0103     unsigned long flags;
0104     bool reset;
0105
0106     spin_lock_irqsave(&common->cc_lock, flags);
0107     ath_hw_cycle_counters_update(common);
0108     spin_unlock_irqrestore(&common->cc_lock, flags);
0109
0110     ath9k_hw_setrxabort(sc->sc_ah, 1);
0111     ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
0112
0113     ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
0114 }
0115
0116 void ath9k_ps_wakeup(struct ath_softc *sc)
0117 {
0118     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
0119     unsigned long flags;
0120     enum ath9k_power_mode power_mode;
0121
0122     spin_lock_irqsave(&sc->sc_pm_lock, flags);
0123     if (++sc->ps_usecount != 1)
0124         goto unlock;
0125
0126     del_timer_sync(&sc->sleep_timer);
0127     power_mode = sc->sc_ah->power_mode;
0128     ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
0129
0130     /*
0131      * While the hardware is asleep, the cycle counters contain no
0132      * useful data. Better clear them now so that they don't mess up
0133      * survey data results.
0134      */
0135     if (power_mode != ATH9K_PM_AWAKE) {
0136         spin_lock(&common->cc_lock);
0137         ath_hw_cycle_counters_update(common);
0138         memset(&common->cc_survey, 0, sizeof(common->cc_survey));
0139         memset(&common->cc_ani, 0, sizeof(common->cc_ani));
0140         spin_unlock(&common->cc_lock);
0141     }
0142
0143  unlock:
0144     spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
0145 }
0146
0147 void ath9k_ps_restore(struct ath_softc *sc)
0148 {
0149     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
0150     enum ath9k_power_mode mode;
0151     unsigned long flags;
0152
0153     spin_lock_irqsave(&sc->sc_pm_lock, flags);
0154     if (--sc->ps_usecount != 0)
0155         goto unlock;
0156
0157     if (sc->ps_idle) {
0158         mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
0159         goto unlock;
0160     }
0161
0162     if (sc->ps_enabled &&
0163            !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
0164                      PS_WAIT_FOR_CAB |
0165                      PS_WAIT_FOR_PSPOLL_DATA |
0166                      PS_WAIT_FOR_TX_ACK |
0167                      PS_WAIT_FOR_ANI))) {
0168         mode = ATH9K_PM_NETWORK_SLEEP;
0169         if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
0170             ath9k_btcoex_stop_gen_timer(sc);
0171     } else {
0172         goto unlock;
0173     }
0174
0175     spin_lock(&common->cc_lock);
0176     ath_hw_cycle_counters_update(common);
0177     spin_unlock(&common->cc_lock);
0178
0179     ath9k_hw_setpower(sc->sc_ah, mode);
0180
0181  unlock:
0182     spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
0183 }
0184
0185 static void __ath_cancel_work(struct ath_softc *sc)
0186 {
0187     cancel_work_sync(&sc->paprd_work);
0188     cancel_delayed_work_sync(&sc->hw_check_work);
0189     cancel_delayed_work_sync(&sc->hw_pll_work);
0190
0191 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
0192     if (ath9k_hw_mci_is_enabled(sc->sc_ah))
0193         cancel_work_sync(&sc->mci_work);
0194 #endif
0195 }
0196
0197 void ath_cancel_work(struct ath_softc *sc)
0198 {
0199     __ath_cancel_work(sc);
0200     cancel_work_sync(&sc->hw_reset_work);
0201 }
0202
0203 void ath_restart_work(struct ath_softc *sc)
0204 {
0205     ieee80211_queue_delayed_work(sc->hw, &sc->hw_check_work,
0206                      ATH_HW_CHECK_POLL_INT);
0207
0208     if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
0209         ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
0210                      msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
0211
0212     ath_start_ani(sc);
0213 }
0214
0215 static bool ath_prepare_reset(struct ath_softc *sc)
0216 {
0217     struct ath_hw *ah = sc->sc_ah;
0218     bool ret = true;
0219
0220     ieee80211_stop_queues(sc->hw);
0221     ath_stop_ani(sc);
0222     ath9k_hw_disable_interrupts(ah);
0223
0224     if (AR_SREV_9300_20_OR_LATER(ah)) {
0225         ret &= ath_stoprecv(sc);
0226         ret &= ath_drain_all_txq(sc);
0227     } else {
0228         ret &= ath_drain_all_txq(sc);
0229         ret &= ath_stoprecv(sc);
0230     }
0231
0232     return ret;
0233 }
0234
0235 static bool ath_complete_reset(struct ath_softc *sc, bool start)
0236 {
0237     struct ath_hw *ah = sc->sc_ah;
0238     struct ath_common *common = ath9k_hw_common(ah);
0239     unsigned long flags;
0240
0241     ath9k_calculate_summary_state(sc, sc->cur_chan);
0242     ath_startrecv(sc);
0243     ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
0244                    sc->cur_chan->txpower,
0245                    &sc->cur_chan->cur_txpower);
0246     clear_bit(ATH_OP_HW_RESET, &common->op_flags);
0247
0248     if (!sc->cur_chan->offchannel && start) {
0249         /* restore per chanctx TSF timer */
0250         if (sc->cur_chan->tsf_val) {
0251             u32 offset;
0252
0253             offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
0254                              NULL);
0255             ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
0256         }
0257
0258
0259         if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
0260             goto work;
0261
0262         if (ah->opmode == NL80211_IFTYPE_STATION &&
0263             test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
0264             spin_lock_irqsave(&sc->sc_pm_lock, flags);
0265             sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
0266             spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
0267         } else {
0268             ath9k_set_beacon(sc);
0269         }
0270     work:
0271         ath_restart_work(sc);
0272         ath_txq_schedule_all(sc);
0273     }
0274
0275     sc->gtt_cnt = 0;
0276
0277     ath9k_hw_set_interrupts(ah);
0278     ath9k_hw_enable_interrupts(ah);
0279     ieee80211_wake_queues(sc->hw);
0280     ath9k_p2p_ps_timer(sc);
0281
0282     return true;
0283 }
0284
0285 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
0286 {
0287     struct ath_hw *ah = sc->sc_ah;
0288     struct ath_common *common = ath9k_hw_common(ah);
0289     struct ath9k_hw_cal_data *caldata = NULL;
0290     bool fastcc = true;
0291     int r;
0292
0293     __ath_cancel_work(sc);
0294
0295     disable_irq(sc->irq);
0296     tasklet_disable(&sc->intr_tq);
0297     tasklet_disable(&sc->bcon_tasklet);
0298     spin_lock_bh(&sc->sc_pcu_lock);
0299
0300     if (!sc->cur_chan->offchannel) {
0301         fastcc = false;
0302         caldata = &sc->cur_chan->caldata;
0303     }
0304
0305     if (!hchan) {
0306         fastcc = false;
0307         hchan = ah->curchan;
0308     }
0309
0310     if (!hchan) {
0311         fastcc = false;
0312         hchan = ath9k_cmn_get_channel(sc->hw, ah, &sc->cur_chan->chandef);
0313     }
0314
0315     if (!ath_prepare_reset(sc))
0316         fastcc = false;
0317
0318     if (ath9k_is_chanctx_enabled())
0319         fastcc = false;
0320
0321     spin_lock_bh(&sc->chan_lock);
0322     sc->cur_chandef = sc->cur_chan->chandef;
0323     spin_unlock_bh(&sc->chan_lock);
0324
0325     ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
0326         hchan->channel, IS_CHAN_HT40(hchan), fastcc);
0327
0328     r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
0329     if (r) {
0330         ath_err(common,
0331             "Unable to reset channel, reset status %d\n", r);
0332
0333         ath9k_hw_enable_interrupts(ah);
0334         ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
0335
0336         goto out;
0337     }
0338
0339     if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
0340         sc->cur_chan->offchannel)
0341         ath9k_mci_set_txpower(sc, true, false);
0342
0343     if (!ath_complete_reset(sc, true))
0344         r = -EIO;
0345
0346 out:
0347     enable_irq(sc->irq);
0348     spin_unlock_bh(&sc->sc_pcu_lock);
0349     tasklet_enable(&sc->bcon_tasklet);
0350     tasklet_enable(&sc->intr_tq);
0351
0352     return r;
0353 }
0354
0355 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
0356                 struct ieee80211_vif *vif)
0357 {
0358     struct ath_node *an;
0359     an = (struct ath_node *)sta->drv_priv;
0360
0361     an->sc = sc;
0362     an->sta = sta;
0363     an->vif = vif;
0364     memset(&an->key_idx, 0, sizeof(an->key_idx));
0365
0366     ath_tx_node_init(sc, an);
0367
0368     ath_dynack_node_init(sc->sc_ah, an);
0369 }
0370
0371 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
0372 {
0373     struct ath_node *an = (struct ath_node *)sta->drv_priv;
0374     ath_tx_node_cleanup(sc, an);
0375
0376     ath_dynack_node_deinit(sc->sc_ah, an);
0377 }
0378
0379 void ath9k_tasklet(struct tasklet_struct *t)
0380 {
0381     struct ath_softc *sc = from_tasklet(sc, t, intr_tq);
0382     struct ath_hw *ah = sc->sc_ah;
0383     struct ath_common *common = ath9k_hw_common(ah);
0384     enum ath_reset_type type;
0385     unsigned long flags;
0386     u32 status;
0387     u32 rxmask;
0388
0389     spin_lock_irqsave(&sc->intr_lock, flags);
0390     status = sc->intrstatus;
0391     sc->intrstatus = 0;
0392     spin_unlock_irqrestore(&sc->intr_lock, flags);
0393
0394     ath9k_ps_wakeup(sc);
0395     spin_lock(&sc->sc_pcu_lock);
0396
0397     if (status & ATH9K_INT_FATAL) {
0398         type = RESET_TYPE_FATAL_INT;
0399         ath9k_queue_reset(sc, type);
0400         ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
0401         goto out;
0402     }
0403
0404     if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
0405         (status & ATH9K_INT_BB_WATCHDOG)) {
0406         spin_lock_irqsave(&common->cc_lock, flags);
0407         ath_hw_cycle_counters_update(common);
0408         ar9003_hw_bb_watchdog_dbg_info(ah);
0409         spin_unlock_irqrestore(&common->cc_lock, flags);
0410
0411         if (ar9003_hw_bb_watchdog_check(ah)) {
0412             type = RESET_TYPE_BB_WATCHDOG;
0413             ath9k_queue_reset(sc, type);
0414
0415             ath_dbg(common, RESET,
0416                 "BB_WATCHDOG: Skipping interrupts\n");
0417             goto out;
0418         }
0419     }
0420
0421     if (status & ATH9K_INT_GTT) {
0422         sc->gtt_cnt++;
0423
0424         if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
0425             type = RESET_TYPE_TX_GTT;
0426             ath9k_queue_reset(sc, type);
0427             ath_dbg(common, RESET,
0428                 "GTT: Skipping interrupts\n");
0429             goto out;
0430         }
0431     }
0432
0433     spin_lock_irqsave(&sc->sc_pm_lock, flags);
0434     if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
0435         /*
0436          * TSF sync does not look correct; remain awake to sync with
0437          * the next Beacon.
0438          */
0439         ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
0440         sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
0441     }
0442     spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
0443
0444     if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
0445         rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
0446               ATH9K_INT_RXORN);
0447     else
0448         rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
0449
0450     if (status & rxmask) {
0451         /* Check for high priority Rx first */
0452         if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
0453             (status & ATH9K_INT_RXHP))
0454             ath_rx_tasklet(sc, 0, true);
0455
0456         ath_rx_tasklet(sc, 0, false);
0457     }
0458
0459     if (status & ATH9K_INT_TX) {
0460         if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
0461             /*
0462              * For EDMA chips, TX completion is enabled for the
0463              * beacon queue, so if a beacon has been transmitted
0464              * successfully after a GTT interrupt, the GTT counter
0465              * gets reset to zero here.
0466              */
0467             sc->gtt_cnt = 0;
0468
0469             ath_tx_edma_tasklet(sc);
0470         } else {
0471             ath_tx_tasklet(sc);
0472         }
0473
0474         wake_up(&sc->tx_wait);
0475     }
0476
0477     if (status & ATH9K_INT_GENTIMER)
0478         ath_gen_timer_isr(sc->sc_ah);
0479
0480     ath9k_btcoex_handle_interrupt(sc, status);
0481
0482     /* re-enable hardware interrupt */
0483     ath9k_hw_resume_interrupts(ah);
0484 out:
0485     spin_unlock(&sc->sc_pcu_lock);
0486     ath9k_ps_restore(sc);
0487 }
0488
0489 irqreturn_t ath_isr(int irq, void *dev)
0490 {
0491 #define SCHED_INTR (                \
0492         ATH9K_INT_FATAL |       \
0493         ATH9K_INT_BB_WATCHDOG |     \
0494         ATH9K_INT_RXORN |       \
0495         ATH9K_INT_RXEOL |       \
0496         ATH9K_INT_RX |          \
0497         ATH9K_INT_RXLP |        \
0498         ATH9K_INT_RXHP |        \
0499         ATH9K_INT_TX |          \
0500         ATH9K_INT_BMISS |       \
0501         ATH9K_INT_CST |         \
0502         ATH9K_INT_GTT |         \
0503         ATH9K_INT_TSFOOR |      \
0504         ATH9K_INT_GENTIMER |        \
0505         ATH9K_INT_MCI)
0506
0507     struct ath_softc *sc = dev;
0508     struct ath_hw *ah = sc->sc_ah;
0509     struct ath_common *common = ath9k_hw_common(ah);
0510     enum ath9k_int status;
0511     u32 sync_cause = 0;
0512     bool sched = false;
0513
0514     /*
0515      * The hardware is not ready/present, don't
0516      * touch anything. Note this can happen early
0517      * on if the IRQ is shared.
0518      */
0519     if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
0520         return IRQ_NONE;
0521
0522     /* shared irq, not for us */
0523     if (!ath9k_hw_intrpend(ah))
0524         return IRQ_NONE;
0525
0526     /*
0527      * Figure out the reason(s) for the interrupt.  Note
0528      * that the hal returns a pseudo-ISR that may include
0529      * bits we haven't explicitly enabled so we mask the
0530      * value to insure we only process bits we requested.
0531      */
0532     ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
0533     ath9k_debug_sync_cause(sc, sync_cause);
0534     status &= ah->imask;    /* discard unasked-for bits */
0535
0536     if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) {
0537         ath9k_hw_kill_interrupts(sc->sc_ah);
0538         return IRQ_HANDLED;
0539     }
0540
0541     /*
0542      * If there are no status bits set, then this interrupt was not
0543      * for me (should have been caught above).
0544      */
0545     if (!status)
0546         return IRQ_NONE;
0547
0548     /* Cache the status */
0549     spin_lock(&sc->intr_lock);
0550     sc->intrstatus |= status;
0551     spin_unlock(&sc->intr_lock);
0552
0553     if (status & SCHED_INTR)
0554         sched = true;
0555
0556     /*
0557      * If a FATAL interrupt is received, we have to reset the chip
0558      * immediately.
0559      */
0560     if (status & ATH9K_INT_FATAL)
0561         goto chip_reset;
0562
0563     if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
0564         (status & ATH9K_INT_BB_WATCHDOG))
0565         goto chip_reset;
0566
0567     if (status & ATH9K_INT_SWBA)
0568         tasklet_schedule(&sc->bcon_tasklet);
0569
0570     if (status & ATH9K_INT_TXURN)
0571         ath9k_hw_updatetxtriglevel(ah, true);
0572
0573     if (status & ATH9K_INT_RXEOL) {
0574         ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
0575         ath9k_hw_set_interrupts(ah);
0576     }
0577
0578     if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
0579         if (status & ATH9K_INT_TIM_TIMER) {
0580             if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
0581                 goto chip_reset;
0582             /* Clear RxAbort bit so that we can
0583              * receive frames */
0584             ath9k_setpower(sc, ATH9K_PM_AWAKE);
0585             spin_lock(&sc->sc_pm_lock);
0586             ath9k_hw_setrxabort(sc->sc_ah, 0);
0587             sc->ps_flags |= PS_WAIT_FOR_BEACON;
0588             spin_unlock(&sc->sc_pm_lock);
0589         }
0590
0591 chip_reset:
0592
0593     ath_debug_stat_interrupt(sc, status);
0594
0595     if (sched) {
0596         /* turn off every interrupt */
0597         ath9k_hw_kill_interrupts(ah);
0598         tasklet_schedule(&sc->intr_tq);
0599     }
0600
0601     return IRQ_HANDLED;
0602
0603 #undef SCHED_INTR
0604 }
0605
0606 /*
0607  * This function is called when a HW reset cannot be deferred
0608  * and has to be immediate.
0609  */
0610 int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan)
0611 {
0612     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
0613     int r;
0614
0615     ath9k_hw_kill_interrupts(sc->sc_ah);
0616     set_bit(ATH_OP_HW_RESET, &common->op_flags);
0617
0618     ath9k_ps_wakeup(sc);
0619     r = ath_reset_internal(sc, hchan);
0620     ath9k_ps_restore(sc);
0621
0622     return r;
0623 }
0624
0625 /*
0626  * When a HW reset can be deferred, it is added to the
0627  * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before
0628  * queueing.
0629  */
0630 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
0631 {
0632     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
0633 #ifdef CONFIG_ATH9K_DEBUGFS
0634     RESET_STAT_INC(sc, type);
0635 #endif
0636     ath9k_hw_kill_interrupts(sc->sc_ah);
0637     set_bit(ATH_OP_HW_RESET, &common->op_flags);
0638     ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
0639 }
0640
0641 void ath_reset_work(struct work_struct *work)
0642 {
0643     struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
0644
0645     ath9k_ps_wakeup(sc);
0646     ath_reset_internal(sc, NULL);
0647     ath9k_ps_restore(sc);
0648 }
0649
0650 /**********************/
0651 /* mac80211 callbacks */
0652 /**********************/
0653
0654 static int ath9k_start(struct ieee80211_hw *hw)
0655 {
0656     struct ath_softc *sc = hw->priv;
0657     struct ath_hw *ah = sc->sc_ah;
0658     struct ath_common *common = ath9k_hw_common(ah);
0659     struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
0660     struct ath_chanctx *ctx = sc->cur_chan;
0661     struct ath9k_channel *init_channel;
0662     int r;
0663
0664     ath_dbg(common, CONFIG,
0665         "Starting driver with initial channel: %d MHz\n",
0666         curchan->center_freq);
0667
0668     ath9k_ps_wakeup(sc);
0669     mutex_lock(&sc->mutex);
0670
0671     init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
0672     sc->cur_chandef = hw->conf.chandef;
0673
0674     /* Reset SERDES registers */
0675     ath9k_hw_configpcipowersave(ah, false);
0676
0677     /*
0678      * The basic interface to setting the hardware in a good
0679      * state is ``reset''.  On return the hardware is known to
0680      * be powered up and with interrupts disabled.  This must
0681      * be followed by initialization of the appropriate bits
0682      * and then setup of the interrupt mask.
0683      */
0684     spin_lock_bh(&sc->sc_pcu_lock);
0685
0686     atomic_set(&ah->intr_ref_cnt, -1);
0687
0688     r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
0689     if (r) {
0690         ath_err(common,
0691             "Unable to reset hardware; reset status %d (freq %u MHz)\n",
0692             r, curchan->center_freq);
0693         ah->reset_power_on = false;
0694     }
0695
0696     /* Setup our intr mask. */
0697     ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
0698             ATH9K_INT_RXORN | ATH9K_INT_FATAL |
0699             ATH9K_INT_GLOBAL;
0700
0701     if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
0702         ah->imask |= ATH9K_INT_RXHP |
0703                  ATH9K_INT_RXLP;
0704     else
0705         ah->imask |= ATH9K_INT_RX;
0706
0707     if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
0708         ah->imask |= ATH9K_INT_BB_WATCHDOG;
0709
0710     /*
0711      * Enable GTT interrupts only for AR9003/AR9004 chips
0712      * for now.
0713      */
0714     if (AR_SREV_9300_20_OR_LATER(ah))
0715         ah->imask |= ATH9K_INT_GTT;
0716
0717     if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
0718         ah->imask |= ATH9K_INT_CST;
0719
0720     ath_mci_enable(sc);
0721
0722     clear_bit(ATH_OP_INVALID, &common->op_flags);
0723     sc->sc_ah->is_monitoring = false;
0724
0725     if (!ath_complete_reset(sc, false))
0726         ah->reset_power_on = false;
0727
0728     if (ah->led_pin >= 0) {
0729         ath9k_hw_set_gpio(ah, ah->led_pin,
0730                   (ah->config.led_active_high) ? 1 : 0);
0731         ath9k_hw_gpio_request_out(ah, ah->led_pin, NULL,
0732                       AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
0733     }
0734
0735     /*
0736      * Reset key cache to sane defaults (all entries cleared) instead of
0737      * semi-random values after suspend/resume.
0738      */
0739     ath9k_cmn_init_crypto(sc->sc_ah);
0740
0741     ath9k_hw_reset_tsf(ah);
0742
0743     spin_unlock_bh(&sc->sc_pcu_lock);
0744
0745     ath9k_rng_start(sc);
0746
0747     mutex_unlock(&sc->mutex);
0748
0749     ath9k_ps_restore(sc);
0750
0751     return 0;
0752 }
0753
0754 static void ath9k_tx(struct ieee80211_hw *hw,
0755              struct ieee80211_tx_control *control,
0756              struct sk_buff *skb)
0757 {
0758     struct ath_softc *sc = hw->priv;
0759     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
0760     struct ath_tx_control txctl;
0761     struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
0762     unsigned long flags;
0763
0764     if (sc->ps_enabled) {
0765         /*
0766          * mac80211 does not set PM field for normal data frames, so we
0767          * need to update that based on the current PS mode.
0768          */
0769         if (ieee80211_is_data(hdr->frame_control) &&
0770             !ieee80211_is_nullfunc(hdr->frame_control) &&
0771             !ieee80211_has_pm(hdr->frame_control)) {
0772             ath_dbg(common, PS,
0773                 "Add PM=1 for a TX frame while in PS mode\n");
0774             hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
0775         }
0776     }
0777
0778     if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
0779         /*
0780          * We are using PS-Poll and mac80211 can request TX while in
0781          * power save mode. Need to wake up hardware for the TX to be
0782          * completed and if needed, also for RX of buffered frames.
0783          */
0784         ath9k_ps_wakeup(sc);
0785         spin_lock_irqsave(&sc->sc_pm_lock, flags);
0786         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
0787             ath9k_hw_setrxabort(sc->sc_ah, 0);
0788         if (ieee80211_is_pspoll(hdr->frame_control)) {
0789             ath_dbg(common, PS,
0790                 "Sending PS-Poll to pick a buffered frame\n");
0791             sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
0792         } else {
0793             ath_dbg(common, PS, "Wake up to complete TX\n");
0794             sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
0795         }
0796         /*
0797          * The actual restore operation will happen only after
0798          * the ps_flags bit is cleared. We are just dropping
0799          * the ps_usecount here.
0800          */
0801         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
0802         ath9k_ps_restore(sc);
0803     }
0804
0805     /*
0806      * Cannot tx while the hardware is in full sleep, it first needs a full
0807      * chip reset to recover from that
0808      */
0809     if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
0810         ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
0811         goto exit;
0812     }
0813
0814     memset(&txctl, 0, sizeof(struct ath_tx_control));
0815     txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
0816     txctl.sta = control->sta;
0817
0818     ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
0819
0820     if (ath_tx_start(hw, skb, &txctl) != 0) {
0821         ath_dbg(common, XMIT, "TX failed\n");
0822         TX_STAT_INC(sc, txctl.txq->axq_qnum, txfailed);
0823         goto exit;
0824     }
0825
0826     return;
0827 exit:
0828     ieee80211_free_txskb(hw, skb);
0829 }
0830
0831 static bool ath9k_txq_list_has_key(struct list_head *txq_list, u32 keyix)
0832 {
0833     struct ath_buf *bf;
0834     struct ieee80211_tx_info *txinfo;
0835     struct ath_frame_info *fi;
0836
0837     list_for_each_entry(bf, txq_list, list) {
0838         if (bf->bf_state.stale || !bf->bf_mpdu)
0839             continue;
0840
0841         txinfo = IEEE80211_SKB_CB(bf->bf_mpdu);
0842         fi = (struct ath_frame_info *)&txinfo->status.status_driver_data[0];
0843         if (fi->keyix == keyix)
0844             return true;
0845     }
0846
0847     return false;
0848 }
0849
0850 static bool ath9k_txq_has_key(struct ath_softc *sc, u32 keyix)
0851 {
0852     struct ath_hw *ah = sc->sc_ah;
0853     int i;
0854     struct ath_txq *txq;
0855     bool key_in_use = false;
0856
0857     for (i = 0; !key_in_use && i < ATH9K_NUM_TX_QUEUES; i++) {
0858         if (!ATH_TXQ_SETUP(sc, i))
0859             continue;
0860         txq = &sc->tx.txq[i];
0861         if (!txq->axq_depth)
0862             continue;
0863         if (!ath9k_hw_numtxpending(ah, txq->axq_qnum))
0864             continue;
0865
0866         ath_txq_lock(sc, txq);
0867         key_in_use = ath9k_txq_list_has_key(&txq->axq_q, keyix);
0868         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
0869             int idx = txq->txq_tailidx;
0870
0871             while (!key_in_use &&
0872                    !list_empty(&txq->txq_fifo[idx])) {
0873                 key_in_use = ath9k_txq_list_has_key(
0874                     &txq->txq_fifo[idx], keyix);
0875                 INCR(idx, ATH_TXFIFO_DEPTH);
0876             }
0877         }
0878         ath_txq_unlock(sc, txq);
0879     }
0880
0881     return key_in_use;
0882 }
0883
0884 static void ath9k_pending_key_del(struct ath_softc *sc, u8 keyix)
0885 {
0886     struct ath_hw *ah = sc->sc_ah;
0887     struct ath_common *common = ath9k_hw_common(ah);
0888
0889     if (!test_bit(keyix, ah->pending_del_keymap) ||
0890         ath9k_txq_has_key(sc, keyix))
0891         return;
0892
0893     /* No more TXQ frames point to this key cache entry, so delete it. */
0894     clear_bit(keyix, ah->pending_del_keymap);
0895     ath_key_delete(common, keyix);
0896 }
0897
0898 static void ath9k_stop(struct ieee80211_hw *hw)
0899 {
0900     struct ath_softc *sc = hw->priv;
0901     struct ath_hw *ah = sc->sc_ah;
0902     struct ath_common *common = ath9k_hw_common(ah);
0903     bool prev_idle;
0904     int i;
0905
0906     ath9k_deinit_channel_context(sc);
0907
0908     mutex_lock(&sc->mutex);
0909
0910     ath9k_rng_stop(sc);
0911
0912     ath_cancel_work(sc);
0913
0914     if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
0915         ath_dbg(common, ANY, "Device not present\n");
0916         mutex_unlock(&sc->mutex);
0917         return;
0918     }
0919
0920     /* Ensure HW is awake when we try to shut it down. */
0921     ath9k_ps_wakeup(sc);
0922
0923     spin_lock_bh(&sc->sc_pcu_lock);
0924
0925     /* prevent tasklets to enable interrupts once we disable them */
0926     ah->imask &= ~ATH9K_INT_GLOBAL;
0927
0928     /* make sure h/w will not generate any interrupt
0929      * before setting the invalid flag. */
0930     ath9k_hw_disable_interrupts(ah);
0931
0932     spin_unlock_bh(&sc->sc_pcu_lock);
0933
0934     /* we can now sync irq and kill any running tasklets, since we already
0935      * disabled interrupts and not holding a spin lock */
0936     synchronize_irq(sc->irq);
0937     tasklet_kill(&sc->intr_tq);
0938     tasklet_kill(&sc->bcon_tasklet);
0939
0940     prev_idle = sc->ps_idle;
0941     sc->ps_idle = true;
0942
0943     spin_lock_bh(&sc->sc_pcu_lock);
0944
0945     if (ah->led_pin >= 0) {
0946         ath9k_hw_set_gpio(ah, ah->led_pin,
0947                   (ah->config.led_active_high) ? 0 : 1);
0948         ath9k_hw_gpio_request_in(ah, ah->led_pin, NULL);
0949     }
0950
0951     ath_prepare_reset(sc);
0952
0953     if (sc->rx.frag) {
0954         dev_kfree_skb_any(sc->rx.frag);
0955         sc->rx.frag = NULL;
0956     }
0957
0958     if (!ah->curchan)
0959         ah->curchan = ath9k_cmn_get_channel(hw, ah,
0960                             &sc->cur_chan->chandef);
0961
0962     ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
0963
0964     set_bit(ATH_OP_INVALID, &common->op_flags);
0965
0966     ath9k_hw_phy_disable(ah);
0967
0968     ath9k_hw_configpcipowersave(ah, true);
0969
0970     spin_unlock_bh(&sc->sc_pcu_lock);
0971
0972     for (i = 0; i < ATH_KEYMAX; i++)
0973         ath9k_pending_key_del(sc, i);
0974
0975     /* Clear key cache entries explicitly to get rid of any potentially
0976      * remaining keys.
0977      */
0978     ath9k_cmn_init_crypto(sc->sc_ah);
0979
0980     ath9k_ps_restore(sc);
0981
0982     sc->ps_idle = prev_idle;
0983
0984     mutex_unlock(&sc->mutex);
0985
0986     ath_dbg(common, CONFIG, "Driver halt\n");
0987 }
0988
0989 static bool ath9k_uses_beacons(int type)
0990 {
0991     switch (type) {
0992     case NL80211_IFTYPE_AP:
0993     case NL80211_IFTYPE_ADHOC:
0994     case NL80211_IFTYPE_MESH_POINT:
0995         return true;
0996     default:
0997         return false;
0998     }
0999 }
1000
1001 static void ath9k_vif_iter_set_beacon(struct ath9k_vif_iter_data *iter_data,
1002                       struct ieee80211_vif *vif)
1003 {
1004     /* Use the first (configured) interface, but prefering AP interfaces. */
1005     if (!iter_data->primary_beacon_vif) {
1006         iter_data->primary_beacon_vif = vif;
1007     } else {
1008         if (iter_data->primary_beacon_vif->type != NL80211_IFTYPE_AP &&
1009             vif->type == NL80211_IFTYPE_AP)
1010             iter_data->primary_beacon_vif = vif;
1011     }
1012
1013     iter_data->beacons = true;
1014     iter_data->nbcnvifs += 1;
1015 }
1016
1017 static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
1018                u8 *mac, struct ieee80211_vif *vif)
1019 {
1020     struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
1021     int i;
1022
1023     if (iter_data->has_hw_macaddr) {
1024         for (i = 0; i < ETH_ALEN; i++)
1025             iter_data->mask[i] &=
1026                 ~(iter_data->hw_macaddr[i] ^ mac[i]);
1027     } else {
1028         memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
1029         iter_data->has_hw_macaddr = true;
1030     }
1031
1032     if (!vif->bss_conf.use_short_slot)
1033         iter_data->slottime = 20;
1034
1035     switch (vif->type) {
1036     case NL80211_IFTYPE_AP:
1037         iter_data->naps++;
1038         if (vif->bss_conf.enable_beacon)
1039             ath9k_vif_iter_set_beacon(iter_data, vif);
1040         break;
1041     case NL80211_IFTYPE_STATION:
1042         iter_data->nstations++;
1043         if (avp->assoc && !iter_data->primary_sta)
1044             iter_data->primary_sta = vif;
1045         break;
1046     case NL80211_IFTYPE_OCB:
1047         iter_data->nocbs++;
1048         break;
1049     case NL80211_IFTYPE_ADHOC:
1050         iter_data->nadhocs++;
1051         if (vif->bss_conf.enable_beacon)
1052             ath9k_vif_iter_set_beacon(iter_data, vif);
1053         break;
1054     case NL80211_IFTYPE_MESH_POINT:
1055         iter_data->nmeshes++;
1056         if (vif->bss_conf.enable_beacon)
1057             ath9k_vif_iter_set_beacon(iter_data, vif);
1058         break;
1059     default:
1060         break;
1061     }
1062 }
1063
1064 static void ath9k_update_bssid_mask(struct ath_softc *sc,
1065                     struct ath_chanctx *ctx,
1066                     struct ath9k_vif_iter_data *iter_data)
1067 {
1068     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1069     struct ath_vif *avp;
1070     int i;
1071
1072     if (!ath9k_is_chanctx_enabled())
1073         return;
1074
1075     list_for_each_entry(avp, &ctx->vifs, list) {
1076         if (ctx->nvifs_assigned != 1)
1077             continue;
1078
1079         if (!iter_data->has_hw_macaddr)
1080             continue;
1081
1082         ether_addr_copy(common->curbssid, avp->bssid);
1083
1084         /* perm_addr will be used as the p2p device address. */
1085         for (i = 0; i < ETH_ALEN; i++)
1086             iter_data->mask[i] &=
1087                 ~(iter_data->hw_macaddr[i] ^
1088                   sc->hw->wiphy->perm_addr[i]);
1089     }
1090 }
1091
1092 /* Called with sc->mutex held. */
1093 void ath9k_calculate_iter_data(struct ath_softc *sc,
1094                    struct ath_chanctx *ctx,
1095                    struct ath9k_vif_iter_data *iter_data)
1096 {
1097     struct ath_vif *avp;
1098
1099     /*
1100      * The hardware will use primary station addr together with the
1101      * BSSID mask when matching addresses.
1102      */
1103     memset(iter_data, 0, sizeof(*iter_data));
1104     eth_broadcast_addr(iter_data->mask);
1105     iter_data->slottime = 9;
1106
1107     list_for_each_entry(avp, &ctx->vifs, list)
1108         ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
1109
1110     ath9k_update_bssid_mask(sc, ctx, iter_data);
1111 }
1112
1113 static void ath9k_set_assoc_state(struct ath_softc *sc,
1114                   struct ieee80211_vif *vif, bool changed)
1115 {
1116     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1117     struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
1118     unsigned long flags;
1119
1120     set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1121
1122     ether_addr_copy(common->curbssid, avp->bssid);
1123     common->curaid = avp->aid;
1124     ath9k_hw_write_associd(sc->sc_ah);
1125
1126     if (changed) {
1127         common->last_rssi = ATH_RSSI_DUMMY_MARKER;
1128         sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1129
1130         spin_lock_irqsave(&sc->sc_pm_lock, flags);
1131         sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1132         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1133     }
1134
1135     if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1136         ath9k_mci_update_wlan_channels(sc, false);
1137
1138     ath_dbg(common, CONFIG,
1139         "Primary Station interface: %pM, BSSID: %pM\n",
1140         vif->addr, common->curbssid);
1141 }
1142
1143 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1144 static void ath9k_set_offchannel_state(struct ath_softc *sc)
1145 {
1146     struct ath_hw *ah = sc->sc_ah;
1147     struct ath_common *common = ath9k_hw_common(ah);
1148     struct ieee80211_vif *vif = NULL;
1149
1150     ath9k_ps_wakeup(sc);
1151
1152     if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
1153         vif = sc->offchannel.scan_vif;
1154     else
1155         vif = sc->offchannel.roc_vif;
1156
1157     if (WARN_ON(!vif))
1158         goto exit;
1159
1160     eth_zero_addr(common->curbssid);
1161     eth_broadcast_addr(common->bssidmask);
1162     memcpy(common->macaddr, vif->addr, ETH_ALEN);
1163     common->curaid = 0;
1164     ah->opmode = vif->type;
1165     ah->imask &= ~ATH9K_INT_SWBA;
1166     ah->imask &= ~ATH9K_INT_TSFOOR;
1167     ah->slottime = 9;
1168
1169     ath_hw_setbssidmask(common);
1170     ath9k_hw_setopmode(ah);
1171     ath9k_hw_write_associd(sc->sc_ah);
1172     ath9k_hw_set_interrupts(ah);
1173     ath9k_hw_init_global_settings(ah);
1174
1175 exit:
1176     ath9k_ps_restore(sc);
1177 }
1178 #endif
1179
1180 /* Called with sc->mutex held. */
1181 void ath9k_calculate_summary_state(struct ath_softc *sc,
1182                    struct ath_chanctx *ctx)
1183 {
1184     struct ath_hw *ah = sc->sc_ah;
1185     struct ath_common *common = ath9k_hw_common(ah);
1186     struct ath9k_vif_iter_data iter_data;
1187
1188     ath_chanctx_check_active(sc, ctx);
1189
1190     if (ctx != sc->cur_chan)
1191         return;
1192
1193 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1194     if (ctx == &sc->offchannel.chan)
1195         return ath9k_set_offchannel_state(sc);
1196 #endif
1197
1198     ath9k_ps_wakeup(sc);
1199     ath9k_calculate_iter_data(sc, ctx, &iter_data);
1200
1201     if (iter_data.has_hw_macaddr)
1202         memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN);
1203
1204     memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1205     ath_hw_setbssidmask(common);
1206
1207     if (iter_data.naps > 0) {
1208         ath9k_hw_set_tsfadjust(ah, true);
1209         ah->opmode = NL80211_IFTYPE_AP;
1210     } else {
1211         ath9k_hw_set_tsfadjust(ah, false);
1212         if (iter_data.beacons)
1213             ath9k_beacon_ensure_primary_slot(sc);
1214
1215         if (iter_data.nmeshes)
1216             ah->opmode = NL80211_IFTYPE_MESH_POINT;
1217         else if (iter_data.nocbs)
1218             ah->opmode = NL80211_IFTYPE_OCB;
1219         else if (iter_data.nadhocs)
1220             ah->opmode = NL80211_IFTYPE_ADHOC;
1221         else
1222             ah->opmode = NL80211_IFTYPE_STATION;
1223     }
1224
1225     ath9k_hw_setopmode(ah);
1226
1227     ctx->switch_after_beacon = false;
1228     if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
1229         ah->imask |= ATH9K_INT_TSFOOR;
1230     else {
1231         ah->imask &= ~ATH9K_INT_TSFOOR;
1232         if (iter_data.naps == 1 && iter_data.beacons)
1233             ctx->switch_after_beacon = true;
1234     }
1235
1236     if (ah->opmode == NL80211_IFTYPE_STATION) {
1237         bool changed = (iter_data.primary_sta != ctx->primary_sta);
1238
1239         if (iter_data.primary_sta) {
1240             iter_data.primary_beacon_vif = iter_data.primary_sta;
1241             iter_data.beacons = true;
1242             ath9k_set_assoc_state(sc, iter_data.primary_sta,
1243                           changed);
1244             ctx->primary_sta = iter_data.primary_sta;
1245         } else {
1246             ctx->primary_sta = NULL;
1247             eth_zero_addr(common->curbssid);
1248             common->curaid = 0;
1249             ath9k_hw_write_associd(sc->sc_ah);
1250             if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1251                 ath9k_mci_update_wlan_channels(sc, true);
1252         }
1253     }
1254     sc->nbcnvifs = iter_data.nbcnvifs;
1255     ath9k_beacon_config(sc, iter_data.primary_beacon_vif,
1256                 iter_data.beacons);
1257     ath9k_hw_set_interrupts(ah);
1258
1259     if (ah->slottime != iter_data.slottime) {
1260         ah->slottime = iter_data.slottime;
1261         ath9k_hw_init_global_settings(ah);
1262     }
1263
1264     if (iter_data.primary_sta)
1265         set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1266     else
1267         clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1268
1269     ath_dbg(common, CONFIG,
1270         "macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
1271         common->macaddr, common->curbssid, common->bssidmask);
1272
1273     ath9k_ps_restore(sc);
1274 }
1275
1276 static void ath9k_tpc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1277 {
1278     int *power = data;
1279
1280     if (vif->bss_conf.txpower == INT_MIN)
1281         return;
1282
1283     if (*power < vif->bss_conf.txpower)
1284         *power = vif->bss_conf.txpower;
1285 }
1286
1287 /* Called with sc->mutex held. */
1288 void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif)
1289 {
1290     int power;
1291     struct ath_hw *ah = sc->sc_ah;
1292     struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
1293
1294     ath9k_ps_wakeup(sc);
1295     if (ah->tpc_enabled) {
1296         power = (vif) ? vif->bss_conf.txpower : -1;
1297         ieee80211_iterate_active_interfaces_atomic(
1298                 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1299                 ath9k_tpc_vif_iter, &power);
1300         if (power == -1)
1301             power = sc->hw->conf.power_level;
1302     } else {
1303         power = sc->hw->conf.power_level;
1304     }
1305     sc->cur_chan->txpower = 2 * power;
1306     ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
1307     sc->cur_chan->cur_txpower = reg->max_power_level;
1308     ath9k_ps_restore(sc);
1309 }
1310
1311 static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
1312                    struct ieee80211_vif *vif)
1313 {
1314     int i;
1315
1316     if (!ath9k_is_chanctx_enabled())
1317         return;
1318
1319     for (i = 0; i < IEEE80211_NUM_ACS; i++)
1320         vif->hw_queue[i] = i;
1321
1322     if (vif->type == NL80211_IFTYPE_AP ||
1323         vif->type == NL80211_IFTYPE_MESH_POINT)
1324         vif->cab_queue = hw->queues - 2;
1325     else
1326         vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
1327 }
1328
1329 static int ath9k_add_interface(struct ieee80211_hw *hw,
1330                    struct ieee80211_vif *vif)
1331 {
1332     struct ath_softc *sc = hw->priv;
1333     struct ath_hw *ah = sc->sc_ah;
1334     struct ath_common *common = ath9k_hw_common(ah);
1335     struct ath_vif *avp = (void *)vif->drv_priv;
1336     struct ath_node *an = &avp->mcast_node;
1337
1338     mutex_lock(&sc->mutex);
1339     if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
1340         if (sc->cur_chan->nvifs >= 1) {
1341             mutex_unlock(&sc->mutex);
1342             return -EOPNOTSUPP;
1343         }
1344         sc->tx99_vif = vif;
1345     }
1346
1347     ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
1348     sc->cur_chan->nvifs++;
1349
1350     if (vif->type == NL80211_IFTYPE_STATION && ath9k_is_chanctx_enabled())
1351         vif->driver_flags |= IEEE80211_VIF_GET_NOA_UPDATE;
1352
1353     if (ath9k_uses_beacons(vif->type))
1354         ath9k_beacon_assign_slot(sc, vif);
1355
1356     avp->vif = vif;
1357     if (!ath9k_is_chanctx_enabled()) {
1358         avp->chanctx = sc->cur_chan;
1359         list_add_tail(&avp->list, &avp->chanctx->vifs);
1360     }
1361
1362     ath9k_calculate_summary_state(sc, avp->chanctx);
1363
1364     ath9k_assign_hw_queues(hw, vif);
1365
1366     ath9k_set_txpower(sc, vif);
1367
1368     an->sc = sc;
1369     an->sta = NULL;
1370     an->vif = vif;
1371     an->no_ps_filter = true;
1372     ath_tx_node_init(sc, an);
1373
1374     mutex_unlock(&sc->mutex);
1375     return 0;
1376 }
1377
1378 static int ath9k_change_interface(struct ieee80211_hw *hw,
1379                   struct ieee80211_vif *vif,
1380                   enum nl80211_iftype new_type,
1381                   bool p2p)
1382 {
1383     struct ath_softc *sc = hw->priv;
1384     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1385     struct ath_vif *avp = (void *)vif->drv_priv;
1386
1387     mutex_lock(&sc->mutex);
1388
1389     if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
1390         mutex_unlock(&sc->mutex);
1391         return -EOPNOTSUPP;
1392     }
1393
1394     ath_dbg(common, CONFIG, "Change Interface\n");
1395
1396     if (ath9k_uses_beacons(vif->type))
1397         ath9k_beacon_remove_slot(sc, vif);
1398
1399     vif->type = new_type;
1400     vif->p2p = p2p;
1401
1402     if (ath9k_uses_beacons(vif->type))
1403         ath9k_beacon_assign_slot(sc, vif);
1404
1405     ath9k_assign_hw_queues(hw, vif);
1406     ath9k_calculate_summary_state(sc, avp->chanctx);
1407
1408     ath9k_set_txpower(sc, vif);
1409
1410     mutex_unlock(&sc->mutex);
1411     return 0;
1412 }
1413
1414 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1415                    struct ieee80211_vif *vif)
1416 {
1417     struct ath_softc *sc = hw->priv;
1418     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1419     struct ath_vif *avp = (void *)vif->drv_priv;
1420
1421     ath_dbg(common, CONFIG, "Detach Interface\n");
1422
1423     mutex_lock(&sc->mutex);
1424
1425     ath9k_p2p_remove_vif(sc, vif);
1426
1427     sc->cur_chan->nvifs--;
1428     sc->tx99_vif = NULL;
1429     if (!ath9k_is_chanctx_enabled())
1430         list_del(&avp->list);
1431
1432     if (ath9k_uses_beacons(vif->type))
1433         ath9k_beacon_remove_slot(sc, vif);
1434
1435     ath_tx_node_cleanup(sc, &avp->mcast_node);
1436
1437     ath9k_calculate_summary_state(sc, avp->chanctx);
1438
1439     ath9k_set_txpower(sc, NULL);
1440
1441     mutex_unlock(&sc->mutex);
1442 }
1443
1444 static void ath9k_enable_ps(struct ath_softc *sc)
1445 {
1446     struct ath_hw *ah = sc->sc_ah;
1447     struct ath_common *common = ath9k_hw_common(ah);
1448
1449     if (IS_ENABLED(CONFIG_ATH9K_TX99))
1450         return;
1451
1452     sc->ps_enabled = true;
1453     if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1454         if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1455             ah->imask |= ATH9K_INT_TIM_TIMER;
1456             ath9k_hw_set_interrupts(ah);
1457         }
1458         ath9k_hw_setrxabort(ah, 1);
1459     }
1460     ath_dbg(common, PS, "PowerSave enabled\n");
1461 }
1462
1463 static void ath9k_disable_ps(struct ath_softc *sc)
1464 {
1465     struct ath_hw *ah = sc->sc_ah;
1466     struct ath_common *common = ath9k_hw_common(ah);
1467
1468     if (IS_ENABLED(CONFIG_ATH9K_TX99))
1469         return;
1470
1471     sc->ps_enabled = false;
1472     ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1473     if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1474         ath9k_hw_setrxabort(ah, 0);
1475         sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1476                   PS_WAIT_FOR_CAB |
1477                   PS_WAIT_FOR_PSPOLL_DATA |
1478                   PS_WAIT_FOR_TX_ACK);
1479         if (ah->imask & ATH9K_INT_TIM_TIMER) {
1480             ah->imask &= ~ATH9K_INT_TIM_TIMER;
1481             ath9k_hw_set_interrupts(ah);
1482         }
1483     }
1484     ath_dbg(common, PS, "PowerSave disabled\n");
1485 }
1486
1487 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1488 {
1489     struct ath_softc *sc = hw->priv;
1490     struct ath_hw *ah = sc->sc_ah;
1491     struct ath_common *common = ath9k_hw_common(ah);
1492     struct ieee80211_conf *conf = &hw->conf;
1493     struct ath_chanctx *ctx = sc->cur_chan;
1494
1495     ath9k_ps_wakeup(sc);
1496     mutex_lock(&sc->mutex);
1497
1498     if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1499         sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1500         if (sc->ps_idle) {
1501             ath_cancel_work(sc);
1502             ath9k_stop_btcoex(sc);
1503         } else {
1504             ath9k_start_btcoex(sc);
1505             /*
1506              * The chip needs a reset to properly wake up from
1507              * full sleep
1508              */
1509             ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
1510         }
1511     }
1512
1513     /*
1514      * We just prepare to enable PS. We have to wait until our AP has
1515      * ACK'd our null data frame to disable RX otherwise we'll ignore
1516      * those ACKs and end up retransmitting the same null data frames.
1517      * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1518      */
1519     if (changed & IEEE80211_CONF_CHANGE_PS) {
1520         unsigned long flags;
1521         spin_lock_irqsave(&sc->sc_pm_lock, flags);
1522         if (conf->flags & IEEE80211_CONF_PS)
1523             ath9k_enable_ps(sc);
1524         else
1525             ath9k_disable_ps(sc);
1526         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1527     }
1528
1529     if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1530         if (conf->flags & IEEE80211_CONF_MONITOR) {
1531             ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1532             sc->sc_ah->is_monitoring = true;
1533         } else {
1534             ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1535             sc->sc_ah->is_monitoring = false;
1536         }
1537     }
1538
1539     if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
1540         ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
1541         ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
1542     }
1543
1544     if (changed & IEEE80211_CONF_CHANGE_POWER)
1545         ath9k_set_txpower(sc, NULL);
1546
1547     mutex_unlock(&sc->mutex);
1548     ath9k_ps_restore(sc);
1549
1550     return 0;
1551 }
1552
1553 #define SUPPORTED_FILTERS           \
1554     (FIF_ALLMULTI |             \
1555     FIF_CONTROL |               \
1556     FIF_PSPOLL |                \
1557     FIF_OTHER_BSS |             \
1558     FIF_BCN_PRBRESP_PROMISC |       \
1559     FIF_PROBE_REQ |             \
1560     FIF_MCAST_ACTION |          \
1561     FIF_FCSFAIL)
1562
1563 /* FIXME: sc->sc_full_reset ? */
1564 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1565                    unsigned int changed_flags,
1566                    unsigned int *total_flags,
1567                    u64 multicast)
1568 {
1569     struct ath_softc *sc = hw->priv;
1570     struct ath_chanctx *ctx;
1571     u32 rfilt;
1572
1573     changed_flags &= SUPPORTED_FILTERS;
1574     *total_flags &= SUPPORTED_FILTERS;
1575
1576     spin_lock_bh(&sc->chan_lock);
1577     ath_for_each_chanctx(sc, ctx)
1578         ctx->rxfilter = *total_flags;
1579 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1580     sc->offchannel.chan.rxfilter = *total_flags;
1581 #endif
1582     spin_unlock_bh(&sc->chan_lock);
1583
1584     ath9k_ps_wakeup(sc);
1585     rfilt = ath_calcrxfilter(sc);
1586     ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1587     ath9k_ps_restore(sc);
1588
1589     ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1590         rfilt);
1591 }
1592
1593 static int ath9k_sta_add(struct ieee80211_hw *hw,
1594              struct ieee80211_vif *vif,
1595              struct ieee80211_sta *sta)
1596 {
1597     struct ath_softc *sc = hw->priv;
1598     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1599     struct ath_node *an = (struct ath_node *) sta->drv_priv;
1600     struct ieee80211_key_conf ps_key = { };
1601     int key;
1602
1603     ath_node_attach(sc, sta, vif);
1604
1605     if (vif->type != NL80211_IFTYPE_AP &&
1606         vif->type != NL80211_IFTYPE_AP_VLAN)
1607         return 0;
1608
1609     key = ath_key_config(common, vif, sta, &ps_key);
1610     if (key > 0) {
1611         an->ps_key = key;
1612         an->key_idx[0] = key;
1613     }
1614
1615     return 0;
1616 }
1617
1618 static void ath9k_del_ps_key(struct ath_softc *sc,
1619                  struct ieee80211_vif *vif,
1620                  struct ieee80211_sta *sta)
1621 {
1622     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1623     struct ath_node *an = (struct ath_node *) sta->drv_priv;
1624
1625     if (!an->ps_key)
1626         return;
1627
1628     ath_key_delete(common, an->ps_key);
1629     an->ps_key = 0;
1630     an->key_idx[0] = 0;
1631 }
1632
1633 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1634                 struct ieee80211_vif *vif,
1635                 struct ieee80211_sta *sta)
1636 {
1637     struct ath_softc *sc = hw->priv;
1638
1639     ath9k_del_ps_key(sc, vif, sta);
1640     ath_node_detach(sc, sta);
1641
1642     return 0;
1643 }
1644
1645 static int ath9k_sta_state(struct ieee80211_hw *hw,
1646                struct ieee80211_vif *vif,
1647                struct ieee80211_sta *sta,
1648                enum ieee80211_sta_state old_state,
1649                enum ieee80211_sta_state new_state)
1650 {
1651     struct ath_softc *sc = hw->priv;
1652     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1653     int ret = 0;
1654
1655     if (old_state == IEEE80211_STA_NOTEXIST &&
1656         new_state == IEEE80211_STA_NONE) {
1657         ret = ath9k_sta_add(hw, vif, sta);
1658         ath_dbg(common, CONFIG,
1659             "Add station: %pM\n", sta->addr);
1660     } else if (old_state == IEEE80211_STA_NONE &&
1661            new_state == IEEE80211_STA_NOTEXIST) {
1662         ret = ath9k_sta_remove(hw, vif, sta);
1663         ath_dbg(common, CONFIG,
1664             "Remove station: %pM\n", sta->addr);
1665     }
1666
1667     if (ath9k_is_chanctx_enabled()) {
1668         if (vif->type == NL80211_IFTYPE_STATION) {
1669             if (old_state == IEEE80211_STA_ASSOC &&
1670                 new_state == IEEE80211_STA_AUTHORIZED)
1671                 ath_chanctx_event(sc, vif,
1672                           ATH_CHANCTX_EVENT_AUTHORIZED);
1673         }
1674     }
1675
1676     return ret;
1677 }
1678
1679 static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
1680                     struct ath_node *an,
1681                     bool set)
1682 {
1683     int i;
1684
1685     for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1686         if (!an->key_idx[i])
1687             continue;
1688         ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
1689     }
1690 }
1691
1692 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1693              struct ieee80211_vif *vif,
1694              enum sta_notify_cmd cmd,
1695              struct ieee80211_sta *sta)
1696 {
1697     struct ath_softc *sc = hw->priv;
1698     struct ath_node *an = (struct ath_node *) sta->drv_priv;
1699
1700     switch (cmd) {
1701     case STA_NOTIFY_SLEEP:
1702         an->sleeping = true;
1703         ath_tx_aggr_sleep(sta, sc, an);
1704         ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
1705         break;
1706     case STA_NOTIFY_AWAKE:
1707         ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
1708         an->sleeping = false;
1709         ath_tx_aggr_wakeup(sc, an);
1710         break;
1711     }
1712 }
1713
1714 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1715              struct ieee80211_vif *vif,
1716              unsigned int link_id, u16 queue,
1717              const struct ieee80211_tx_queue_params *params)
1718 {
1719     struct ath_softc *sc = hw->priv;
1720     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1721     struct ath_txq *txq;
1722     struct ath9k_tx_queue_info qi;
1723     int ret = 0;
1724
1725     if (queue >= IEEE80211_NUM_ACS)
1726         return 0;
1727
1728     txq = sc->tx.txq_map[queue];
1729
1730     ath9k_ps_wakeup(sc);
1731     mutex_lock(&sc->mutex);
1732
1733     memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1734
1735     qi.tqi_aifs = params->aifs;
1736     qi.tqi_cwmin = params->cw_min;
1737     qi.tqi_cwmax = params->cw_max;
1738     qi.tqi_burstTime = params->txop * 32;
1739
1740     ath_dbg(common, CONFIG,
1741         "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1742         queue, txq->axq_qnum, params->aifs, params->cw_min,
1743         params->cw_max, params->txop);
1744
1745     ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1746     ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1747     if (ret)
1748         ath_err(common, "TXQ Update failed\n");
1749
1750     mutex_unlock(&sc->mutex);
1751     ath9k_ps_restore(sc);
1752
1753     return ret;
1754 }
1755
1756 static int ath9k_set_key(struct ieee80211_hw *hw,
1757              enum set_key_cmd cmd,
1758              struct ieee80211_vif *vif,
1759              struct ieee80211_sta *sta,
1760              struct ieee80211_key_conf *key)
1761 {
1762     struct ath_softc *sc = hw->priv;
1763     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1764     struct ath_node *an = NULL;
1765     int ret = 0, i;
1766
1767     if (ath9k_modparam_nohwcrypt)
1768         return -ENOSPC;
1769
1770     if ((vif->type == NL80211_IFTYPE_ADHOC ||
1771          vif->type == NL80211_IFTYPE_MESH_POINT) &&
1772         (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1773          key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1774         !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1775         /*
1776          * For now, disable hw crypto for the RSN IBSS group keys. This
1777          * could be optimized in the future to use a modified key cache
1778          * design to support per-STA RX GTK, but until that gets
1779          * implemented, use of software crypto for group addressed
1780          * frames is a acceptable to allow RSN IBSS to be used.
1781          */
1782         return -EOPNOTSUPP;
1783     }
1784
1785     /* There may be MPDUs queued for the outgoing PTK key. Flush queues to
1786      * make sure these are not send unencrypted or with a wrong (new) key
1787      */
1788     if (cmd == DISABLE_KEY && key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
1789         ieee80211_stop_queues(hw);
1790         ath9k_flush(hw, vif, 0, true);
1791         ieee80211_wake_queues(hw);
1792     }
1793
1794     mutex_lock(&sc->mutex);
1795     ath9k_ps_wakeup(sc);
1796     ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
1797     if (sta)
1798         an = (struct ath_node *)sta->drv_priv;
1799
1800     /* Delete pending key cache entries if no more frames are pointing to
1801      * them in TXQs.
1802      */
1803     for (i = 0; i < ATH_KEYMAX; i++)
1804         ath9k_pending_key_del(sc, i);
1805
1806     switch (cmd) {
1807     case SET_KEY:
1808         if (sta)
1809             ath9k_del_ps_key(sc, vif, sta);
1810
1811         key->hw_key_idx = 0;
1812         ret = ath_key_config(common, vif, sta, key);
1813         if (ret >= 0) {
1814             key->hw_key_idx = ret;
1815             /* push IV and Michael MIC generation to stack */
1816             key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1817             if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1818                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1819             if (sc->sc_ah->sw_mgmt_crypto_tx &&
1820                 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1821                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1822             ret = 0;
1823         }
1824         if (an && key->hw_key_idx) {
1825             for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1826                 if (an->key_idx[i])
1827                     continue;
1828                 an->key_idx[i] = key->hw_key_idx;
1829                 break;
1830             }
1831             WARN_ON(i == ARRAY_SIZE(an->key_idx));
1832         }
1833         break;
1834     case DISABLE_KEY:
1835         if (ath9k_txq_has_key(sc, key->hw_key_idx)) {
1836             /* Delay key cache entry deletion until there are no
1837              * remaining TXQ frames pointing to this entry.
1838              */
1839             set_bit(key->hw_key_idx, sc->sc_ah->pending_del_keymap);
1840             ath_hw_keysetmac(common, key->hw_key_idx, NULL);
1841         } else {
1842             ath_key_delete(common, key->hw_key_idx);
1843         }
1844         if (an) {
1845             for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1846                 if (an->key_idx[i] != key->hw_key_idx)
1847                     continue;
1848                 an->key_idx[i] = 0;
1849                 break;
1850             }
1851         }
1852         key->hw_key_idx = 0;
1853         break;
1854     default:
1855         ret = -EINVAL;
1856     }
1857
1858     ath9k_ps_restore(sc);
1859     mutex_unlock(&sc->mutex);
1860
1861     return ret;
1862 }
1863
1864 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1865                    struct ieee80211_vif *vif,
1866                    struct ieee80211_bss_conf *bss_conf,
1867                    u64 changed)
1868 {
1869 #define CHECK_ANI               \
1870     (BSS_CHANGED_ASSOC |            \
1871      BSS_CHANGED_IBSS |         \
1872      BSS_CHANGED_BEACON_ENABLED)
1873
1874     struct ath_softc *sc = hw->priv;
1875     struct ath_hw *ah = sc->sc_ah;
1876     struct ath_common *common = ath9k_hw_common(ah);
1877     struct ath_vif *avp = (void *)vif->drv_priv;
1878     int slottime;
1879
1880     ath9k_ps_wakeup(sc);
1881     mutex_lock(&sc->mutex);
1882
1883     if (changed & BSS_CHANGED_ASSOC) {
1884         ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1885             bss_conf->bssid, vif->cfg.assoc);
1886
1887         memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1888         avp->aid = vif->cfg.aid;
1889         avp->assoc = vif->cfg.assoc;
1890
1891         ath9k_calculate_summary_state(sc, avp->chanctx);
1892     }
1893
1894     if ((changed & BSS_CHANGED_IBSS) ||
1895           (changed & BSS_CHANGED_OCB)) {
1896         memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1897         common->curaid = vif->cfg.aid;
1898         ath9k_hw_write_associd(sc->sc_ah);
1899     }
1900
1901     if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1902         (changed & BSS_CHANGED_BEACON_INT) ||
1903         (changed & BSS_CHANGED_BEACON_INFO)) {
1904         ath9k_calculate_summary_state(sc, avp->chanctx);
1905     }
1906
1907     if ((avp->chanctx == sc->cur_chan) &&
1908         (changed & BSS_CHANGED_ERP_SLOT)) {
1909         if (bss_conf->use_short_slot)
1910             slottime = 9;
1911         else
1912             slottime = 20;
1913
1914         if (vif->type == NL80211_IFTYPE_AP) {
1915             /*
1916              * Defer update, so that connected stations can adjust
1917              * their settings at the same time.
1918              * See beacon.c for more details
1919              */
1920             sc->beacon.slottime = slottime;
1921             sc->beacon.updateslot = UPDATE;
1922         } else {
1923             ah->slottime = slottime;
1924             ath9k_hw_init_global_settings(ah);
1925         }
1926     }
1927
1928     if (changed & BSS_CHANGED_P2P_PS)
1929         ath9k_p2p_bss_info_changed(sc, vif);
1930
1931     if (changed & CHECK_ANI)
1932         ath_check_ani(sc);
1933
1934     if (changed & BSS_CHANGED_TXPOWER) {
1935         ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n",
1936             vif->addr, bss_conf->txpower, bss_conf->txpower_type);
1937         ath9k_set_txpower(sc, vif);
1938     }
1939
1940     mutex_unlock(&sc->mutex);
1941     ath9k_ps_restore(sc);
1942
1943 #undef CHECK_ANI
1944 }
1945
1946 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1947 {
1948     struct ath_softc *sc = hw->priv;
1949     struct ath_vif *avp = (void *)vif->drv_priv;
1950     u64 tsf;
1951
1952     mutex_lock(&sc->mutex);
1953     ath9k_ps_wakeup(sc);
1954     /* Get current TSF either from HW or kernel time. */
1955     if (sc->cur_chan == avp->chanctx) {
1956         tsf = ath9k_hw_gettsf64(sc->sc_ah);
1957     } else {
1958         tsf = sc->cur_chan->tsf_val +
1959               ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, NULL);
1960     }
1961     tsf += le64_to_cpu(avp->tsf_adjust);
1962     ath9k_ps_restore(sc);
1963     mutex_unlock(&sc->mutex);
1964
1965     return tsf;
1966 }
1967
1968 static void ath9k_set_tsf(struct ieee80211_hw *hw,
1969               struct ieee80211_vif *vif,
1970               u64 tsf)
1971 {
1972     struct ath_softc *sc = hw->priv;
1973     struct ath_vif *avp = (void *)vif->drv_priv;
1974
1975     mutex_lock(&sc->mutex);
1976     ath9k_ps_wakeup(sc);
1977     tsf -= le64_to_cpu(avp->tsf_adjust);
1978     ktime_get_raw_ts64(&avp->chanctx->tsf_ts);
1979     if (sc->cur_chan == avp->chanctx)
1980         ath9k_hw_settsf64(sc->sc_ah, tsf);
1981     avp->chanctx->tsf_val = tsf;
1982     ath9k_ps_restore(sc);
1983     mutex_unlock(&sc->mutex);
1984 }
1985
1986 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1987 {
1988     struct ath_softc *sc = hw->priv;
1989     struct ath_vif *avp = (void *)vif->drv_priv;
1990
1991     mutex_lock(&sc->mutex);
1992
1993     ath9k_ps_wakeup(sc);
1994     ktime_get_raw_ts64(&avp->chanctx->tsf_ts);
1995     if (sc->cur_chan == avp->chanctx)
1996         ath9k_hw_reset_tsf(sc->sc_ah);
1997     avp->chanctx->tsf_val = 0;
1998     ath9k_ps_restore(sc);
1999
2000     mutex_unlock(&sc->mutex);
2001 }
2002
2003 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2004                   struct ieee80211_vif *vif,
2005                   struct ieee80211_ampdu_params *params)
2006 {
2007     struct ath_softc *sc = hw->priv;
2008     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2009     bool flush = false;
2010     int ret = 0;
2011     struct ieee80211_sta *sta = params->sta;
2012     struct ath_node *an = (struct ath_node *)sta->drv_priv;
2013     enum ieee80211_ampdu_mlme_action action = params->action;
2014     u16 tid = params->tid;
2015     u16 *ssn = &params->ssn;
2016     struct ath_atx_tid *atid;
2017
2018     mutex_lock(&sc->mutex);
2019
2020     switch (action) {
2021     case IEEE80211_AMPDU_RX_START:
2022         break;
2023     case IEEE80211_AMPDU_RX_STOP:
2024         break;
2025     case IEEE80211_AMPDU_TX_START:
2026         if (ath9k_is_chanctx_enabled()) {
2027             if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2028                 ret = -EBUSY;
2029                 break;
2030             }
2031         }
2032         ath9k_ps_wakeup(sc);
2033         ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2034         if (!ret)
2035             ret = IEEE80211_AMPDU_TX_START_IMMEDIATE;
2036         ath9k_ps_restore(sc);
2037         break;
2038     case IEEE80211_AMPDU_TX_STOP_FLUSH:
2039     case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
2040         flush = true;
2041         fallthrough;
2042     case IEEE80211_AMPDU_TX_STOP_CONT:
2043         ath9k_ps_wakeup(sc);
2044         ath_tx_aggr_stop(sc, sta, tid);
2045         if (!flush)
2046             ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2047         ath9k_ps_restore(sc);
2048         break;
2049     case IEEE80211_AMPDU_TX_OPERATIONAL:
2050         atid = ath_node_to_tid(an, tid);
2051         atid->baw_size = IEEE80211_MIN_AMPDU_BUF <<
2052                     sta->deflink.ht_cap.ampdu_factor;
2053         break;
2054     default:
2055         ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
2056     }
2057
2058     mutex_unlock(&sc->mutex);
2059
2060     return ret;
2061 }
2062
2063 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2064                  struct survey_info *survey)
2065 {
2066     struct ath_softc *sc = hw->priv;
2067     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2068     struct ieee80211_supported_band *sband;
2069     struct ieee80211_channel *chan;
2070     unsigned long flags;
2071     int pos;
2072
2073     if (IS_ENABLED(CONFIG_ATH9K_TX99))
2074         return -EOPNOTSUPP;
2075
2076     spin_lock_irqsave(&common->cc_lock, flags);
2077     if (idx == 0)
2078         ath_update_survey_stats(sc);
2079
2080     sband = hw->wiphy->bands[NL80211_BAND_2GHZ];
2081     if (sband && idx >= sband->n_channels) {
2082         idx -= sband->n_channels;
2083         sband = NULL;
2084     }
2085
2086     if (!sband)
2087         sband = hw->wiphy->bands[NL80211_BAND_5GHZ];
2088
2089     if (!sband || idx >= sband->n_channels) {
2090         spin_unlock_irqrestore(&common->cc_lock, flags);
2091         return -ENOENT;
2092     }
2093
2094     chan = &sband->channels[idx];
2095     pos = chan->hw_value;
2096     memcpy(survey, &sc->survey[pos], sizeof(*survey));
2097     survey->channel = chan;
2098     spin_unlock_irqrestore(&common->cc_lock, flags);
2099
2100     return 0;
2101 }
2102
2103 static void ath9k_enable_dynack(struct ath_softc *sc)
2104 {
2105 #ifdef CONFIG_ATH9K_DYNACK
2106     u32 rfilt;
2107     struct ath_hw *ah = sc->sc_ah;
2108
2109     ath_dynack_reset(ah);
2110
2111     ah->dynack.enabled = true;
2112     rfilt = ath_calcrxfilter(sc);
2113     ath9k_hw_setrxfilter(ah, rfilt);
2114 #endif
2115 }
2116
2117 static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
2118                      s16 coverage_class)
2119 {
2120     struct ath_softc *sc = hw->priv;
2121     struct ath_hw *ah = sc->sc_ah;
2122
2123     if (IS_ENABLED(CONFIG_ATH9K_TX99))
2124         return;
2125
2126     mutex_lock(&sc->mutex);
2127
2128     if (coverage_class >= 0) {
2129         ah->coverage_class = coverage_class;
2130         if (ah->dynack.enabled) {
2131             u32 rfilt;
2132
2133             ah->dynack.enabled = false;
2134             rfilt = ath_calcrxfilter(sc);
2135             ath9k_hw_setrxfilter(ah, rfilt);
2136         }
2137         ath9k_ps_wakeup(sc);
2138         ath9k_hw_init_global_settings(ah);
2139         ath9k_ps_restore(sc);
2140     } else if (!ah->dynack.enabled) {
2141         ath9k_enable_dynack(sc);
2142     }
2143
2144     mutex_unlock(&sc->mutex);
2145 }
2146
2147 static bool ath9k_has_tx_pending(struct ath_softc *sc,
2148                  bool sw_pending)
2149 {
2150     int i, npend = 0;
2151
2152     for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2153         if (!ATH_TXQ_SETUP(sc, i))
2154             continue;
2155
2156         npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i],
2157                          sw_pending);
2158         if (npend)
2159             break;
2160     }
2161
2162     return !!npend;
2163 }
2164
2165 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2166             u32 queues, bool drop)
2167 {
2168     struct ath_softc *sc = hw->priv;
2169     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2170
2171     if (ath9k_is_chanctx_enabled()) {
2172         if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2173             goto flush;
2174
2175         /*
2176          * If MCC is active, extend the flush timeout
2177          * and wait for the HW/SW queues to become
2178          * empty. This needs to be done outside the
2179          * sc->mutex lock to allow the channel scheduler
2180          * to switch channel contexts.
2181          *
2182          * The vif queues have been stopped in mac80211,
2183          * so there won't be any incoming frames.
2184          */
2185         __ath9k_flush(hw, queues, drop, true, true);
2186         return;
2187     }
2188 flush:
2189     mutex_lock(&sc->mutex);
2190     __ath9k_flush(hw, queues, drop, true, false);
2191     mutex_unlock(&sc->mutex);
2192 }
2193
2194 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
2195            bool sw_pending, bool timeout_override)
2196 {
2197     struct ath_softc *sc = hw->priv;
2198     struct ath_hw *ah = sc->sc_ah;
2199     struct ath_common *common = ath9k_hw_common(ah);
2200     int timeout;
2201     bool drain_txq;
2202
2203     cancel_delayed_work_sync(&sc->hw_check_work);
2204
2205     if (ah->ah_flags & AH_UNPLUGGED) {
2206         ath_dbg(common, ANY, "Device has been unplugged!\n");
2207         return;
2208     }
2209
2210     if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
2211         ath_dbg(common, ANY, "Device not present\n");
2212         return;
2213     }
2214
2215     spin_lock_bh(&sc->chan_lock);
2216     if (timeout_override)
2217         timeout = HZ / 5;
2218     else
2219         timeout = sc->cur_chan->flush_timeout;
2220     spin_unlock_bh(&sc->chan_lock);
2221
2222     ath_dbg(common, CHAN_CTX,
2223         "Flush timeout: %d\n", jiffies_to_msecs(timeout));
2224
2225     if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending),
2226                    timeout) > 0)
2227         drop = false;
2228
2229     if (drop) {
2230         ath9k_ps_wakeup(sc);
2231         spin_lock_bh(&sc->sc_pcu_lock);
2232         drain_txq = ath_drain_all_txq(sc);
2233         spin_unlock_bh(&sc->sc_pcu_lock);
2234
2235         if (!drain_txq)
2236             ath_reset(sc, NULL);
2237
2238         ath9k_ps_restore(sc);
2239     }
2240
2241     ieee80211_queue_delayed_work(hw, &sc->hw_check_work,
2242                      ATH_HW_CHECK_POLL_INT);
2243 }
2244
2245 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2246 {
2247     struct ath_softc *sc = hw->priv;
2248
2249     return ath9k_has_tx_pending(sc, true);
2250 }
2251
2252 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
2253 {
2254     struct ath_softc *sc = hw->priv;
2255     struct ath_hw *ah = sc->sc_ah;
2256     struct ieee80211_vif *vif;
2257     struct ath_vif *avp;
2258     struct ath_buf *bf;
2259     struct ath_tx_status ts;
2260     bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2261     int status;
2262
2263     vif = sc->beacon.bslot[0];
2264     if (!vif)
2265         return 0;
2266
2267     if (!vif->bss_conf.enable_beacon)
2268         return 0;
2269
2270     avp = (void *)vif->drv_priv;
2271
2272     if (!sc->beacon.tx_processed && !edma) {
2273         tasklet_disable(&sc->bcon_tasklet);
2274
2275         bf = avp->av_bcbuf;
2276         if (!bf || !bf->bf_mpdu)
2277             goto skip;
2278
2279         status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2280         if (status == -EINPROGRESS)
2281             goto skip;
2282
2283         sc->beacon.tx_processed = true;
2284         sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2285
2286 skip:
2287         tasklet_enable(&sc->bcon_tasklet);
2288     }
2289
2290     return sc->beacon.tx_last;
2291 }
2292
2293 static int ath9k_get_stats(struct ieee80211_hw *hw,
2294                struct ieee80211_low_level_stats *stats)
2295 {
2296     struct ath_softc *sc = hw->priv;
2297     struct ath_hw *ah = sc->sc_ah;
2298     struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2299
2300     stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2301     stats->dot11RTSFailureCount = mib_stats->rts_bad;
2302     stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2303     stats->dot11RTSSuccessCount = mib_stats->rts_good;
2304     return 0;
2305 }
2306
2307 static u32 fill_chainmask(u32 cap, u32 new)
2308 {
2309     u32 filled = 0;
2310     int i;
2311
2312     for (i = 0; cap && new; i++, cap >>= 1) {
2313         if (!(cap & BIT(0)))
2314             continue;
2315
2316         if (new & BIT(0))
2317             filled |= BIT(i);
2318
2319         new >>= 1;
2320     }
2321
2322     return filled;
2323 }
2324
2325 static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
2326 {
2327     if (AR_SREV_9300_20_OR_LATER(ah))
2328         return true;
2329
2330     switch (val & 0x7) {
2331     case 0x1:
2332     case 0x3:
2333     case 0x7:
2334         return true;
2335     case 0x2:
2336         return (ah->caps.rx_chainmask == 1);
2337     default:
2338         return false;
2339     }
2340 }
2341
2342 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2343 {
2344     struct ath_softc *sc = hw->priv;
2345     struct ath_hw *ah = sc->sc_ah;
2346
2347     if (ah->caps.rx_chainmask != 1)
2348         rx_ant |= tx_ant;
2349
2350     if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
2351         return -EINVAL;
2352
2353     sc->ant_rx = rx_ant;
2354     sc->ant_tx = tx_ant;
2355
2356     if (ah->caps.rx_chainmask == 1)
2357         return 0;
2358
2359     /* AR9100 runs into calibration issues if not all rx chains are enabled */
2360     if (AR_SREV_9100(ah))
2361         ah->rxchainmask = 0x7;
2362     else
2363         ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2364
2365     ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2366     ath9k_cmn_reload_chainmask(ah);
2367
2368     return 0;
2369 }
2370
2371 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2372 {
2373     struct ath_softc *sc = hw->priv;
2374
2375     *tx_ant = sc->ant_tx;
2376     *rx_ant = sc->ant_rx;
2377     return 0;
2378 }
2379
2380 static void ath9k_sw_scan_start(struct ieee80211_hw *hw,
2381                 struct ieee80211_vif *vif,
2382                 const u8 *mac_addr)
2383 {
2384     struct ath_softc *sc = hw->priv;
2385     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2386     set_bit(ATH_OP_SCANNING, &common->op_flags);
2387 }
2388
2389 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw,
2390                    struct ieee80211_vif *vif)
2391 {
2392     struct ath_softc *sc = hw->priv;
2393     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2394     clear_bit(ATH_OP_SCANNING, &common->op_flags);
2395 }
2396
2397 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
2398
2399 static void ath9k_cancel_pending_offchannel(struct ath_softc *sc)
2400 {
2401     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2402
2403     if (sc->offchannel.roc_vif) {
2404         ath_dbg(common, CHAN_CTX,
2405             "%s: Aborting RoC\n", __func__);
2406
2407         del_timer_sync(&sc->offchannel.timer);
2408         if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2409             ath_roc_complete(sc, ATH_ROC_COMPLETE_ABORT);
2410     }
2411
2412     if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2413         ath_dbg(common, CHAN_CTX,
2414             "%s: Aborting HW scan\n", __func__);
2415
2416         del_timer_sync(&sc->offchannel.timer);
2417         ath_scan_complete(sc, true);
2418     }
2419 }
2420
2421 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2422              struct ieee80211_scan_request *hw_req)
2423 {
2424     struct cfg80211_scan_request *req = &hw_req->req;
2425     struct ath_softc *sc = hw->priv;
2426     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2427     int ret = 0;
2428
2429     mutex_lock(&sc->mutex);
2430
2431     if (WARN_ON(sc->offchannel.scan_req)) {
2432         ret = -EBUSY;
2433         goto out;
2434     }
2435
2436     ath9k_ps_wakeup(sc);
2437     set_bit(ATH_OP_SCANNING, &common->op_flags);
2438     sc->offchannel.scan_vif = vif;
2439     sc->offchannel.scan_req = req;
2440     sc->offchannel.scan_idx = 0;
2441
2442     ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
2443         vif->addr);
2444
2445     if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2446         ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
2447         ath_offchannel_next(sc);
2448     }
2449
2450 out:
2451     mutex_unlock(&sc->mutex);
2452
2453     return ret;
2454 }
2455
2456 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
2457                  struct ieee80211_vif *vif)
2458 {
2459     struct ath_softc *sc = hw->priv;
2460     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2461
2462     ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
2463
2464     mutex_lock(&sc->mutex);
2465     del_timer_sync(&sc->offchannel.timer);
2466     ath_scan_complete(sc, true);
2467     mutex_unlock(&sc->mutex);
2468 }
2469
2470 static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
2471                    struct ieee80211_vif *vif,
2472                    struct ieee80211_channel *chan, int duration,
2473                    enum ieee80211_roc_type type)
2474 {
2475     struct ath_softc *sc = hw->priv;
2476     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2477     int ret = 0;
2478
2479     mutex_lock(&sc->mutex);
2480
2481     if (WARN_ON(sc->offchannel.roc_vif)) {
2482         ret = -EBUSY;
2483         goto out;
2484     }
2485
2486     ath9k_ps_wakeup(sc);
2487     sc->offchannel.roc_vif = vif;
2488     sc->offchannel.roc_chan = chan;
2489     sc->offchannel.roc_duration = duration;
2490
2491     ath_dbg(common, CHAN_CTX,
2492         "RoC request on vif: %pM, type: %d duration: %d\n",
2493         vif->addr, type, duration);
2494
2495     if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2496         ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
2497         ath_offchannel_next(sc);
2498     }
2499
2500 out:
2501     mutex_unlock(&sc->mutex);
2502
2503     return ret;
2504 }
2505
2506 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw,
2507                       struct ieee80211_vif *vif)
2508 {
2509     struct ath_softc *sc = hw->priv;
2510     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2511
2512     mutex_lock(&sc->mutex);
2513
2514     ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
2515     del_timer_sync(&sc->offchannel.timer);
2516
2517     if (sc->offchannel.roc_vif) {
2518         if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2519             ath_roc_complete(sc, ATH_ROC_COMPLETE_CANCEL);
2520     }
2521
2522     mutex_unlock(&sc->mutex);
2523
2524     return 0;
2525 }
2526
2527 static int ath9k_add_chanctx(struct ieee80211_hw *hw,
2528                  struct ieee80211_chanctx_conf *conf)
2529 {
2530     struct ath_softc *sc = hw->priv;
2531     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2532     struct ath_chanctx *ctx, **ptr;
2533     int pos;
2534
2535     mutex_lock(&sc->mutex);
2536
2537     ath_for_each_chanctx(sc, ctx) {
2538         if (ctx->assigned)
2539             continue;
2540
2541         ptr = (void *) conf->drv_priv;
2542         *ptr = ctx;
2543         ctx->assigned = true;
2544         pos = ctx - &sc->chanctx[0];
2545         ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
2546
2547         ath_dbg(common, CHAN_CTX,
2548             "Add channel context: %d MHz\n",
2549             conf->def.chan->center_freq);
2550
2551         ath_chanctx_set_channel(sc, ctx, &conf->def);
2552
2553         mutex_unlock(&sc->mutex);
2554         return 0;
2555     }
2556
2557     mutex_unlock(&sc->mutex);
2558     return -ENOSPC;
2559 }
2560
2561
2562 static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
2563                  struct ieee80211_chanctx_conf *conf)
2564 {
2565     struct ath_softc *sc = hw->priv;
2566     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2567     struct ath_chanctx *ctx = ath_chanctx_get(conf);
2568
2569     mutex_lock(&sc->mutex);
2570
2571     ath_dbg(common, CHAN_CTX,
2572         "Remove channel context: %d MHz\n",
2573         conf->def.chan->center_freq);
2574
2575     ctx->assigned = false;
2576     ctx->hw_queue_base = 0;
2577     ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
2578
2579     mutex_unlock(&sc->mutex);
2580 }
2581
2582 static void ath9k_change_chanctx(struct ieee80211_hw *hw,
2583                  struct ieee80211_chanctx_conf *conf,
2584                  u32 changed)
2585 {
2586     struct ath_softc *sc = hw->priv;
2587     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2588     struct ath_chanctx *ctx = ath_chanctx_get(conf);
2589
2590     mutex_lock(&sc->mutex);
2591     ath_dbg(common, CHAN_CTX,
2592         "Change channel context: %d MHz\n",
2593         conf->def.chan->center_freq);
2594     ath_chanctx_set_channel(sc, ctx, &conf->def);
2595     mutex_unlock(&sc->mutex);
2596 }
2597
2598 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
2599                     struct ieee80211_vif *vif,
2600                     struct ieee80211_bss_conf *link_conf,
2601                     struct ieee80211_chanctx_conf *conf)
2602 {
2603     struct ath_softc *sc = hw->priv;
2604     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2605     struct ath_vif *avp = (void *)vif->drv_priv;
2606     struct ath_chanctx *ctx = ath_chanctx_get(conf);
2607     int i;
2608
2609     ath9k_cancel_pending_offchannel(sc);
2610
2611     mutex_lock(&sc->mutex);
2612
2613     ath_dbg(common, CHAN_CTX,
2614         "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
2615         vif->addr, vif->type, vif->p2p,
2616         conf->def.chan->center_freq);
2617
2618     avp->chanctx = ctx;
2619     ctx->nvifs_assigned++;
2620     list_add_tail(&avp->list, &ctx->vifs);
2621     ath9k_calculate_summary_state(sc, ctx);
2622     for (i = 0; i < IEEE80211_NUM_ACS; i++)
2623         vif->hw_queue[i] = ctx->hw_queue_base + i;
2624
2625     mutex_unlock(&sc->mutex);
2626
2627     return 0;
2628 }
2629
2630 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
2631                        struct ieee80211_vif *vif,
2632                        struct ieee80211_bss_conf *link_conf,
2633                        struct ieee80211_chanctx_conf *conf)
2634 {
2635     struct ath_softc *sc = hw->priv;
2636     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2637     struct ath_vif *avp = (void *)vif->drv_priv;
2638     struct ath_chanctx *ctx = ath_chanctx_get(conf);
2639     int ac;
2640
2641     ath9k_cancel_pending_offchannel(sc);
2642
2643     mutex_lock(&sc->mutex);
2644
2645     ath_dbg(common, CHAN_CTX,
2646         "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
2647         vif->addr, vif->type, vif->p2p,
2648         conf->def.chan->center_freq);
2649
2650     avp->chanctx = NULL;
2651     ctx->nvifs_assigned--;
2652     list_del(&avp->list);
2653     ath9k_calculate_summary_state(sc, ctx);
2654     for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2655         vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
2656
2657     mutex_unlock(&sc->mutex);
2658 }
2659
2660 static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
2661                  struct ieee80211_vif *vif,
2662                  struct ieee80211_prep_tx_info *info)
2663 {
2664     struct ath_softc *sc = hw->priv;
2665     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2666     struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
2667     struct ath_beacon_config *cur_conf;
2668     struct ath_chanctx *go_ctx;
2669     unsigned long timeout;
2670     bool changed = false;
2671     u32 beacon_int;
2672
2673     if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2674         return;
2675
2676     if (!avp->chanctx)
2677         return;
2678
2679     mutex_lock(&sc->mutex);
2680
2681     spin_lock_bh(&sc->chan_lock);
2682     if (sc->next_chan || (sc->cur_chan != avp->chanctx))
2683         changed = true;
2684     spin_unlock_bh(&sc->chan_lock);
2685
2686     if (!changed)
2687         goto out;
2688
2689     ath9k_cancel_pending_offchannel(sc);
2690
2691     go_ctx = ath_is_go_chanctx_present(sc);
2692
2693     if (go_ctx) {
2694         /*
2695          * Wait till the GO interface gets a chance
2696          * to send out an NoA.
2697          */
2698         spin_lock_bh(&sc->chan_lock);
2699         sc->sched.mgd_prepare_tx = true;
2700         cur_conf = &go_ctx->beacon;
2701         beacon_int = TU_TO_USEC(cur_conf->beacon_interval);
2702         spin_unlock_bh(&sc->chan_lock);
2703
2704         timeout = usecs_to_jiffies(beacon_int * 2);
2705         init_completion(&sc->go_beacon);
2706
2707         mutex_unlock(&sc->mutex);
2708
2709         if (wait_for_completion_timeout(&sc->go_beacon,
2710                         timeout) == 0) {
2711             ath_dbg(common, CHAN_CTX,
2712                 "Failed to send new NoA\n");
2713
2714             spin_lock_bh(&sc->chan_lock);
2715             sc->sched.mgd_prepare_tx = false;
2716             spin_unlock_bh(&sc->chan_lock);
2717         }
2718
2719         mutex_lock(&sc->mutex);
2720     }
2721
2722     ath_dbg(common, CHAN_CTX,
2723         "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n",
2724         __func__, vif->addr);
2725
2726     spin_lock_bh(&sc->chan_lock);
2727     sc->next_chan = avp->chanctx;
2728     sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
2729     spin_unlock_bh(&sc->chan_lock);
2730
2731     ath_chanctx_set_next(sc, true);
2732 out:
2733     mutex_unlock(&sc->mutex);
2734 }
2735
2736 void ath9k_fill_chanctx_ops(void)
2737 {
2738     if (!ath9k_is_chanctx_enabled())
2739         return;
2740
2741     ath9k_ops.hw_scan                  = ath9k_hw_scan;
2742     ath9k_ops.cancel_hw_scan           = ath9k_cancel_hw_scan;
2743     ath9k_ops.remain_on_channel        = ath9k_remain_on_channel;
2744     ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
2745     ath9k_ops.add_chanctx              = ath9k_add_chanctx;
2746     ath9k_ops.remove_chanctx           = ath9k_remove_chanctx;
2747     ath9k_ops.change_chanctx           = ath9k_change_chanctx;
2748     ath9k_ops.assign_vif_chanctx       = ath9k_assign_vif_chanctx;
2749     ath9k_ops.unassign_vif_chanctx     = ath9k_unassign_vif_chanctx;
2750     ath9k_ops.mgd_prepare_tx           = ath9k_mgd_prepare_tx;
2751 }
2752
2753 #endif
2754
2755 static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2756                  int *dbm)
2757 {
2758     struct ath_softc *sc = hw->priv;
2759     struct ath_vif *avp = (void *)vif->drv_priv;
2760
2761     mutex_lock(&sc->mutex);
2762     if (avp->chanctx)
2763         *dbm = avp->chanctx->cur_txpower;
2764     else
2765         *dbm = sc->cur_chan->cur_txpower;
2766     mutex_unlock(&sc->mutex);
2767
2768     *dbm /= 2;
2769
2770     return 0;
2771 }
2772
2773 struct ieee80211_ops ath9k_ops = {
2774     .tx             = ath9k_tx,
2775     .start          = ath9k_start,
2776     .stop           = ath9k_stop,
2777     .add_interface      = ath9k_add_interface,
2778     .change_interface   = ath9k_change_interface,
2779     .remove_interface   = ath9k_remove_interface,
2780     .config         = ath9k_config,
2781     .configure_filter   = ath9k_configure_filter,
2782     .sta_state          = ath9k_sta_state,
2783     .sta_notify         = ath9k_sta_notify,
2784     .conf_tx        = ath9k_conf_tx,
2785     .bss_info_changed   = ath9k_bss_info_changed,
2786     .set_key            = ath9k_set_key,
2787     .get_tsf        = ath9k_get_tsf,
2788     .set_tsf        = ath9k_set_tsf,
2789     .reset_tsf      = ath9k_reset_tsf,
2790     .ampdu_action       = ath9k_ampdu_action,
2791     .get_survey     = ath9k_get_survey,
2792     .rfkill_poll        = ath9k_rfkill_poll_state,
2793     .set_coverage_class = ath9k_set_coverage_class,
2794     .flush          = ath9k_flush,
2795     .tx_frames_pending  = ath9k_tx_frames_pending,
2796     .tx_last_beacon     = ath9k_tx_last_beacon,
2797     .release_buffered_frames = ath9k_release_buffered_frames,
2798     .get_stats      = ath9k_get_stats,
2799     .set_antenna        = ath9k_set_antenna,
2800     .get_antenna        = ath9k_get_antenna,
2801
2802 #ifdef CONFIG_ATH9K_WOW
2803     .suspend        = ath9k_suspend,
2804     .resume         = ath9k_resume,
2805     .set_wakeup     = ath9k_set_wakeup,
2806 #endif
2807
2808 #ifdef CONFIG_ATH9K_DEBUGFS
2809     .get_et_sset_count  = ath9k_get_et_sset_count,
2810     .get_et_stats       = ath9k_get_et_stats,
2811     .get_et_strings     = ath9k_get_et_strings,
2812 #endif
2813
2814 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
2815     .sta_add_debugfs    = ath9k_sta_add_debugfs,
2816 #endif
2817     .sw_scan_start      = ath9k_sw_scan_start,
2818     .sw_scan_complete   = ath9k_sw_scan_complete,
2819     .get_txpower        = ath9k_get_txpower,
2820     .wake_tx_queue      = ath9k_wake_tx_queue,
2821 };