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0001 /*
0002  * Copyright (c) 2008-2011 Atheros Communications Inc.
0003  *
0004  * Permission to use, copy, modify, and/or distribute this software for any
0005  * purpose with or without fee is hereby granted, provided that the above
0006  * copyright notice and this permission notice appear in all copies.
0007  *
0008  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0009  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0010  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0011  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0012  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0013  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0014  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0015  */
0016 
0017 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0018 
0019 #include <linux/dma-mapping.h>
0020 #include <linux/slab.h>
0021 #include <linux/ath9k_platform.h>
0022 #include <linux/module.h>
0023 #include <linux/of.h>
0024 #include <linux/of_net.h>
0025 #include <linux/nvmem-consumer.h>
0026 #include <linux/relay.h>
0027 #include <linux/dmi.h>
0028 #include <net/ieee80211_radiotap.h>
0029 
0030 #include "ath9k.h"
0031 
0032 struct ath9k_eeprom_ctx {
0033     struct completion complete;
0034     struct ath_hw *ah;
0035 };
0036 
0037 static char *dev_info = "ath9k";
0038 
0039 MODULE_AUTHOR("Atheros Communications");
0040 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
0041 MODULE_LICENSE("Dual BSD/GPL");
0042 
0043 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
0044 module_param_named(debug, ath9k_debug, uint, 0);
0045 MODULE_PARM_DESC(debug, "Debugging mask");
0046 
0047 int ath9k_modparam_nohwcrypt;
0048 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
0049 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
0050 
0051 int ath9k_led_blink;
0052 module_param_named(blink, ath9k_led_blink, int, 0444);
0053 MODULE_PARM_DESC(blink, "Enable LED blink on activity");
0054 
0055 static int ath9k_led_active_high = -1;
0056 module_param_named(led_active_high, ath9k_led_active_high, int, 0444);
0057 MODULE_PARM_DESC(led_active_high, "Invert LED polarity");
0058 
0059 static int ath9k_btcoex_enable;
0060 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
0061 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
0062 
0063 static int ath9k_bt_ant_diversity;
0064 module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444);
0065 MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity");
0066 
0067 static int ath9k_ps_enable;
0068 module_param_named(ps_enable, ath9k_ps_enable, int, 0444);
0069 MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave");
0070 
0071 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
0072 
0073 int ath9k_use_chanctx;
0074 module_param_named(use_chanctx, ath9k_use_chanctx, int, 0444);
0075 MODULE_PARM_DESC(use_chanctx, "Enable channel context for concurrency");
0076 
0077 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
0078 
0079 int ath9k_use_msi;
0080 module_param_named(use_msi, ath9k_use_msi, int, 0444);
0081 MODULE_PARM_DESC(use_msi, "Use MSI instead of INTx if possible");
0082 
0083 bool is_ath9k_unloaded;
0084 
0085 #ifdef CONFIG_MAC80211_LEDS
0086 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
0087     { .throughput = 0 * 1024, .blink_time = 334 },
0088     { .throughput = 1 * 1024, .blink_time = 260 },
0089     { .throughput = 5 * 1024, .blink_time = 220 },
0090     { .throughput = 10 * 1024, .blink_time = 190 },
0091     { .throughput = 20 * 1024, .blink_time = 170 },
0092     { .throughput = 50 * 1024, .blink_time = 150 },
0093     { .throughput = 70 * 1024, .blink_time = 130 },
0094     { .throughput = 100 * 1024, .blink_time = 110 },
0095     { .throughput = 200 * 1024, .blink_time = 80 },
0096     { .throughput = 300 * 1024, .blink_time = 50 },
0097 };
0098 #endif
0099 
0100 static int __init set_use_msi(const struct dmi_system_id *dmi)
0101 {
0102     ath9k_use_msi = 1;
0103     return 1;
0104 }
0105 
0106 static const struct dmi_system_id ath9k_quirks[] __initconst = {
0107     {
0108         .callback = set_use_msi,
0109         .ident = "Dell Inspiron 24-3460",
0110         .matches = {
0111             DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
0112             DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 24-3460"),
0113         },
0114     },
0115     {
0116         .callback = set_use_msi,
0117         .ident = "Dell Vostro 3262",
0118         .matches = {
0119             DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
0120             DMI_MATCH(DMI_PRODUCT_NAME, "Vostro 3262"),
0121         },
0122     },
0123     {
0124         .callback = set_use_msi,
0125         .ident = "Dell Inspiron 3472",
0126         .matches = {
0127             DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
0128             DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 3472"),
0129         },
0130     },
0131     {
0132         .callback = set_use_msi,
0133         .ident = "Dell Vostro 15-3572",
0134         .matches = {
0135             DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
0136             DMI_MATCH(DMI_PRODUCT_NAME, "Vostro 15-3572"),
0137         },
0138     },
0139     {
0140         .callback = set_use_msi,
0141         .ident = "Dell Inspiron 14-3473",
0142         .matches = {
0143             DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
0144             DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 14-3473"),
0145         },
0146     },
0147     {}
0148 };
0149 
0150 static void ath9k_deinit_softc(struct ath_softc *sc);
0151 
0152 static void ath9k_op_ps_wakeup(struct ath_common *common)
0153 {
0154     ath9k_ps_wakeup((struct ath_softc *) common->priv);
0155 }
0156 
0157 static void ath9k_op_ps_restore(struct ath_common *common)
0158 {
0159     ath9k_ps_restore((struct ath_softc *) common->priv);
0160 }
0161 
0162 static const struct ath_ps_ops ath9k_ps_ops = {
0163     .wakeup = ath9k_op_ps_wakeup,
0164     .restore = ath9k_op_ps_restore,
0165 };
0166 
0167 /*
0168  * Read and write, they both share the same lock. We do this to serialize
0169  * reads and writes on Atheros 802.11n PCI devices only. This is required
0170  * as the FIFO on these devices can only accept sanely 2 requests.
0171  */
0172 
0173 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
0174 {
0175     struct ath_hw *ah = hw_priv;
0176     struct ath_common *common = ath9k_hw_common(ah);
0177     struct ath_softc *sc = (struct ath_softc *) common->priv;
0178 
0179     if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
0180         unsigned long flags;
0181         spin_lock_irqsave(&sc->sc_serial_rw, flags);
0182         iowrite32(val, sc->mem + reg_offset);
0183         spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
0184     } else
0185         iowrite32(val, sc->mem + reg_offset);
0186 }
0187 
0188 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
0189 {
0190     struct ath_hw *ah = hw_priv;
0191     struct ath_common *common = ath9k_hw_common(ah);
0192     struct ath_softc *sc = (struct ath_softc *) common->priv;
0193     u32 val;
0194 
0195     if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
0196         unsigned long flags;
0197         spin_lock_irqsave(&sc->sc_serial_rw, flags);
0198         val = ioread32(sc->mem + reg_offset);
0199         spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
0200     } else
0201         val = ioread32(sc->mem + reg_offset);
0202     return val;
0203 }
0204 
0205 static void ath9k_multi_ioread32(void *hw_priv, u32 *addr,
0206                                 u32 *val, u16 count)
0207 {
0208     int i;
0209 
0210     for (i = 0; i < count; i++)
0211         val[i] = ath9k_ioread32(hw_priv, addr[i]);
0212 }
0213 
0214 
0215 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,
0216                     u32 set, u32 clr)
0217 {
0218     u32 val;
0219 
0220     val = ioread32(sc->mem + reg_offset);
0221     val &= ~clr;
0222     val |= set;
0223     iowrite32(val, sc->mem + reg_offset);
0224 
0225     return val;
0226 }
0227 
0228 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
0229 {
0230     struct ath_hw *ah = hw_priv;
0231     struct ath_common *common = ath9k_hw_common(ah);
0232     struct ath_softc *sc = (struct ath_softc *) common->priv;
0233     unsigned long flags;
0234     u32 val;
0235 
0236     if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
0237         spin_lock_irqsave(&sc->sc_serial_rw, flags);
0238         val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
0239         spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
0240     } else
0241         val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
0242 
0243     return val;
0244 }
0245 
0246 /**************************/
0247 /*     Initialization     */
0248 /**************************/
0249 
0250 static void ath9k_reg_notifier(struct wiphy *wiphy,
0251                    struct regulatory_request *request)
0252 {
0253     struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
0254     struct ath_softc *sc = hw->priv;
0255     struct ath_hw *ah = sc->sc_ah;
0256     struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
0257 
0258     ath_reg_notifier_apply(wiphy, request, reg);
0259 
0260     /* synchronize DFS detector if regulatory domain changed */
0261     if (sc->dfs_detector != NULL)
0262         sc->dfs_detector->set_dfs_domain(sc->dfs_detector,
0263                          request->dfs_region);
0264 
0265     /* Set tx power */
0266     if (!ah->curchan)
0267         return;
0268 
0269     sc->cur_chan->txpower = 2 * ah->curchan->chan->max_power;
0270     ath9k_ps_wakeup(sc);
0271     ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
0272     ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
0273                    sc->cur_chan->txpower,
0274                    &sc->cur_chan->cur_txpower);
0275     ath9k_ps_restore(sc);
0276 }
0277 
0278 /*
0279  *  This function will allocate both the DMA descriptor structure, and the
0280  *  buffers it contains.  These are used to contain the descriptors used
0281  *  by the system.
0282 */
0283 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
0284               struct list_head *head, const char *name,
0285               int nbuf, int ndesc, bool is_tx)
0286 {
0287     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
0288     u8 *ds;
0289     int i, bsize, desc_len;
0290 
0291     ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n",
0292         name, nbuf, ndesc);
0293 
0294     INIT_LIST_HEAD(head);
0295 
0296     if (is_tx)
0297         desc_len = sc->sc_ah->caps.tx_desc_len;
0298     else
0299         desc_len = sizeof(struct ath_desc);
0300 
0301     /* ath_desc must be a multiple of DWORDs */
0302     if ((desc_len % 4) != 0) {
0303         ath_err(common, "ath_desc not DWORD aligned\n");
0304         BUG_ON((desc_len % 4) != 0);
0305         return -ENOMEM;
0306     }
0307 
0308     dd->dd_desc_len = desc_len * nbuf * ndesc;
0309 
0310     /*
0311      * Need additional DMA memory because we can't use
0312      * descriptors that cross the 4K page boundary. Assume
0313      * one skipped descriptor per 4K page.
0314      */
0315     if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
0316         u32 ndesc_skipped =
0317             ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
0318         u32 dma_len;
0319 
0320         while (ndesc_skipped) {
0321             dma_len = ndesc_skipped * desc_len;
0322             dd->dd_desc_len += dma_len;
0323 
0324             ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
0325         }
0326     }
0327 
0328     /* allocate descriptors */
0329     dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
0330                       &dd->dd_desc_paddr, GFP_KERNEL);
0331     if (!dd->dd_desc)
0332         return -ENOMEM;
0333 
0334     ds = dd->dd_desc;
0335     ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
0336         name, ds, (u32) dd->dd_desc_len,
0337         ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
0338 
0339     /* allocate buffers */
0340     if (is_tx) {
0341         struct ath_buf *bf;
0342 
0343         bsize = sizeof(struct ath_buf) * nbuf;
0344         bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
0345         if (!bf)
0346             return -ENOMEM;
0347 
0348         for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
0349             bf->bf_desc = ds;
0350             bf->bf_daddr = DS2PHYS(dd, ds);
0351 
0352             if (!(sc->sc_ah->caps.hw_caps &
0353                   ATH9K_HW_CAP_4KB_SPLITTRANS)) {
0354                 /*
0355                  * Skip descriptor addresses which can cause 4KB
0356                  * boundary crossing (addr + length) with a 32 dword
0357                  * descriptor fetch.
0358                  */
0359                 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
0360                     BUG_ON((caddr_t) bf->bf_desc >=
0361                            ((caddr_t) dd->dd_desc +
0362                         dd->dd_desc_len));
0363 
0364                     ds += (desc_len * ndesc);
0365                     bf->bf_desc = ds;
0366                     bf->bf_daddr = DS2PHYS(dd, ds);
0367                 }
0368             }
0369             list_add_tail(&bf->list, head);
0370         }
0371     } else {
0372         struct ath_rxbuf *bf;
0373 
0374         bsize = sizeof(struct ath_rxbuf) * nbuf;
0375         bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
0376         if (!bf)
0377             return -ENOMEM;
0378 
0379         for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
0380             bf->bf_desc = ds;
0381             bf->bf_daddr = DS2PHYS(dd, ds);
0382 
0383             if (!(sc->sc_ah->caps.hw_caps &
0384                   ATH9K_HW_CAP_4KB_SPLITTRANS)) {
0385                 /*
0386                  * Skip descriptor addresses which can cause 4KB
0387                  * boundary crossing (addr + length) with a 32 dword
0388                  * descriptor fetch.
0389                  */
0390                 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
0391                     BUG_ON((caddr_t) bf->bf_desc >=
0392                            ((caddr_t) dd->dd_desc +
0393                         dd->dd_desc_len));
0394 
0395                     ds += (desc_len * ndesc);
0396                     bf->bf_desc = ds;
0397                     bf->bf_daddr = DS2PHYS(dd, ds);
0398                 }
0399             }
0400             list_add_tail(&bf->list, head);
0401         }
0402     }
0403     return 0;
0404 }
0405 
0406 static int ath9k_init_queues(struct ath_softc *sc)
0407 {
0408     int i = 0;
0409 
0410     sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
0411     sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
0412     ath_cabq_update(sc);
0413 
0414     sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0);
0415 
0416     for (i = 0; i < IEEE80211_NUM_ACS; i++) {
0417         sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
0418         sc->tx.txq_map[i]->mac80211_qnum = i;
0419     }
0420     return 0;
0421 }
0422 
0423 static void ath9k_init_misc(struct ath_softc *sc)
0424 {
0425     struct ath_common *common = ath9k_hw_common(sc->sc_ah);
0426     int i = 0;
0427 
0428     timer_setup(&common->ani.timer, ath_ani_calibrate, 0);
0429 
0430     common->last_rssi = ATH_RSSI_DUMMY_MARKER;
0431     eth_broadcast_addr(common->bssidmask);
0432     sc->beacon.slottime = 9;
0433 
0434     for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
0435         sc->beacon.bslot[i] = NULL;
0436 
0437     if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
0438         sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
0439 
0440     sc->spec_priv.ah = sc->sc_ah;
0441     sc->spec_priv.spec_config.enabled = 0;
0442     sc->spec_priv.spec_config.short_repeat = true;
0443     sc->spec_priv.spec_config.count = 8;
0444     sc->spec_priv.spec_config.endless = false;
0445     sc->spec_priv.spec_config.period = 0xFF;
0446     sc->spec_priv.spec_config.fft_period = 0xF;
0447 }
0448 
0449 static void ath9k_init_pcoem_platform(struct ath_softc *sc)
0450 {
0451     struct ath_hw *ah = sc->sc_ah;
0452     struct ath9k_hw_capabilities *pCap = &ah->caps;
0453     struct ath_common *common = ath9k_hw_common(ah);
0454 
0455     if (!IS_ENABLED(CONFIG_ATH9K_PCOEM))
0456         return;
0457 
0458     if (common->bus_ops->ath_bus_type != ATH_PCI)
0459         return;
0460 
0461     if (sc->driver_data & (ATH9K_PCI_CUS198 |
0462                    ATH9K_PCI_CUS230)) {
0463         ah->config.xlna_gpio = 9;
0464         ah->config.xatten_margin_cfg = true;
0465         ah->config.alt_mingainidx = true;
0466         ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88;
0467         sc->ant_comb.low_rssi_thresh = 20;
0468         sc->ant_comb.fast_div_bias = 3;
0469 
0470         ath_info(common, "Set parameters for %s\n",
0471              (sc->driver_data & ATH9K_PCI_CUS198) ?
0472              "CUS198" : "CUS230");
0473     }
0474 
0475     if (sc->driver_data & ATH9K_PCI_CUS217)
0476         ath_info(common, "CUS217 card detected\n");
0477 
0478     if (sc->driver_data & ATH9K_PCI_CUS252)
0479         ath_info(common, "CUS252 card detected\n");
0480 
0481     if (sc->driver_data & ATH9K_PCI_AR9565_1ANT)
0482         ath_info(common, "WB335 1-ANT card detected\n");
0483 
0484     if (sc->driver_data & ATH9K_PCI_AR9565_2ANT)
0485         ath_info(common, "WB335 2-ANT card detected\n");
0486 
0487     if (sc->driver_data & ATH9K_PCI_KILLER)
0488         ath_info(common, "Killer Wireless card detected\n");
0489 
0490     /*
0491      * Some WB335 cards do not support antenna diversity. Since
0492      * we use a hardcoded value for AR9565 instead of using the
0493      * EEPROM/OTP data, remove the combining feature from
0494      * the HW capabilities bitmap.
0495      */
0496     if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) {
0497         if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV))
0498             pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB;
0499     }
0500 
0501     if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) {
0502         pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV;
0503         ath_info(common, "Set BT/WLAN RX diversity capability\n");
0504     }
0505 
0506     if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) {
0507         ah->config.pcie_waen = 0x0040473b;
0508         ath_info(common, "Enable WAR for ASPM D3/L1\n");
0509     }
0510 
0511     /*
0512      * The default value of pll_pwrsave is 1.
0513      * For certain AR9485 cards, it is set to 0.
0514      * For AR9462, AR9565 it's set to 7.
0515      */
0516     ah->config.pll_pwrsave = 1;
0517 
0518     if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
0519         ah->config.pll_pwrsave = 0;
0520         ath_info(common, "Disable PLL PowerSave\n");
0521     }
0522 
0523     if (sc->driver_data & ATH9K_PCI_LED_ACT_HI)
0524         ah->config.led_active_high = true;
0525 }
0526 
0527 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
0528                     void *ctx)
0529 {
0530     struct ath9k_eeprom_ctx *ec = ctx;
0531 
0532     if (eeprom_blob)
0533         ec->ah->eeprom_blob = eeprom_blob;
0534 
0535     complete(&ec->complete);
0536 }
0537 
0538 static int ath9k_eeprom_request(struct ath_softc *sc, const char *name)
0539 {
0540     struct ath9k_eeprom_ctx ec;
0541     struct ath_hw *ah = sc->sc_ah;
0542     int err;
0543 
0544     /* try to load the EEPROM content asynchronously */
0545     init_completion(&ec.complete);
0546     ec.ah = sc->sc_ah;
0547 
0548     err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL,
0549                       &ec, ath9k_eeprom_request_cb);
0550     if (err < 0) {
0551         ath_err(ath9k_hw_common(ah),
0552             "EEPROM request failed\n");
0553         return err;
0554     }
0555 
0556     wait_for_completion(&ec.complete);
0557 
0558     if (!ah->eeprom_blob) {
0559         ath_err(ath9k_hw_common(ah),
0560             "Unable to load EEPROM file %s\n", name);
0561         return -EINVAL;
0562     }
0563 
0564     return 0;
0565 }
0566 
0567 static void ath9k_eeprom_release(struct ath_softc *sc)
0568 {
0569     release_firmware(sc->sc_ah->eeprom_blob);
0570 }
0571 
0572 static int ath9k_nvmem_request_eeprom(struct ath_softc *sc)
0573 {
0574     struct ath_hw *ah = sc->sc_ah;
0575     struct nvmem_cell *cell;
0576     void *buf;
0577     size_t len;
0578     int err;
0579 
0580     cell = devm_nvmem_cell_get(sc->dev, "calibration");
0581     if (IS_ERR(cell)) {
0582         err = PTR_ERR(cell);
0583 
0584         /* nvmem cell might not be defined, or the nvmem
0585          * subsystem isn't included. In this case, follow
0586          * the established "just return 0;" convention of
0587          * ath9k_init_platform to say:
0588          * "All good. Nothing to see here. Please go on."
0589          */
0590         if (err == -ENOENT || err == -EOPNOTSUPP)
0591             return 0;
0592 
0593         return err;
0594     }
0595 
0596     buf = nvmem_cell_read(cell, &len);
0597     if (IS_ERR(buf))
0598         return PTR_ERR(buf);
0599 
0600     /* run basic sanity checks on the returned nvram cell length.
0601      * That length has to be a multiple of a "u16" (i.e.: & 1).
0602      * Furthermore, it has to be more than "let's say" 512 bytes
0603      * but less than the maximum of AR9300_EEPROM_SIZE (16kb).
0604      */
0605     if ((len & 1) == 1 || len < 512 || len >= AR9300_EEPROM_SIZE) {
0606         kfree(buf);
0607         return -EINVAL;
0608     }
0609 
0610     /* devres manages the calibration values release on shutdown */
0611     ah->nvmem_blob = (u16 *)devm_kmemdup(sc->dev, buf, len, GFP_KERNEL);
0612     kfree(buf);
0613     if (!ah->nvmem_blob)
0614         return -ENOMEM;
0615 
0616     ah->nvmem_blob_len = len;
0617     ah->ah_flags &= ~AH_USE_EEPROM;
0618     ah->ah_flags |= AH_NO_EEP_SWAP;
0619 
0620     return 0;
0621 }
0622 
0623 static int ath9k_init_platform(struct ath_softc *sc)
0624 {
0625     struct ath9k_platform_data *pdata = sc->dev->platform_data;
0626     struct ath_hw *ah = sc->sc_ah;
0627     struct ath_common *common = ath9k_hw_common(ah);
0628     int ret;
0629 
0630     if (!pdata)
0631         return 0;
0632 
0633     if (!pdata->use_eeprom) {
0634         ah->ah_flags &= ~AH_USE_EEPROM;
0635         ah->gpio_mask = pdata->gpio_mask;
0636         ah->gpio_val = pdata->gpio_val;
0637         ah->led_pin = pdata->led_pin;
0638         ah->is_clk_25mhz = pdata->is_clk_25mhz;
0639         ah->get_mac_revision = pdata->get_mac_revision;
0640         ah->external_reset = pdata->external_reset;
0641         ah->disable_2ghz = pdata->disable_2ghz;
0642         ah->disable_5ghz = pdata->disable_5ghz;
0643 
0644         if (!pdata->endian_check)
0645             ah->ah_flags |= AH_NO_EEP_SWAP;
0646     }
0647 
0648     if (pdata->eeprom_name) {
0649         ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
0650         if (ret)
0651             return ret;
0652     }
0653 
0654     if (pdata->led_active_high)
0655         ah->config.led_active_high = true;
0656 
0657     if (pdata->tx_gain_buffalo)
0658         ah->config.tx_gain_buffalo = true;
0659 
0660     if (pdata->macaddr)
0661         ether_addr_copy(common->macaddr, pdata->macaddr);
0662 
0663     return 0;
0664 }
0665 
0666 static int ath9k_of_init(struct ath_softc *sc)
0667 {
0668     struct device_node *np = sc->dev->of_node;
0669     struct ath_hw *ah = sc->sc_ah;
0670     struct ath_common *common = ath9k_hw_common(ah);
0671     enum ath_bus_type bus_type = common->bus_ops->ath_bus_type;
0672     char eeprom_name[100];
0673     int ret;
0674 
0675     if (!of_device_is_available(np))
0676         return 0;
0677 
0678     ath_dbg(common, CONFIG, "parsing configuration from OF node\n");
0679 
0680     if (of_property_read_bool(np, "qca,no-eeprom")) {
0681         /* ath9k-eeprom-<bus>-<id>.bin */
0682         scnprintf(eeprom_name, sizeof(eeprom_name),
0683               "ath9k-eeprom-%s-%s.bin",
0684               ath_bus_type_to_string(bus_type), dev_name(ah->dev));
0685 
0686         ret = ath9k_eeprom_request(sc, eeprom_name);
0687         if (ret)
0688             return ret;
0689 
0690         ah->ah_flags &= ~AH_USE_EEPROM;
0691         ah->ah_flags |= AH_NO_EEP_SWAP;
0692     }
0693 
0694     of_get_mac_address(np, common->macaddr);
0695 
0696     return 0;
0697 }
0698 
0699 static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
0700                 const struct ath_bus_ops *bus_ops)
0701 {
0702     struct ath_hw *ah = NULL;
0703     struct ath9k_hw_capabilities *pCap;
0704     struct ath_common *common;
0705     int ret = 0, i;
0706     int csz = 0;
0707 
0708     ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL);
0709     if (!ah)
0710         return -ENOMEM;
0711 
0712     ah->dev = sc->dev;
0713     ah->hw = sc->hw;
0714     ah->hw_version.devid = devid;
0715     ah->ah_flags |= AH_USE_EEPROM;
0716     ah->led_pin = -1;
0717     ah->reg_ops.read = ath9k_ioread32;
0718     ah->reg_ops.multi_read = ath9k_multi_ioread32;
0719     ah->reg_ops.write = ath9k_iowrite32;
0720     ah->reg_ops.rmw = ath9k_reg_rmw;
0721     pCap = &ah->caps;
0722 
0723     common = ath9k_hw_common(ah);
0724 
0725     /* Will be cleared in ath9k_start() */
0726     set_bit(ATH_OP_INVALID, &common->op_flags);
0727 
0728     sc->sc_ah = ah;
0729     sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET);
0730     sc->tx99_power = MAX_RATE_POWER + 1;
0731     init_waitqueue_head(&sc->tx_wait);
0732     sc->cur_chan = &sc->chanctx[0];
0733     if (!ath9k_is_chanctx_enabled())
0734         sc->cur_chan->hw_queue_base = 0;
0735 
0736     common->ops = &ah->reg_ops;
0737     common->bus_ops = bus_ops;
0738     common->ps_ops = &ath9k_ps_ops;
0739     common->ah = ah;
0740     common->hw = sc->hw;
0741     common->priv = sc;
0742     common->debug_mask = ath9k_debug;
0743     common->btcoex_enabled = ath9k_btcoex_enable == 1;
0744     common->disable_ani = false;
0745 
0746     /*
0747      * Platform quirks.
0748      */
0749     ath9k_init_pcoem_platform(sc);
0750 
0751     ret = ath9k_init_platform(sc);
0752     if (ret)
0753         return ret;
0754 
0755     ret = ath9k_of_init(sc);
0756     if (ret)
0757         return ret;
0758 
0759     ret = ath9k_nvmem_request_eeprom(sc);
0760     if (ret)
0761         return ret;
0762 
0763     if (ath9k_led_active_high != -1)
0764         ah->config.led_active_high = ath9k_led_active_high == 1;
0765 
0766     /*
0767      * Enable WLAN/BT RX Antenna diversity only when:
0768      *
0769      * - BTCOEX is disabled.
0770      * - the user manually requests the feature.
0771      * - the HW cap is set using the platform data.
0772      */
0773     if (!common->btcoex_enabled && ath9k_bt_ant_diversity &&
0774         (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV))
0775         common->bt_ant_diversity = 1;
0776 
0777     spin_lock_init(&common->cc_lock);
0778     spin_lock_init(&sc->intr_lock);
0779     spin_lock_init(&sc->sc_serial_rw);
0780     spin_lock_init(&sc->sc_pm_lock);
0781     spin_lock_init(&sc->chan_lock);
0782     mutex_init(&sc->mutex);
0783     tasklet_setup(&sc->intr_tq, ath9k_tasklet);
0784     tasklet_setup(&sc->bcon_tasklet, ath9k_beacon_tasklet);
0785 
0786     timer_setup(&sc->sleep_timer, ath_ps_full_sleep, 0);
0787     INIT_WORK(&sc->hw_reset_work, ath_reset_work);
0788     INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
0789     INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
0790     INIT_DELAYED_WORK(&sc->hw_check_work, ath_hw_check_work);
0791 
0792     ath9k_init_channel_context(sc);
0793 
0794     /*
0795      * Cache line size is used to size and align various
0796      * structures used to communicate with the hardware.
0797      */
0798     ath_read_cachesize(common, &csz);
0799     common->cachelsz = csz << 2; /* convert to bytes */
0800 
0801     /* Initializes the hardware for all supported chipsets */
0802     ret = ath9k_hw_init(ah);
0803     if (ret)
0804         goto err_hw;
0805 
0806     ret = ath9k_init_queues(sc);
0807     if (ret)
0808         goto err_queues;
0809 
0810     ret =  ath9k_init_btcoex(sc);
0811     if (ret)
0812         goto err_btcoex;
0813 
0814     ret = ath9k_cmn_init_channels_rates(common);
0815     if (ret)
0816         goto err_btcoex;
0817 
0818     ret = ath9k_init_p2p(sc);
0819     if (ret)
0820         goto err_btcoex;
0821 
0822     ath9k_cmn_init_crypto(sc->sc_ah);
0823     ath9k_init_misc(sc);
0824     ath_chanctx_init(sc);
0825     ath9k_offchannel_init(sc);
0826 
0827     if (common->bus_ops->aspm_init)
0828         common->bus_ops->aspm_init(common);
0829 
0830     return 0;
0831 
0832 err_btcoex:
0833     for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
0834         if (ATH_TXQ_SETUP(sc, i))
0835             ath_tx_cleanupq(sc, &sc->tx.txq[i]);
0836 err_queues:
0837     ath9k_hw_deinit(ah);
0838 err_hw:
0839     ath9k_eeprom_release(sc);
0840     dev_kfree_skb_any(sc->tx99_skb);
0841     return ret;
0842 }
0843 
0844 static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
0845 {
0846     struct ieee80211_supported_band *sband;
0847     struct ieee80211_channel *chan;
0848     struct ath_hw *ah = sc->sc_ah;
0849     struct ath_common *common = ath9k_hw_common(ah);
0850     struct cfg80211_chan_def chandef;
0851     int i;
0852 
0853     sband = &common->sbands[band];
0854     for (i = 0; i < sband->n_channels; i++) {
0855         chan = &sband->channels[i];
0856         ah->curchan = &ah->channels[chan->hw_value];
0857         cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20);
0858         ath9k_cmn_get_channel(sc->hw, ah, &chandef);
0859         ath9k_hw_set_txpowerlimit(ah, MAX_COMBINED_POWER, true);
0860     }
0861 }
0862 
0863 static void ath9k_init_txpower_limits(struct ath_softc *sc)
0864 {
0865     struct ath_hw *ah = sc->sc_ah;
0866     struct ath9k_channel *curchan = ah->curchan;
0867 
0868     if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
0869         ath9k_init_band_txpower(sc, NL80211_BAND_2GHZ);
0870     if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
0871         ath9k_init_band_txpower(sc, NL80211_BAND_5GHZ);
0872 
0873     ah->curchan = curchan;
0874 }
0875 
0876 static const struct ieee80211_iface_limit if_limits[] = {
0877     { .max = 2048,  .types = BIT(NL80211_IFTYPE_STATION) },
0878     { .max = 8, .types =
0879 #ifdef CONFIG_MAC80211_MESH
0880                  BIT(NL80211_IFTYPE_MESH_POINT) |
0881 #endif
0882                  BIT(NL80211_IFTYPE_AP) },
0883     { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
0884                  BIT(NL80211_IFTYPE_P2P_GO) },
0885 };
0886 
0887 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
0888 
0889 static const struct ieee80211_iface_limit if_limits_multi[] = {
0890     { .max = 2, .types = BIT(NL80211_IFTYPE_STATION) |
0891                  BIT(NL80211_IFTYPE_AP) |
0892                  BIT(NL80211_IFTYPE_P2P_CLIENT) |
0893                  BIT(NL80211_IFTYPE_P2P_GO) },
0894     { .max = 1, .types = BIT(NL80211_IFTYPE_ADHOC) },
0895     { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_DEVICE) },
0896 };
0897 
0898 static const struct ieee80211_iface_combination if_comb_multi[] = {
0899     {
0900         .limits = if_limits_multi,
0901         .n_limits = ARRAY_SIZE(if_limits_multi),
0902         .max_interfaces = 3,
0903         .num_different_channels = 2,
0904         .beacon_int_infra_match = true,
0905     },
0906 };
0907 
0908 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
0909 
0910 static const struct ieee80211_iface_combination if_comb[] = {
0911     {
0912         .limits = if_limits,
0913         .n_limits = ARRAY_SIZE(if_limits),
0914         .max_interfaces = 2048,
0915         .num_different_channels = 1,
0916         .beacon_int_infra_match = true,
0917 #ifdef CONFIG_ATH9K_DFS_CERTIFIED
0918         .radar_detect_widths =  BIT(NL80211_CHAN_WIDTH_20_NOHT) |
0919                     BIT(NL80211_CHAN_WIDTH_20) |
0920                     BIT(NL80211_CHAN_WIDTH_40),
0921 #endif
0922     },
0923 };
0924 
0925 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
0926 static void ath9k_set_mcc_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
0927 {
0928     struct ath_hw *ah = sc->sc_ah;
0929     struct ath_common *common = ath9k_hw_common(ah);
0930 
0931     if (!ath9k_is_chanctx_enabled())
0932         return;
0933 
0934     ieee80211_hw_set(hw, QUEUE_CONTROL);
0935     hw->queues = ATH9K_NUM_TX_QUEUES;
0936     hw->offchannel_tx_hw_queue = hw->queues - 1;
0937     hw->wiphy->iface_combinations = if_comb_multi;
0938     hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb_multi);
0939     hw->wiphy->max_scan_ssids = 255;
0940     hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
0941     hw->wiphy->max_remain_on_channel_duration = 10000;
0942     hw->chanctx_data_size = sizeof(void *);
0943     hw->extra_beacon_tailroom =
0944         sizeof(struct ieee80211_p2p_noa_attr) + 9;
0945 
0946     ath_dbg(common, CHAN_CTX, "Use channel contexts\n");
0947 }
0948 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
0949 
0950 static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
0951 {
0952     struct ath_hw *ah = sc->sc_ah;
0953     struct ath_common *common = ath9k_hw_common(ah);
0954 
0955     ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES);
0956     ieee80211_hw_set(hw, SUPPORTS_RC_TABLE);
0957     ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
0958     ieee80211_hw_set(hw, SPECTRUM_MGMT);
0959     ieee80211_hw_set(hw, PS_NULLFUNC_STACK);
0960     ieee80211_hw_set(hw, SIGNAL_DBM);
0961     ieee80211_hw_set(hw, RX_INCLUDES_FCS);
0962     ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING);
0963     ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
0964     ieee80211_hw_set(hw, SUPPORTS_CLONED_SKBS);
0965 
0966     if (ath9k_ps_enable)
0967         ieee80211_hw_set(hw, SUPPORTS_PS);
0968 
0969     if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
0970         ieee80211_hw_set(hw, AMPDU_AGGREGATION);
0971 
0972         if (AR_SREV_9280_20_OR_LATER(ah))
0973             hw->radiotap_mcs_details |=
0974                 IEEE80211_RADIOTAP_MCS_HAVE_STBC;
0975     }
0976 
0977     if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
0978         ieee80211_hw_set(hw, MFP_CAPABLE);
0979 
0980     hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR |
0981                    NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE |
0982                    NL80211_FEATURE_P2P_GO_CTWIN;
0983 
0984     if (!IS_ENABLED(CONFIG_ATH9K_TX99)) {
0985         hw->wiphy->interface_modes =
0986             BIT(NL80211_IFTYPE_P2P_GO) |
0987             BIT(NL80211_IFTYPE_P2P_CLIENT) |
0988             BIT(NL80211_IFTYPE_AP) |
0989             BIT(NL80211_IFTYPE_STATION) |
0990             BIT(NL80211_IFTYPE_ADHOC) |
0991             BIT(NL80211_IFTYPE_MESH_POINT) |
0992             BIT(NL80211_IFTYPE_OCB);
0993 
0994         if (ath9k_is_chanctx_enabled())
0995             hw->wiphy->interface_modes |=
0996                     BIT(NL80211_IFTYPE_P2P_DEVICE);
0997 
0998         hw->wiphy->iface_combinations = if_comb;
0999         hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
1000     }
1001 
1002     hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
1003 
1004     hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
1005     hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
1006     hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
1007     hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
1008     hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
1009     hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD;
1010 
1011     hw->queues = 4;
1012     hw->max_rates = 4;
1013     hw->max_listen_interval = 10;
1014     hw->max_rate_tries = 10;
1015     hw->sta_data_size = sizeof(struct ath_node);
1016     hw->vif_data_size = sizeof(struct ath_vif);
1017     hw->txq_data_size = sizeof(struct ath_atx_tid);
1018     hw->extra_tx_headroom = 4;
1019 
1020     hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1;
1021     hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1;
1022 
1023     /* single chain devices with rx diversity */
1024     if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
1025         hw->wiphy->available_antennas_rx = BIT(0) | BIT(1);
1026 
1027     sc->ant_rx = hw->wiphy->available_antennas_rx;
1028     sc->ant_tx = hw->wiphy->available_antennas_tx;
1029 
1030     if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
1031         hw->wiphy->bands[NL80211_BAND_2GHZ] =
1032             &common->sbands[NL80211_BAND_2GHZ];
1033     if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
1034         hw->wiphy->bands[NL80211_BAND_5GHZ] =
1035             &common->sbands[NL80211_BAND_5GHZ];
1036 
1037 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1038     ath9k_set_mcc_capab(sc, hw);
1039 #endif
1040     ath9k_init_wow(hw);
1041     ath9k_cmn_reload_chainmask(ah);
1042 
1043     SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
1044 
1045     wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
1046     wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_AIRTIME_FAIRNESS);
1047     wiphy_ext_feature_set(hw->wiphy,
1048                   NL80211_EXT_FEATURE_MULTICAST_REGISTRATIONS);
1049     wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
1050 }
1051 
1052 int ath9k_init_device(u16 devid, struct ath_softc *sc,
1053             const struct ath_bus_ops *bus_ops)
1054 {
1055     struct ieee80211_hw *hw = sc->hw;
1056     struct ath_common *common;
1057     struct ath_hw *ah;
1058     int error = 0;
1059     struct ath_regulatory *reg;
1060 
1061     /* Bring up device */
1062     error = ath9k_init_softc(devid, sc, bus_ops);
1063     if (error)
1064         return error;
1065 
1066     ah = sc->sc_ah;
1067     common = ath9k_hw_common(ah);
1068     ath9k_set_hw_capab(sc, hw);
1069 
1070     /* Initialize regulatory */
1071     error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
1072                   ath9k_reg_notifier);
1073     if (error)
1074         goto deinit;
1075 
1076     reg = &common->regulatory;
1077 
1078     /* Setup TX DMA */
1079     error = ath_tx_init(sc, ATH_TXBUF);
1080     if (error != 0)
1081         goto deinit;
1082 
1083     /* Setup RX DMA */
1084     error = ath_rx_init(sc, ATH_RXBUF);
1085     if (error != 0)
1086         goto deinit;
1087 
1088     ath9k_init_txpower_limits(sc);
1089 
1090 #ifdef CONFIG_MAC80211_LEDS
1091     /* must be initialized before ieee80211_register_hw */
1092     sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
1093         IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
1094         ARRAY_SIZE(ath9k_tpt_blink));
1095 #endif
1096 
1097     wiphy_read_of_freq_limits(hw->wiphy);
1098 
1099     /* Register with mac80211 */
1100     error = ieee80211_register_hw(hw);
1101     if (error)
1102         goto rx_cleanup;
1103 
1104     error = ath9k_init_debug(ah);
1105     if (error) {
1106         ath_err(common, "Unable to create debugfs files\n");
1107         goto unregister;
1108     }
1109 
1110     /* Handle world regulatory */
1111     if (!ath_is_world_regd(reg)) {
1112         error = regulatory_hint(hw->wiphy, reg->alpha2);
1113         if (error)
1114             goto debug_cleanup;
1115     }
1116 
1117     ath_init_leds(sc);
1118     ath_start_rfkill_poll(sc);
1119 
1120     return 0;
1121 
1122 debug_cleanup:
1123     ath9k_deinit_debug(sc);
1124 unregister:
1125     ieee80211_unregister_hw(hw);
1126 rx_cleanup:
1127     ath_rx_cleanup(sc);
1128 deinit:
1129     ath9k_deinit_softc(sc);
1130     return error;
1131 }
1132 
1133 /*****************************/
1134 /*     De-Initialization     */
1135 /*****************************/
1136 
1137 static void ath9k_deinit_softc(struct ath_softc *sc)
1138 {
1139     int i = 0;
1140 
1141     ath9k_deinit_p2p(sc);
1142     ath9k_deinit_btcoex(sc);
1143 
1144     for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1145         if (ATH_TXQ_SETUP(sc, i))
1146             ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1147 
1148     del_timer_sync(&sc->sleep_timer);
1149     ath9k_hw_deinit(sc->sc_ah);
1150     if (sc->dfs_detector != NULL)
1151         sc->dfs_detector->exit(sc->dfs_detector);
1152 
1153     ath9k_eeprom_release(sc);
1154 }
1155 
1156 void ath9k_deinit_device(struct ath_softc *sc)
1157 {
1158     struct ieee80211_hw *hw = sc->hw;
1159 
1160     ath9k_ps_wakeup(sc);
1161 
1162     wiphy_rfkill_stop_polling(sc->hw->wiphy);
1163     ath_deinit_leds(sc);
1164 
1165     ath9k_ps_restore(sc);
1166 
1167     ath9k_deinit_debug(sc);
1168     ath9k_deinit_wow(hw);
1169     ieee80211_unregister_hw(hw);
1170     ath_rx_cleanup(sc);
1171     ath9k_deinit_softc(sc);
1172 }
1173 
1174 /************************/
1175 /*     Module Hooks     */
1176 /************************/
1177 
1178 static int __init ath9k_init(void)
1179 {
1180     int error;
1181 
1182     error = ath_pci_init();
1183     if (error < 0) {
1184         pr_err("No PCI devices found, driver not installed\n");
1185         error = -ENODEV;
1186         goto err_out;
1187     }
1188 
1189     error = ath_ahb_init();
1190     if (error < 0) {
1191         error = -ENODEV;
1192         goto err_pci_exit;
1193     }
1194 
1195     dmi_check_system(ath9k_quirks);
1196 
1197     return 0;
1198 
1199  err_pci_exit:
1200     ath_pci_exit();
1201  err_out:
1202     return error;
1203 }
1204 module_init(ath9k_init);
1205 
1206 static void __exit ath9k_exit(void)
1207 {
1208     is_ath9k_unloaded = true;
1209     ath_ahb_exit();
1210     ath_pci_exit();
1211     pr_info("%s: Driver unloaded\n", dev_info);
1212 }
1213 module_exit(ath9k_exit);
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