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0001 /*
0002  * Copyright (c) 2008-2011 Atheros Communications Inc.
0003  *
0004  * Permission to use, copy, modify, and/or distribute this software for any
0005  * purpose with or without fee is hereby granted, provided that the above
0006  * copyright notice and this permission notice appear in all copies.
0007  *
0008  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0009  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0010  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0011  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0012  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0013  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0014  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0015  */
0016 
0017 #ifndef HW_H
0018 #define HW_H
0019 
0020 #include <linux/if_ether.h>
0021 #include <linux/delay.h>
0022 #include <linux/io.h>
0023 #include <linux/firmware.h>
0024 
0025 #include "mac.h"
0026 #include "ani.h"
0027 #include "eeprom.h"
0028 #include "calib.h"
0029 #include "reg.h"
0030 #include "reg_mci.h"
0031 #include "phy.h"
0032 #include "btcoex.h"
0033 #include "dynack.h"
0034 
0035 #include "../regd.h"
0036 
0037 #define ATHEROS_VENDOR_ID   0x168c
0038 
0039 #define AR5416_DEVID_PCI    0x0023
0040 #define AR5416_DEVID_PCIE   0x0024
0041 #define AR9160_DEVID_PCI    0x0027
0042 #define AR9280_DEVID_PCI    0x0029
0043 #define AR9280_DEVID_PCIE   0x002a
0044 #define AR9285_DEVID_PCIE   0x002b
0045 #define AR2427_DEVID_PCIE   0x002c
0046 #define AR9287_DEVID_PCI    0x002d
0047 #define AR9287_DEVID_PCIE   0x002e
0048 #define AR9300_DEVID_PCIE   0x0030
0049 #define AR9300_DEVID_AR9340 0x0031
0050 #define AR9300_DEVID_AR9485_PCIE 0x0032
0051 #define AR9300_DEVID_AR9580 0x0033
0052 #define AR9300_DEVID_AR9462 0x0034
0053 #define AR9300_DEVID_AR9330 0x0035
0054 #define AR9300_DEVID_QCA955X    0x0038
0055 #define AR9485_DEVID_AR1111 0x0037
0056 #define AR9300_DEVID_AR9565     0x0036
0057 #define AR9300_DEVID_AR953X     0x003d
0058 #define AR9300_DEVID_QCA956X    0x003f
0059 
0060 #define AR5416_AR9100_DEVID 0x000b
0061 
0062 #define AR_SUBVENDOR_ID_NOG 0x0e11
0063 #define AR_SUBVENDOR_ID_NEW_A   0x7065
0064 #define AR5416_MAGIC        0x19641014
0065 
0066 #define AR9280_COEX2WIRE_SUBSYSID   0x309b
0067 #define AT9285_COEX3WIRE_SA_SUBSYSID    0x30aa
0068 #define AT9285_COEX3WIRE_DA_SUBSYSID    0x30ab
0069 
0070 #define ATH_AMPDU_LIMIT_MAX        (64 * 1024 - 1)
0071 
0072 #define ATH_DEFAULT_NOISE_FLOOR -95
0073 
0074 #define ATH9K_RSSI_BAD          -128
0075 
0076 #define ATH9K_NUM_CHANNELS  38
0077 
0078 /* Register read/write primitives */
0079 #define REG_WRITE(_ah, _reg, _val) \
0080     (_ah)->reg_ops.write((_ah), (_val), (_reg))
0081 
0082 #define REG_READ(_ah, _reg) \
0083     (_ah)->reg_ops.read((_ah), (_reg))
0084 
0085 #define REG_READ_MULTI(_ah, _addr, _val, _cnt)      \
0086     (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
0087 
0088 #define REG_RMW(_ah, _reg, _set, _clr) \
0089     (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
0090 
0091 #define ENABLE_REGWRITE_BUFFER(_ah)                 \
0092     do {                                \
0093         if ((_ah)->reg_ops.enable_write_buffer) \
0094             (_ah)->reg_ops.enable_write_buffer((_ah)); \
0095     } while (0)
0096 
0097 #define REGWRITE_BUFFER_FLUSH(_ah)                  \
0098     do {                                \
0099         if ((_ah)->reg_ops.write_flush)     \
0100             (_ah)->reg_ops.write_flush((_ah));  \
0101     } while (0)
0102 
0103 #define ENABLE_REG_RMW_BUFFER(_ah)                  \
0104     do {                                \
0105         if ((_ah)->reg_ops.enable_rmw_buffer)   \
0106             (_ah)->reg_ops.enable_rmw_buffer((_ah)); \
0107     } while (0)
0108 
0109 #define REG_RMW_BUFFER_FLUSH(_ah)                   \
0110     do {                                \
0111         if ((_ah)->reg_ops.rmw_flush)       \
0112             (_ah)->reg_ops.rmw_flush((_ah));    \
0113     } while (0)
0114 
0115 #define PR_EEP(_s, _val)                        \
0116     do {                                \
0117         len += scnprintf(buf + len, size - len, "%20s : %10d\n",\
0118                  _s, (_val));               \
0119     } while (0)
0120 
0121 #define SM(_v, _f)  (((_v) << _f##_S) & _f)
0122 #define MS(_v, _f)  (((_v) & _f) >> _f##_S)
0123 #define REG_RMW_FIELD(_a, _r, _f, _v) \
0124     REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
0125 #define REG_READ_FIELD(_a, _r, _f) \
0126     (((REG_READ(_a, _r) & _f) >> _f##_S))
0127 #define REG_SET_BIT(_a, _r, _f) \
0128     REG_RMW(_a, _r, (_f), 0)
0129 #define REG_CLR_BIT(_a, _r, _f) \
0130     REG_RMW(_a, _r, 0, (_f))
0131 
0132 #define DO_DELAY(x) do {                    \
0133         if (((++(x) % 64) == 0) &&          \
0134             (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
0135             != ATH_USB))                \
0136             udelay(1);              \
0137     } while (0)
0138 
0139 #define REG_WRITE_ARRAY(iniarray, column, regWr) \
0140     ath9k_hw_write_array(ah, iniarray, column, &(regWr))
0141 #define REG_READ_ARRAY(ah, array, size) \
0142     ath9k_hw_read_array(ah, array, size)
0143 
0144 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT             0
0145 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
0146 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED     2
0147 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME           3
0148 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL  4
0149 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED    5
0150 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED      6
0151 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA      0x16
0152 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK       0x17
0153 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA        0x18
0154 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK         0x19
0155 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX           0x14
0156 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX           0x13
0157 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX           9
0158 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX           8
0159 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE      0x1d
0160 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA        0x1e
0161 
0162 #define AR_GPIOD_MASK               0x00001FFF
0163 
0164 #define BASE_ACTIVATE_DELAY         100
0165 #define RTC_PLL_SETTLE_DELAY        (AR_SREV_9340(ah) ? 1000 : 100)
0166 #define COEF_SCALE_S                24
0167 #define HT40_CHANNEL_CENTER_SHIFT   10
0168 
0169 #define ATH9K_ANTENNA0_CHAINMASK    0x1
0170 #define ATH9K_ANTENNA1_CHAINMASK    0x2
0171 
0172 #define ATH9K_NUM_DMA_DEBUG_REGS    8
0173 #define ATH9K_NUM_QUEUES            10
0174 
0175 #define MAX_RATE_POWER              63
0176 #define MAX_COMBINED_POWER          254 /* 128 dBm, chosen to fit in u8 */
0177 #define AH_WAIT_TIMEOUT             100000 /* (us) */
0178 #define AH_TSF_WRITE_TIMEOUT        100    /* (us) */
0179 #define AH_TIME_QUANTUM             10
0180 #define AR_KEYTABLE_SIZE            128
0181 #define POWER_UP_TIME               10000
0182 #define SPUR_RSSI_THRESH            40
0183 #define UPPER_5G_SUB_BAND_START     5700
0184 #define MID_5G_SUB_BAND_START       5400
0185 
0186 #define CAB_TIMEOUT_VAL             10
0187 #define BEACON_TIMEOUT_VAL          10
0188 #define MIN_BEACON_TIMEOUT_VAL      1
0189 #define SLEEP_SLOP                  TU_TO_USEC(3)
0190 
0191 #define INIT_CONFIG_STATUS          0x00000000
0192 #define INIT_RSSI_THR               0x00000700
0193 #define INIT_BCON_CNTRL_REG         0x00000000
0194 
0195 #define TU_TO_USEC(_tu)             ((_tu) << 10)
0196 
0197 #define ATH9K_HW_RX_HP_QDEPTH   16
0198 #define ATH9K_HW_RX_LP_QDEPTH   128
0199 
0200 #define PAPRD_GAIN_TABLE_ENTRIES    32
0201 #define PAPRD_TABLE_SZ          24
0202 #define PAPRD_IDEAL_AGC2_PWR_RANGE  0xe0
0203 
0204 /*
0205  * Wake on Wireless
0206  */
0207 
0208 /* Keep Alive Frame */
0209 #define KAL_FRAME_LEN       28
0210 #define KAL_FRAME_TYPE      0x2 /* data frame */
0211 #define KAL_FRAME_SUB_TYPE  0x4 /* null data frame */
0212 #define KAL_DURATION_ID     0x3d
0213 #define KAL_NUM_DATA_WORDS  6
0214 #define KAL_NUM_DESC_WORDS  12
0215 #define KAL_ANTENNA_MODE    1
0216 #define KAL_TO_DS       1
0217 #define KAL_DELAY       4   /* delay of 4ms between 2 KAL frames */
0218 #define KAL_TIMEOUT     900
0219 
0220 #define MAX_PATTERN_SIZE        256
0221 #define MAX_PATTERN_MASK_SIZE       32
0222 #define MAX_NUM_PATTERN         16
0223 #define MAX_NUM_PATTERN_LEGACY      8
0224 #define MAX_NUM_USER_PATTERN        6 /*  deducting the disassociate and
0225                           deauthenticate packets */
0226 
0227 /*
0228  * WoW trigger mapping to hardware code
0229  */
0230 
0231 #define AH_WOW_USER_PATTERN_EN      BIT(0)
0232 #define AH_WOW_MAGIC_PATTERN_EN     BIT(1)
0233 #define AH_WOW_LINK_CHANGE      BIT(2)
0234 #define AH_WOW_BEACON_MISS      BIT(3)
0235 
0236 enum ath_hw_txq_subtype {
0237     ATH_TXQ_AC_BK = 0,
0238     ATH_TXQ_AC_BE = 1,
0239     ATH_TXQ_AC_VI = 2,
0240     ATH_TXQ_AC_VO = 3,
0241 };
0242 
0243 enum ath_ini_subsys {
0244     ATH_INI_PRE = 0,
0245     ATH_INI_CORE,
0246     ATH_INI_POST,
0247     ATH_INI_NUM_SPLIT,
0248 };
0249 
0250 enum ath9k_hw_caps {
0251     ATH9K_HW_CAP_HT                         = BIT(0),
0252     ATH9K_HW_CAP_RFSILENT                   = BIT(1),
0253     ATH9K_HW_CAP_AUTOSLEEP                  = BIT(2),
0254     ATH9K_HW_CAP_4KB_SPLITTRANS             = BIT(3),
0255     ATH9K_HW_CAP_EDMA           = BIT(4),
0256     ATH9K_HW_CAP_RAC_SUPPORTED      = BIT(5),
0257     ATH9K_HW_CAP_LDPC           = BIT(6),
0258     ATH9K_HW_CAP_FASTCLOCK          = BIT(7),
0259     ATH9K_HW_CAP_SGI_20         = BIT(8),
0260     ATH9K_HW_CAP_ANT_DIV_COMB       = BIT(10),
0261     ATH9K_HW_CAP_2GHZ           = BIT(11),
0262     ATH9K_HW_CAP_5GHZ           = BIT(12),
0263     ATH9K_HW_CAP_APM            = BIT(13),
0264 #ifdef CONFIG_ATH9K_PCOEM
0265     ATH9K_HW_CAP_RTT            = BIT(14),
0266     ATH9K_HW_CAP_MCI            = BIT(15),
0267     ATH9K_HW_CAP_BT_ANT_DIV         = BIT(17),
0268 #else
0269     ATH9K_HW_CAP_RTT            = 0,
0270     ATH9K_HW_CAP_MCI            = 0,
0271     ATH9K_HW_CAP_BT_ANT_DIV         = 0,
0272 #endif
0273     ATH9K_HW_CAP_DFS            = BIT(18),
0274     ATH9K_HW_CAP_PAPRD          = BIT(19),
0275     ATH9K_HW_CAP_FCC_BAND_SWITCH        = BIT(20),
0276 };
0277 
0278 /*
0279  * WoW device capabilities
0280  * @ATH9K_HW_WOW_DEVICE_CAPABLE: device revision is capable of WoW.
0281  * @ATH9K_HW_WOW_PATTERN_MATCH_EXACT: device is capable of matching
0282  * an exact user defined pattern or de-authentication/disassoc pattern.
0283  * @ATH9K_HW_WOW_PATTERN_MATCH_DWORD: device requires the first four
0284  * bytes of the pattern for user defined pattern, de-authentication and
0285  * disassociation patterns for all types of possible frames recieved
0286  * of those types.
0287  */
0288 
0289 struct ath9k_hw_wow {
0290     u32 wow_event_mask;
0291     u32 wow_event_mask2;
0292     u8 max_patterns;
0293 };
0294 
0295 struct ath9k_hw_capabilities {
0296     u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
0297     u16 rts_aggr_limit;
0298     u8 tx_chainmask;
0299     u8 rx_chainmask;
0300     u8 chip_chainmask;
0301     u8 max_txchains;
0302     u8 max_rxchains;
0303     u8 num_gpio_pins;
0304     u32 gpio_mask;
0305     u32 gpio_requested;
0306     u8 rx_hp_qdepth;
0307     u8 rx_lp_qdepth;
0308     u8 rx_status_len;
0309     u8 tx_desc_len;
0310     u8 txs_len;
0311 };
0312 
0313 #define AR_NO_SPUR          0x8000
0314 #define AR_BASE_FREQ_2GHZ       2300
0315 #define AR_BASE_FREQ_5GHZ       4900
0316 #define AR_SPUR_FEEQ_BOUND_HT40 19
0317 #define AR_SPUR_FEEQ_BOUND_HT20 10
0318 
0319 enum ath9k_hw_hang_checks {
0320     HW_BB_WATCHDOG            = BIT(0),
0321     HW_PHYRESTART_CLC_WAR     = BIT(1),
0322     HW_BB_RIFS_HANG           = BIT(2),
0323     HW_BB_DFS_HANG            = BIT(3),
0324     HW_BB_RX_CLEAR_STUCK_HANG = BIT(4),
0325     HW_MAC_HANG               = BIT(5),
0326 };
0327 
0328 #define AR_PCIE_PLL_PWRSAVE_CONTROL BIT(0)
0329 #define AR_PCIE_PLL_PWRSAVE_ON_D3   BIT(1)
0330 #define AR_PCIE_PLL_PWRSAVE_ON_D0   BIT(2)
0331 #define AR_PCIE_CDR_PWRSAVE_ON_D3   BIT(3)
0332 #define AR_PCIE_CDR_PWRSAVE_ON_D0   BIT(4)
0333 
0334 struct ath9k_ops_config {
0335     int dma_beacon_response_time;
0336     int sw_beacon_response_time;
0337     bool cwm_ignore_extcca;
0338     u32 pcie_waen;
0339     u8 analog_shiftreg;
0340     u32 ofdm_trig_low;
0341     u32 ofdm_trig_high;
0342     u32 cck_trig_high;
0343     u32 cck_trig_low;
0344     bool enable_paprd;
0345     int serialize_regmode;
0346     bool rx_intr_mitigation;
0347     bool tx_intr_mitigation;
0348     u8 max_txtrig_level;
0349     u16 ani_poll_interval; /* ANI poll interval in ms */
0350     u16 hw_hang_checks;
0351     u16 rimt_first;
0352     u16 rimt_last;
0353 
0354     /* Platform specific config */
0355     u32 aspm_l1_fix;
0356     u32 xlna_gpio;
0357     u32 ant_ctrl_comm2g_switch_enable;
0358     bool xatten_margin_cfg;
0359     bool alt_mingainidx;
0360     u8 pll_pwrsave;
0361     bool tx_gain_buffalo;
0362     bool led_active_high;
0363 };
0364 
0365 enum ath9k_int {
0366     ATH9K_INT_RX = 0x00000001,
0367     ATH9K_INT_RXDESC = 0x00000002,
0368     ATH9K_INT_RXHP = 0x00000001,
0369     ATH9K_INT_RXLP = 0x00000002,
0370     ATH9K_INT_RXNOFRM = 0x00000008,
0371     ATH9K_INT_RXEOL = 0x00000010,
0372     ATH9K_INT_RXORN = 0x00000020,
0373     ATH9K_INT_TX = 0x00000040,
0374     ATH9K_INT_TXDESC = 0x00000080,
0375     ATH9K_INT_TIM_TIMER = 0x00000100,
0376     ATH9K_INT_MCI = 0x00000200,
0377     ATH9K_INT_BB_WATCHDOG = 0x00000400,
0378     ATH9K_INT_TXURN = 0x00000800,
0379     ATH9K_INT_MIB = 0x00001000,
0380     ATH9K_INT_RXPHY = 0x00004000,
0381     ATH9K_INT_RXKCM = 0x00008000,
0382     ATH9K_INT_SWBA = 0x00010000,
0383     ATH9K_INT_BMISS = 0x00040000,
0384     ATH9K_INT_BNR = 0x00100000,
0385     ATH9K_INT_TIM = 0x00200000,
0386     ATH9K_INT_DTIM = 0x00400000,
0387     ATH9K_INT_DTIMSYNC = 0x00800000,
0388     ATH9K_INT_GPIO = 0x01000000,
0389     ATH9K_INT_CABEND = 0x02000000,
0390     ATH9K_INT_TSFOOR = 0x04000000,
0391     ATH9K_INT_GENTIMER = 0x08000000,
0392     ATH9K_INT_CST = 0x10000000,
0393     ATH9K_INT_GTT = 0x20000000,
0394     ATH9K_INT_FATAL = 0x40000000,
0395     ATH9K_INT_GLOBAL = 0x80000000,
0396     ATH9K_INT_BMISC = ATH9K_INT_TIM |
0397         ATH9K_INT_DTIM |
0398         ATH9K_INT_DTIMSYNC |
0399         ATH9K_INT_TSFOOR |
0400         ATH9K_INT_CABEND,
0401     ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
0402         ATH9K_INT_RXDESC |
0403         ATH9K_INT_RXEOL |
0404         ATH9K_INT_RXORN |
0405         ATH9K_INT_TXURN |
0406         ATH9K_INT_TXDESC |
0407         ATH9K_INT_MIB |
0408         ATH9K_INT_RXPHY |
0409         ATH9K_INT_RXKCM |
0410         ATH9K_INT_SWBA |
0411         ATH9K_INT_BMISS |
0412         ATH9K_INT_GPIO,
0413     ATH9K_INT_NOCARD = 0xffffffff
0414 };
0415 
0416 #define MAX_RTT_TABLE_ENTRY     6
0417 #define MAX_IQCAL_MEASUREMENT   8
0418 #define MAX_CL_TAB_ENTRY    16
0419 #define CL_TAB_ENTRY(reg_base)  (reg_base + (4 * j))
0420 
0421 enum ath9k_cal_flags {
0422     RTT_DONE,
0423     PAPRD_PACKET_SENT,
0424     PAPRD_DONE,
0425     NFCAL_PENDING,
0426     NFCAL_INTF,
0427     TXIQCAL_DONE,
0428     TXCLCAL_DONE,
0429     SW_PKDET_DONE,
0430     LONGCAL_PENDING,
0431 };
0432 
0433 struct ath9k_hw_cal_data {
0434     u16 channel;
0435     u16 channelFlags;
0436     unsigned long cal_flags;
0437     int32_t CalValid;
0438     int8_t iCoff;
0439     int8_t qCoff;
0440     u8 caldac[2];
0441     u16 small_signal_gain[AR9300_MAX_CHAINS];
0442     u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
0443     u32 num_measures[AR9300_MAX_CHAINS];
0444     int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS];
0445     u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY];
0446     u32 rtt_table[AR9300_MAX_CHAINS][MAX_RTT_TABLE_ENTRY];
0447     struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
0448 };
0449 
0450 struct ath9k_channel {
0451     struct ieee80211_channel *chan;
0452     u16 channel;
0453     u16 channelFlags;
0454     s16 noisefloor;
0455 };
0456 
0457 #define CHANNEL_5GHZ        BIT(0)
0458 #define CHANNEL_HALF        BIT(1)
0459 #define CHANNEL_QUARTER     BIT(2)
0460 #define CHANNEL_HT      BIT(3)
0461 #define CHANNEL_HT40PLUS    BIT(4)
0462 #define CHANNEL_HT40MINUS   BIT(5)
0463 
0464 #define IS_CHAN_5GHZ(_c) (!!((_c)->channelFlags & CHANNEL_5GHZ))
0465 #define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c))
0466 
0467 #define IS_CHAN_HALF_RATE(_c) (!!((_c)->channelFlags & CHANNEL_HALF))
0468 #define IS_CHAN_QUARTER_RATE(_c) (!!((_c)->channelFlags & CHANNEL_QUARTER))
0469 #define IS_CHAN_A_FAST_CLOCK(_ah, _c)           \
0470     (IS_CHAN_5GHZ(_c) && ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
0471 
0472 #define IS_CHAN_HT(_c) ((_c)->channelFlags & CHANNEL_HT)
0473 
0474 #define IS_CHAN_HT20(_c) (IS_CHAN_HT(_c) && !IS_CHAN_HT40(_c))
0475 
0476 #define IS_CHAN_HT40(_c) \
0477     (!!((_c)->channelFlags & (CHANNEL_HT40PLUS | CHANNEL_HT40MINUS)))
0478 
0479 #define IS_CHAN_HT40PLUS(_c) ((_c)->channelFlags & CHANNEL_HT40PLUS)
0480 #define IS_CHAN_HT40MINUS(_c) ((_c)->channelFlags & CHANNEL_HT40MINUS)
0481 
0482 enum ath9k_power_mode {
0483     ATH9K_PM_AWAKE = 0,
0484     ATH9K_PM_FULL_SLEEP,
0485     ATH9K_PM_NETWORK_SLEEP,
0486     ATH9K_PM_UNDEFINED
0487 };
0488 
0489 enum ser_reg_mode {
0490     SER_REG_MODE_OFF = 0,
0491     SER_REG_MODE_ON = 1,
0492     SER_REG_MODE_AUTO = 2,
0493 };
0494 
0495 enum ath9k_rx_qtype {
0496     ATH9K_RX_QUEUE_HP,
0497     ATH9K_RX_QUEUE_LP,
0498     ATH9K_RX_QUEUE_MAX,
0499 };
0500 
0501 struct ath9k_beacon_state {
0502     u32 bs_nexttbtt;
0503     u32 bs_nextdtim;
0504     u32 bs_intval;
0505 #define ATH9K_TSFOOR_THRESHOLD    0x00004240 /* 16k us */
0506     u32 bs_dtimperiod;
0507     u16 bs_bmissthreshold;
0508     u32 bs_sleepduration;
0509     u32 bs_tsfoor_threshold;
0510 };
0511 
0512 struct chan_centers {
0513     u16 synth_center;
0514     u16 ctl_center;
0515     u16 ext_center;
0516 };
0517 
0518 enum {
0519     ATH9K_RESET_POWER_ON,
0520     ATH9K_RESET_WARM,
0521     ATH9K_RESET_COLD,
0522 };
0523 
0524 struct ath9k_hw_version {
0525     u32 magic;
0526     u16 devid;
0527     u16 subvendorid;
0528     u32 macVersion;
0529     u16 macRev;
0530     u16 phyRev;
0531     u16 analog5GhzRev;
0532     u16 analog2GhzRev;
0533     enum ath_usb_dev usbdev;
0534 };
0535 
0536 /* Generic TSF timer definitions */
0537 
0538 #define ATH_MAX_GEN_TIMER   16
0539 
0540 #define AR_GENTMR_BIT(_index)   (1 << (_index))
0541 
0542 struct ath_gen_timer_configuration {
0543     u32 next_addr;
0544     u32 period_addr;
0545     u32 mode_addr;
0546     u32 mode_mask;
0547 };
0548 
0549 struct ath_gen_timer {
0550     void (*trigger)(void *arg);
0551     void (*overflow)(void *arg);
0552     void *arg;
0553     u8 index;
0554 };
0555 
0556 struct ath_gen_timer_table {
0557     struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
0558     u16 timer_mask;
0559     bool tsf2_enabled;
0560 };
0561 
0562 struct ath_hw_antcomb_conf {
0563     u8 main_lna_conf;
0564     u8 alt_lna_conf;
0565     u8 fast_div_bias;
0566     u8 main_gaintb;
0567     u8 alt_gaintb;
0568     int lna1_lna2_delta;
0569     int lna1_lna2_switch_delta;
0570     u8 div_group;
0571 };
0572 
0573 /**
0574  * struct ath_hw_radar_conf - radar detection initialization parameters
0575  *
0576  * @pulse_inband: threshold for checking the ratio of in-band power
0577  *  to total power for short radar pulses (half dB steps)
0578  * @pulse_inband_step: threshold for checking an in-band power to total
0579  *  power ratio increase for short radar pulses (half dB steps)
0580  * @pulse_height: threshold for detecting the beginning of a short
0581  *  radar pulse (dB step)
0582  * @pulse_rssi: threshold for detecting if a short radar pulse is
0583  *  gone (dB step)
0584  * @pulse_maxlen: maximum pulse length (0.8 us steps)
0585  *
0586  * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
0587  * @radar_inband: threshold for checking the ratio of in-band power
0588  *  to total power for long radar pulses (half dB steps)
0589  * @fir_power: threshold for detecting the end of a long radar pulse (dB)
0590  *
0591  * @ext_channel: enable extension channel radar detection
0592  */
0593 struct ath_hw_radar_conf {
0594     unsigned int pulse_inband;
0595     unsigned int pulse_inband_step;
0596     unsigned int pulse_height;
0597     unsigned int pulse_rssi;
0598     unsigned int pulse_maxlen;
0599 
0600     unsigned int radar_rssi;
0601     unsigned int radar_inband;
0602     int fir_power;
0603 
0604     bool ext_channel;
0605 };
0606 
0607 /**
0608  * struct ath_hw_private_ops - callbacks used internally by hardware code
0609  *
0610  * This structure contains private callbacks designed to only be used internally
0611  * by the hardware core.
0612  *
0613  * @init_cal_settings: setup types of calibrations supported
0614  * @init_cal: starts actual calibration
0615  *
0616  * @init_mode_gain_regs: Initialize TX/RX gain registers
0617  *
0618  * @rf_set_freq: change frequency
0619  * @spur_mitigate_freq: spur mitigation
0620  * @set_rf_regs:
0621  * @compute_pll_control: compute the PLL control value to use for
0622  *  AR_RTC_PLL_CONTROL for a given channel
0623  * @setup_calibration: set up calibration
0624  * @iscal_supported: used to query if a type of calibration is supported
0625  *
0626  * @ani_cache_ini_regs: cache the values for ANI from the initial
0627  *  register settings through the register initialization.
0628  */
0629 struct ath_hw_private_ops {
0630     void (*init_hang_checks)(struct ath_hw *ah);
0631     bool (*detect_mac_hang)(struct ath_hw *ah);
0632     bool (*detect_bb_hang)(struct ath_hw *ah);
0633 
0634     /* Calibration ops */
0635     void (*init_cal_settings)(struct ath_hw *ah);
0636     bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
0637 
0638     void (*init_mode_gain_regs)(struct ath_hw *ah);
0639     void (*setup_calibration)(struct ath_hw *ah,
0640                   struct ath9k_cal_list *currCal);
0641 
0642     /* PHY ops */
0643     int (*rf_set_freq)(struct ath_hw *ah,
0644                struct ath9k_channel *chan);
0645     void (*spur_mitigate_freq)(struct ath_hw *ah,
0646                    struct ath9k_channel *chan);
0647     bool (*set_rf_regs)(struct ath_hw *ah,
0648                 struct ath9k_channel *chan,
0649                 u16 modesIndex);
0650     void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
0651     void (*init_bb)(struct ath_hw *ah,
0652             struct ath9k_channel *chan);
0653     int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
0654     void (*olc_init)(struct ath_hw *ah);
0655     void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
0656     void (*mark_phy_inactive)(struct ath_hw *ah);
0657     void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
0658     bool (*rfbus_req)(struct ath_hw *ah);
0659     void (*rfbus_done)(struct ath_hw *ah);
0660     void (*restore_chainmask)(struct ath_hw *ah);
0661     u32 (*compute_pll_control)(struct ath_hw *ah,
0662                    struct ath9k_channel *chan);
0663     bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
0664                 int param);
0665     void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
0666     void (*set_radar_params)(struct ath_hw *ah,
0667                  struct ath_hw_radar_conf *conf);
0668     int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan,
0669                 u8 *ini_reloaded);
0670 
0671     /* ANI */
0672     void (*ani_cache_ini_regs)(struct ath_hw *ah);
0673 
0674 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
0675     bool (*is_aic_enabled)(struct ath_hw *ah);
0676 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
0677 };
0678 
0679 /**
0680  * struct ath_spec_scan - parameters for Atheros spectral scan
0681  *
0682  * @enabled: enable/disable spectral scan
0683  * @short_repeat: controls whether the chip is in spectral scan mode
0684  *        for 4 usec (enabled) or 204 usec (disabled)
0685  * @count: number of scan results requested. There are special meanings
0686  *     in some chip revisions:
0687  *     AR92xx: highest bit set (>=128) for endless mode
0688  *         (spectral scan won't stopped until explicitly disabled)
0689  *     AR9300 and newer: 0 for endless mode
0690  * @endless: true if endless mode is intended. Otherwise, count value is
0691  *           corrected to the next possible value.
0692  * @period: time duration between successive spectral scan entry points
0693  *      (period*256*Tclk). Tclk = ath_common->clockrate
0694  * @fft_period: PHY passes FFT frames to MAC every (fft_period+1)*4uS
0695  *
0696  * Note: Tclk = 40MHz or 44MHz depending upon operating mode.
0697  *   Typically it's 44MHz in 2/5GHz on later chips, but there's
0698  *   a "fast clock" check for this in 5GHz.
0699  *
0700  */
0701 struct ath_spec_scan {
0702     bool enabled;
0703     bool short_repeat;
0704     bool endless;
0705     u8 count;
0706     u8 period;
0707     u8 fft_period;
0708 };
0709 
0710 /**
0711  * struct ath_hw_ops - callbacks used by hardware code and driver code
0712  *
0713  * This structure contains callbacks designed to to be used internally by
0714  * hardware code and also by the lower level driver.
0715  *
0716  * @config_pci_powersave:
0717  * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
0718  *
0719  * @spectral_scan_config: set parameters for spectral scan and enable/disable it
0720  * @spectral_scan_trigger: trigger a spectral scan run
0721  * @spectral_scan_wait: wait for a spectral scan run to finish
0722  */
0723 struct ath_hw_ops {
0724     void (*config_pci_powersave)(struct ath_hw *ah,
0725                      bool power_off);
0726     void (*rx_enable)(struct ath_hw *ah);
0727     void (*set_desc_link)(void *ds, u32 link);
0728     int (*calibrate)(struct ath_hw *ah, struct ath9k_channel *chan,
0729              u8 rxchainmask, bool longcal);
0730     bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked,
0731             u32 *sync_cause_p);
0732     void (*set_txdesc)(struct ath_hw *ah, void *ds,
0733                struct ath_tx_info *i);
0734     int (*proc_txdesc)(struct ath_hw *ah, void *ds,
0735                struct ath_tx_status *ts);
0736     int (*get_duration)(struct ath_hw *ah, const void *ds, int index);
0737     void (*antdiv_comb_conf_get)(struct ath_hw *ah,
0738             struct ath_hw_antcomb_conf *antconf);
0739     void (*antdiv_comb_conf_set)(struct ath_hw *ah,
0740             struct ath_hw_antcomb_conf *antconf);
0741     void (*spectral_scan_config)(struct ath_hw *ah,
0742                      struct ath_spec_scan *param);
0743     void (*spectral_scan_trigger)(struct ath_hw *ah);
0744     void (*spectral_scan_wait)(struct ath_hw *ah);
0745 
0746     void (*tx99_start)(struct ath_hw *ah, u32 qnum);
0747     void (*tx99_stop)(struct ath_hw *ah);
0748     void (*tx99_set_txpower)(struct ath_hw *ah, u8 power);
0749 
0750 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
0751     void (*set_bt_ant_diversity)(struct ath_hw *hw, bool enable);
0752 #endif
0753 };
0754 
0755 struct ath_nf_limits {
0756     s16 max;
0757     s16 min;
0758     s16 nominal;
0759     s16 cal[AR5416_MAX_CHAINS];
0760     s16 pwr[AR5416_MAX_CHAINS];
0761 };
0762 
0763 enum ath_cal_list {
0764     TX_IQ_CAL         = BIT(0),
0765     TX_IQ_ON_AGC_CAL  = BIT(1),
0766     TX_CL_CAL         = BIT(2),
0767 };
0768 
0769 /* ah_flags */
0770 #define AH_USE_EEPROM   0x1
0771 #define AH_UNPLUGGED    0x2 /* The card has been physically removed. */
0772 #define AH_FASTCC       0x4
0773 #define AH_NO_EEP_SWAP  0x8 /* Do not swap EEPROM data */
0774 
0775 struct ath_hw {
0776     struct ath_ops reg_ops;
0777 
0778     struct device *dev;
0779     struct ieee80211_hw *hw;
0780     struct ath_common common;
0781     struct ath9k_hw_version hw_version;
0782     struct ath9k_ops_config config;
0783     struct ath9k_hw_capabilities caps;
0784     struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
0785     struct ath9k_channel *curchan;
0786 
0787     union {
0788         struct ar5416_eeprom_def def;
0789         struct ar5416_eeprom_4k map4k;
0790         struct ar9287_eeprom map9287;
0791         struct ar9300_eeprom ar9300_eep;
0792     } eeprom;
0793     const struct eeprom_ops *eep_ops;
0794 
0795     bool sw_mgmt_crypto_tx;
0796     bool sw_mgmt_crypto_rx;
0797     bool is_pciexpress;
0798     bool aspm_enabled;
0799     bool is_monitoring;
0800     bool need_an_top2_fixup;
0801     u16 tx_trig_level;
0802 
0803     u32 nf_regs[6];
0804     struct ath_nf_limits nf_2g;
0805     struct ath_nf_limits nf_5g;
0806     u16 rfsilent;
0807     u32 rfkill_gpio;
0808     u32 rfkill_polarity;
0809     u32 ah_flags;
0810     s16 nf_override;
0811 
0812     bool reset_power_on;
0813     bool htc_reset_init;
0814 
0815     enum nl80211_iftype opmode;
0816     enum ath9k_power_mode power_mode;
0817 
0818     s8 noise;
0819     struct ath9k_hw_cal_data *caldata;
0820     struct ath9k_pacal_info pacal_info;
0821     struct ar5416Stats stats;
0822     struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
0823     DECLARE_BITMAP(pending_del_keymap, ATH_KEYMAX);
0824 
0825     enum ath9k_int imask;
0826     u32 imrs2_reg;
0827     u32 txok_interrupt_mask;
0828     u32 txerr_interrupt_mask;
0829     u32 txdesc_interrupt_mask;
0830     u32 txeol_interrupt_mask;
0831     u32 txurn_interrupt_mask;
0832     atomic_t intr_ref_cnt;
0833     bool chip_fullsleep;
0834     u32 modes_index;
0835 
0836     /* Calibration */
0837     u32 supp_cals;
0838     unsigned long cal_start_time;
0839     struct ath9k_cal_list iq_caldata;
0840     struct ath9k_cal_list adcgain_caldata;
0841     struct ath9k_cal_list adcdc_caldata;
0842     struct ath9k_cal_list *cal_list;
0843     struct ath9k_cal_list *cal_list_last;
0844     struct ath9k_cal_list *cal_list_curr;
0845 #define totalPowerMeasI meas0.unsign
0846 #define totalPowerMeasQ meas1.unsign
0847 #define totalIqCorrMeas meas2.sign
0848 #define totalAdcIOddPhase  meas0.unsign
0849 #define totalAdcIEvenPhase meas1.unsign
0850 #define totalAdcQOddPhase  meas2.unsign
0851 #define totalAdcQEvenPhase meas3.unsign
0852 #define totalAdcDcOffsetIOddPhase  meas0.sign
0853 #define totalAdcDcOffsetIEvenPhase meas1.sign
0854 #define totalAdcDcOffsetQOddPhase  meas2.sign
0855 #define totalAdcDcOffsetQEvenPhase meas3.sign
0856     union {
0857         u32 unsign[AR5416_MAX_CHAINS];
0858         int32_t sign[AR5416_MAX_CHAINS];
0859     } meas0;
0860     union {
0861         u32 unsign[AR5416_MAX_CHAINS];
0862         int32_t sign[AR5416_MAX_CHAINS];
0863     } meas1;
0864     union {
0865         u32 unsign[AR5416_MAX_CHAINS];
0866         int32_t sign[AR5416_MAX_CHAINS];
0867     } meas2;
0868     union {
0869         u32 unsign[AR5416_MAX_CHAINS];
0870         int32_t sign[AR5416_MAX_CHAINS];
0871     } meas3;
0872     u16 cal_samples;
0873     u8 enabled_cals;
0874 
0875     u32 sta_id1_defaults;
0876     u32 misc_mode;
0877 
0878     /* Private to hardware code */
0879     struct ath_hw_private_ops private_ops;
0880     /* Accessed by the lower level driver */
0881     struct ath_hw_ops ops;
0882 
0883     /* Used to program the radio on non single-chip devices */
0884     u32 *analogBank6Data;
0885 
0886     int coverage_class;
0887     u32 slottime;
0888     u32 globaltxtimeout;
0889 
0890     /* ANI */
0891     u32 aniperiod;
0892     enum ath9k_ani_cmd ani_function;
0893     u32 ani_skip_count;
0894     struct ar5416AniState ani;
0895 
0896 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
0897     struct ath_btcoex_hw btcoex_hw;
0898 #endif
0899 
0900     u32 intr_txqs;
0901     u8 txchainmask;
0902     u8 rxchainmask;
0903 
0904     struct ath_hw_radar_conf radar_conf;
0905 
0906     u32 originalGain[22];
0907     int initPDADC;
0908     int PDADCdelta;
0909     int led_pin;
0910     u32 gpio_mask;
0911     u32 gpio_val;
0912 
0913     struct ar5416IniArray ini_dfs;
0914     struct ar5416IniArray iniModes;
0915     struct ar5416IniArray iniCommon;
0916     struct ar5416IniArray iniBB_RfGain;
0917     struct ar5416IniArray iniBank6;
0918     struct ar5416IniArray iniAddac;
0919     struct ar5416IniArray iniPcieSerdes;
0920     struct ar5416IniArray iniPcieSerdesLowPower;
0921     struct ar5416IniArray iniModesFastClock;
0922     struct ar5416IniArray iniAdditional;
0923     struct ar5416IniArray iniModesRxGain;
0924     struct ar5416IniArray ini_modes_rx_gain_bounds;
0925     struct ar5416IniArray iniModesTxGain;
0926     struct ar5416IniArray iniCckfirNormal;
0927     struct ar5416IniArray iniCckfirJapan2484;
0928     struct ar5416IniArray iniModes_9271_ANI_reg;
0929     struct ar5416IniArray ini_radio_post_sys2ant;
0930     struct ar5416IniArray ini_modes_rxgain_xlna;
0931     struct ar5416IniArray ini_modes_rxgain_bb_core;
0932     struct ar5416IniArray ini_modes_rxgain_bb_postamble;
0933 
0934     struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
0935     struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
0936     struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
0937     struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
0938 
0939     u32 intr_gen_timer_trigger;
0940     u32 intr_gen_timer_thresh;
0941     struct ath_gen_timer_table hw_gen_timers;
0942 
0943     struct ar9003_txs *ts_ring;
0944     u32 ts_paddr_start;
0945     u32 ts_paddr_end;
0946     u16 ts_tail;
0947     u16 ts_size;
0948 
0949     u32 bb_watchdog_last_status;
0950     u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
0951     u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */
0952 
0953     unsigned int paprd_target_power;
0954     unsigned int paprd_training_power;
0955     unsigned int paprd_ratemask;
0956     unsigned int paprd_ratemask_ht40;
0957     bool paprd_table_write_done;
0958     u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
0959     u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
0960     /*
0961      * Store the permanent value of Reg 0x4004in WARegVal
0962      * so we dont have to R/M/W. We should not be reading
0963      * this register when in sleep states.
0964      */
0965     u32 WARegVal;
0966 
0967     /* Enterprise mode cap */
0968     u32 ent_mode;
0969 
0970 #ifdef CONFIG_ATH9K_WOW
0971     struct ath9k_hw_wow wow;
0972 #endif
0973     bool is_clk_25mhz;
0974     int (*get_mac_revision)(void);
0975     int (*external_reset)(void);
0976     bool disable_2ghz;
0977     bool disable_5ghz;
0978 
0979     const struct firmware *eeprom_blob;
0980     u16 *nvmem_blob;    /* devres managed */
0981     size_t nvmem_blob_len;
0982 
0983     struct ath_dynack dynack;
0984 
0985     bool tpc_enabled;
0986     u8 tx_power[Ar5416RateSize];
0987     u8 tx_power_stbc[Ar5416RateSize];
0988     bool msi_enabled;
0989     u32 msi_mask;
0990     u32 msi_reg;
0991 };
0992 
0993 struct ath_bus_ops {
0994     enum ath_bus_type ath_bus_type;
0995     void (*read_cachesize)(struct ath_common *common, int *csz);
0996     bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
0997     void (*bt_coex_prep)(struct ath_common *common);
0998     void (*aspm_init)(struct ath_common *common);
0999 };
1000 
1001 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
1002 {
1003     return &ah->common;
1004 }
1005 
1006 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
1007 {
1008     return &(ath9k_hw_common(ah)->regulatory);
1009 }
1010 
1011 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
1012 {
1013     return &ah->private_ops;
1014 }
1015 
1016 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
1017 {
1018     return &ah->ops;
1019 }
1020 
1021 static inline u8 get_streams(int mask)
1022 {
1023     return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
1024 }
1025 
1026 /* Initialization, Detach, Reset */
1027 void ath9k_hw_deinit(struct ath_hw *ah);
1028 int ath9k_hw_init(struct ath_hw *ah);
1029 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1030            struct ath9k_hw_cal_data *caldata, bool fastcc);
1031 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
1032 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
1033 
1034 /* GPIO / RFKILL / Antennae */
1035 void ath9k_hw_gpio_request_in(struct ath_hw *ah, u32 gpio, const char *label);
1036 void ath9k_hw_gpio_request_out(struct ath_hw *ah, u32 gpio, const char *label,
1037                    u32 ah_signal_type);
1038 void ath9k_hw_gpio_free(struct ath_hw *ah, u32 gpio);
1039 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
1040 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
1041 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
1042 
1043 /* General Operation */
1044 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
1045               int hw_delay);
1046 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
1047 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
1048               int column, unsigned int *writecnt);
1049 void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size);
1050 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
1051 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
1052                u8 phy, int kbps,
1053                u32 frameLen, u16 rateix, bool shortPreamble);
1054 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
1055                   struct ath9k_channel *chan,
1056                   struct chan_centers *centers);
1057 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
1058 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
1059 bool ath9k_hw_phy_disable(struct ath_hw *ah);
1060 bool ath9k_hw_disable(struct ath_hw *ah);
1061 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
1062 void ath9k_hw_setopmode(struct ath_hw *ah);
1063 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
1064 void ath9k_hw_write_associd(struct ath_hw *ah);
1065 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
1066 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
1067 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
1068 void ath9k_hw_reset_tsf(struct ath_hw *ah);
1069 u32 ath9k_hw_get_tsf_offset(struct timespec64 *last, struct timespec64 *cur);
1070 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set);
1071 void ath9k_hw_init_global_settings(struct ath_hw *ah);
1072 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
1073 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan);
1074 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
1075 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1076                     const struct ath9k_beacon_state *bs);
1077 void ath9k_hw_check_nav(struct ath_hw *ah);
1078 bool ath9k_hw_check_alive(struct ath_hw *ah);
1079 
1080 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
1081 
1082 /* Generic hw timer primitives */
1083 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
1084                       void (*trigger)(void *),
1085                       void (*overflow)(void *),
1086                       void *arg,
1087                       u8 timer_index);
1088 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
1089                   struct ath_gen_timer *timer,
1090                   u32 timer_next,
1091                   u32 timer_period);
1092 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah);
1093 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
1094 
1095 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
1096 void ath_gen_timer_isr(struct ath_hw *hw);
1097 
1098 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
1099 
1100 /* PHY */
1101 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1102                    u32 *coef_mantissa, u32 *coef_exponent);
1103 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
1104                 bool test);
1105 
1106 /*
1107  * Code Specific to AR5008, AR9001 or AR9002,
1108  * we stuff these here to avoid callbacks for AR9003.
1109  */
1110 int ar9002_hw_rf_claim(struct ath_hw *ah);
1111 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
1112 
1113 /*
1114  * Code specific to AR9003, we stuff these here to avoid callbacks
1115  * for older families
1116  */
1117 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah);
1118 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
1119 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
1120 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
1121 void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
1122 void ar9003_paprd_enable(struct ath_hw *ah, bool val);
1123 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
1124                     struct ath9k_hw_cal_data *caldata,
1125                     int chain);
1126 int ar9003_paprd_create_curve(struct ath_hw *ah,
1127                   struct ath9k_hw_cal_data *caldata, int chain);
1128 void ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
1129 int ar9003_paprd_init_table(struct ath_hw *ah);
1130 bool ar9003_paprd_is_done(struct ath_hw *ah);
1131 bool ar9003_is_paprd_enabled(struct ath_hw *ah);
1132 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
1133 void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array,
1134                  struct ath9k_channel *chan);
1135 void ar5008_hw_cmn_spur_mitigate(struct ath_hw *ah,
1136                  struct ath9k_channel *chan, int bin);
1137 void ar5008_hw_init_rate_txpower(struct ath_hw *ah, int16_t *rate_array,
1138                  struct ath9k_channel *chan, int ht40_delta);
1139 
1140 /* Hardware family op attach helpers */
1141 int ar5008_hw_attach_phy_ops(struct ath_hw *ah);
1142 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1143 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
1144 
1145 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1146 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1147 
1148 int ar9002_hw_attach_ops(struct ath_hw *ah);
1149 void ar9003_hw_attach_ops(struct ath_hw *ah);
1150 
1151 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
1152 
1153 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
1154 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
1155 
1156 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us);
1157 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us);
1158 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
1159 
1160 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1161 void ar9003_hw_attach_aic_ops(struct ath_hw *ah);
1162 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1163 {
1164     return ah->btcoex_hw.enabled;
1165 }
1166 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1167 {
1168     return ah->common.btcoex_enabled &&
1169            (ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
1170 
1171 }
1172 void ath9k_hw_btcoex_enable(struct ath_hw *ah);
1173 static inline enum ath_btcoex_scheme
1174 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1175 {
1176     return ah->btcoex_hw.scheme;
1177 }
1178 #else
1179 static inline void ar9003_hw_attach_aic_ops(struct ath_hw *ah)
1180 {
1181 }
1182 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1183 {
1184     return false;
1185 }
1186 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1187 {
1188     return false;
1189 }
1190 static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah)
1191 {
1192 }
1193 static inline enum ath_btcoex_scheme
1194 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1195 {
1196     return ATH_BTCOEX_CFG_NONE;
1197 }
1198 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
1199 
1200 
1201 #ifdef CONFIG_ATH9K_WOW
1202 int ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
1203                    u8 *user_mask, int pattern_count,
1204                    int pattern_len);
1205 u32 ath9k_hw_wow_wakeup(struct ath_hw *ah);
1206 void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable);
1207 #else
1208 static inline int ath9k_hw_wow_apply_pattern(struct ath_hw *ah,
1209                          u8 *user_pattern,
1210                          u8 *user_mask,
1211                          int pattern_count,
1212                          int pattern_len)
1213 {
1214     return 0;
1215 }
1216 static inline u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
1217 {
1218     return 0;
1219 }
1220 static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
1221 {
1222 }
1223 #endif
1224 
1225 #define ATH9K_CLOCK_RATE_CCK        22
1226 #define ATH9K_CLOCK_RATE_5GHZ_OFDM  40
1227 #define ATH9K_CLOCK_RATE_2GHZ_OFDM  44
1228 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
1229 
1230 #endif
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