ath/ath9k/dynack.c

0001 /*
0002  * Copyright (c) 2014, Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
0003  *
0004  * Permission to use, copy, modify, and/or distribute this software for any
0005  * purpose with or without fee is hereby granted, provided that the above
0006  * copyright notice and this permission notice appear in all copies.
0007  *
0008  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0009  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0010  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0011  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0012  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0013  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0014  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0015  */
0016
0017 #include "ath9k.h"
0018 #include "hw.h"
0019 #include "dynack.h"
0020
0021 #define COMPUTE_TO      (5 * HZ)
0022 #define LATEACK_DELAY       (10 * HZ)
0023 #define EWMA_LEVEL      96
0024 #define EWMA_DIV        128
0025
0026 /**
0027  * ath_dynack_get_max_to - set max timeout according to channel width
0028  * @ah: ath hw
0029  *
0030  */
0031 static u32 ath_dynack_get_max_to(struct ath_hw *ah)
0032 {
0033     const struct ath9k_channel *chan = ah->curchan;
0034
0035     if (!chan)
0036         return 300;
0037
0038     if (IS_CHAN_HT40(chan))
0039         return 300;
0040     if (IS_CHAN_HALF_RATE(chan))
0041         return 750;
0042     if (IS_CHAN_QUARTER_RATE(chan))
0043         return 1500;
0044     return 600;
0045 }
0046
0047 /*
0048  * ath_dynack_ewma - EWMA (Exponentially Weighted Moving Average) calculation
0049  */
0050 static inline int ath_dynack_ewma(int old, int new)
0051 {
0052     if (old > 0)
0053         return (new * (EWMA_DIV - EWMA_LEVEL) +
0054             old * EWMA_LEVEL) / EWMA_DIV;
0055     else
0056         return new;
0057 }
0058
0059 /**
0060  * ath_dynack_get_sifs - get sifs time based on phy used
0061  * @ah: ath hw
0062  * @phy: phy used
0063  *
0064  */
0065 static inline u32 ath_dynack_get_sifs(struct ath_hw *ah, int phy)
0066 {
0067     u32 sifs = CCK_SIFS_TIME;
0068
0069     if (phy == WLAN_RC_PHY_OFDM) {
0070         if (IS_CHAN_QUARTER_RATE(ah->curchan))
0071             sifs = OFDM_SIFS_TIME_QUARTER;
0072         else if (IS_CHAN_HALF_RATE(ah->curchan))
0073             sifs = OFDM_SIFS_TIME_HALF;
0074         else
0075             sifs = OFDM_SIFS_TIME;
0076     }
0077     return sifs;
0078 }
0079
0080 /**
0081  * ath_dynack_bssidmask - filter out ACK frames based on BSSID mask
0082  * @ah: ath hw
0083  * @mac: receiver address
0084  */
0085 static inline bool ath_dynack_bssidmask(struct ath_hw *ah, const u8 *mac)
0086 {
0087     int i;
0088     struct ath_common *common = ath9k_hw_common(ah);
0089
0090     for (i = 0; i < ETH_ALEN; i++) {
0091         if ((common->macaddr[i] & common->bssidmask[i]) !=
0092             (mac[i] & common->bssidmask[i]))
0093             return false;
0094     }
0095
0096     return true;
0097 }
0098
0099 /**
0100  * ath_dynack_set_timeout - configure timeouts/slottime registers
0101  * @ah: ath hw
0102  * @to: timeout value
0103  *
0104  */
0105 static void ath_dynack_set_timeout(struct ath_hw *ah, int to)
0106 {
0107     struct ath_common *common = ath9k_hw_common(ah);
0108     int slottime = (to - 3) / 2;
0109
0110     ath_dbg(common, DYNACK, "ACK timeout %u slottime %u\n",
0111         to, slottime);
0112     ath9k_hw_setslottime(ah, slottime);
0113     ath9k_hw_set_ack_timeout(ah, to);
0114     ath9k_hw_set_cts_timeout(ah, to);
0115 }
0116
0117 /**
0118  * ath_dynack_compute_ackto - compute ACK timeout as the maximum STA timeout
0119  * @ah: ath hw
0120  *
0121  * should be called while holding qlock
0122  */
0123 static void ath_dynack_compute_ackto(struct ath_hw *ah)
0124 {
0125     struct ath_dynack *da = &ah->dynack;
0126     struct ath_node *an;
0127     int to = 0;
0128
0129     list_for_each_entry(an, &da->nodes, list)
0130         if (an->ackto > to)
0131             to = an->ackto;
0132
0133     if (to && da->ackto != to) {
0134         ath_dynack_set_timeout(ah, to);
0135         da->ackto = to;
0136     }
0137 }
0138
0139 /**
0140  * ath_dynack_compute_to - compute STA ACK timeout
0141  * @ah: ath hw
0142  *
0143  * should be called while holding qlock
0144  */
0145 static void ath_dynack_compute_to(struct ath_hw *ah)
0146 {
0147     struct ath_dynack *da = &ah->dynack;
0148     u32 ackto, ack_ts, max_to;
0149     struct ieee80211_sta *sta;
0150     struct ts_info *st_ts;
0151     struct ath_node *an;
0152     u8 *dst, *src;
0153
0154     rcu_read_lock();
0155
0156     max_to = ath_dynack_get_max_to(ah);
0157     while (da->st_rbf.h_rb != da->st_rbf.t_rb &&
0158            da->ack_rbf.h_rb != da->ack_rbf.t_rb) {
0159         ack_ts = da->ack_rbf.tstamp[da->ack_rbf.h_rb];
0160         st_ts = &da->st_rbf.ts[da->st_rbf.h_rb];
0161         dst = da->st_rbf.addr[da->st_rbf.h_rb].h_dest;
0162         src = da->st_rbf.addr[da->st_rbf.h_rb].h_src;
0163
0164         ath_dbg(ath9k_hw_common(ah), DYNACK,
0165             "ack_ts %u st_ts %u st_dur %u [%u-%u]\n",
0166             ack_ts, st_ts->tstamp, st_ts->dur,
0167             da->ack_rbf.h_rb, da->st_rbf.h_rb);
0168
0169         if (ack_ts > st_ts->tstamp + st_ts->dur) {
0170             ackto = ack_ts - st_ts->tstamp - st_ts->dur;
0171
0172             if (ackto < max_to) {
0173                 sta = ieee80211_find_sta_by_ifaddr(ah->hw, dst,
0174                                    src);
0175                 if (sta) {
0176                     an = (struct ath_node *)sta->drv_priv;
0177                     an->ackto = ath_dynack_ewma(an->ackto,
0178                                     ackto);
0179                     ath_dbg(ath9k_hw_common(ah), DYNACK,
0180                         "%pM to %d [%u]\n", dst,
0181                         an->ackto, ackto);
0182                     if (time_is_before_jiffies(da->lto)) {
0183                         ath_dynack_compute_ackto(ah);
0184                         da->lto = jiffies + COMPUTE_TO;
0185                     }
0186                 }
0187                 INCR(da->ack_rbf.h_rb, ATH_DYN_BUF);
0188             }
0189             INCR(da->st_rbf.h_rb, ATH_DYN_BUF);
0190         } else {
0191             INCR(da->ack_rbf.h_rb, ATH_DYN_BUF);
0192         }
0193     }
0194
0195     rcu_read_unlock();
0196 }
0197
0198 /**
0199  * ath_dynack_sample_tx_ts - status timestamp sampling method
0200  * @ah: ath hw
0201  * @skb: socket buffer
0202  * @ts: tx status info
0203  * @sta: station pointer
0204  *
0205  */
0206 void ath_dynack_sample_tx_ts(struct ath_hw *ah, struct sk_buff *skb,
0207                  struct ath_tx_status *ts,
0208                  struct ieee80211_sta *sta)
0209 {
0210     struct ieee80211_hdr *hdr;
0211     struct ath_dynack *da = &ah->dynack;
0212     struct ath_common *common = ath9k_hw_common(ah);
0213     struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
0214     u32 dur = ts->duration;
0215     u8 ridx;
0216
0217     if (!da->enabled || (info->flags & IEEE80211_TX_CTL_NO_ACK))
0218         return;
0219
0220     spin_lock_bh(&da->qlock);
0221
0222     hdr = (struct ieee80211_hdr *)skb->data;
0223
0224     /* late ACK */
0225     if (ts->ts_status & ATH9K_TXERR_XRETRY) {
0226         if (ieee80211_is_assoc_req(hdr->frame_control) ||
0227             ieee80211_is_assoc_resp(hdr->frame_control) ||
0228             ieee80211_is_auth(hdr->frame_control)) {
0229             u32 max_to = ath_dynack_get_max_to(ah);
0230
0231             ath_dbg(common, DYNACK, "late ack\n");
0232             ath_dynack_set_timeout(ah, max_to);
0233             if (sta) {
0234                 struct ath_node *an;
0235
0236                 an = (struct ath_node *)sta->drv_priv;
0237                 an->ackto = -1;
0238             }
0239             da->lto = jiffies + LATEACK_DELAY;
0240         }
0241
0242         spin_unlock_bh(&da->qlock);
0243         return;
0244     }
0245
0246     ridx = ts->ts_rateindex;
0247
0248     da->st_rbf.ts[da->st_rbf.t_rb].tstamp = ts->ts_tstamp;
0249
0250     /* ether_addr_copy() gives a false warning on gcc-10 so use memcpy()
0251      * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97490
0252      */
0253     memcpy(da->st_rbf.addr[da->st_rbf.t_rb].h_dest, hdr->addr1, ETH_ALEN);
0254     memcpy(da->st_rbf.addr[da->st_rbf.t_rb].h_src, hdr->addr2, ETH_ALEN);
0255
0256     if (!(info->status.rates[ridx].flags & IEEE80211_TX_RC_MCS)) {
0257         const struct ieee80211_rate *rate;
0258         struct ieee80211_tx_rate *rates = info->status.rates;
0259         u32 phy;
0260
0261         rate = &common->sbands[info->band].bitrates[rates[ridx].idx];
0262         if (info->band == NL80211_BAND_2GHZ &&
0263             !(rate->flags & IEEE80211_RATE_ERP_G))
0264             phy = WLAN_RC_PHY_CCK;
0265         else
0266             phy = WLAN_RC_PHY_OFDM;
0267
0268         dur -= ath_dynack_get_sifs(ah, phy);
0269     }
0270     da->st_rbf.ts[da->st_rbf.t_rb].dur = dur;
0271
0272     INCR(da->st_rbf.t_rb, ATH_DYN_BUF);
0273     if (da->st_rbf.t_rb == da->st_rbf.h_rb)
0274         INCR(da->st_rbf.h_rb, ATH_DYN_BUF);
0275
0276     ath_dbg(common, DYNACK, "{%pM} tx sample %u [dur %u][h %u-t %u]\n",
0277         hdr->addr1, ts->ts_tstamp, dur, da->st_rbf.h_rb,
0278         da->st_rbf.t_rb);
0279
0280     ath_dynack_compute_to(ah);
0281
0282     spin_unlock_bh(&da->qlock);
0283 }
0284 EXPORT_SYMBOL(ath_dynack_sample_tx_ts);
0285
0286 /**
0287  * ath_dynack_sample_ack_ts - ACK timestamp sampling method
0288  * @ah: ath hw
0289  * @skb: socket buffer
0290  * @ts: rx timestamp
0291  *
0292  */
0293 void ath_dynack_sample_ack_ts(struct ath_hw *ah, struct sk_buff *skb,
0294                   u32 ts)
0295 {
0296     struct ath_dynack *da = &ah->dynack;
0297     struct ath_common *common = ath9k_hw_common(ah);
0298     struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
0299
0300     if (!da->enabled || !ath_dynack_bssidmask(ah, hdr->addr1))
0301         return;
0302
0303     spin_lock_bh(&da->qlock);
0304     da->ack_rbf.tstamp[da->ack_rbf.t_rb] = ts;
0305
0306     INCR(da->ack_rbf.t_rb, ATH_DYN_BUF);
0307     if (da->ack_rbf.t_rb == da->ack_rbf.h_rb)
0308         INCR(da->ack_rbf.h_rb, ATH_DYN_BUF);
0309
0310     ath_dbg(common, DYNACK, "rx sample %u [h %u-t %u]\n",
0311         ts, da->ack_rbf.h_rb, da->ack_rbf.t_rb);
0312
0313     ath_dynack_compute_to(ah);
0314
0315     spin_unlock_bh(&da->qlock);
0316 }
0317 EXPORT_SYMBOL(ath_dynack_sample_ack_ts);
0318
0319 /**
0320  * ath_dynack_node_init - init ath_node related info
0321  * @ah: ath hw
0322  * @an: ath node
0323  *
0324  */
0325 void ath_dynack_node_init(struct ath_hw *ah, struct ath_node *an)
0326 {
0327     struct ath_dynack *da = &ah->dynack;
0328
0329     an->ackto = da->ackto;
0330
0331     spin_lock_bh(&da->qlock);
0332     list_add_tail(&an->list, &da->nodes);
0333     spin_unlock_bh(&da->qlock);
0334 }
0335 EXPORT_SYMBOL(ath_dynack_node_init);
0336
0337 /**
0338  * ath_dynack_node_deinit - deinit ath_node related info
0339  * @ah: ath hw
0340  * @an: ath node
0341  *
0342  */
0343 void ath_dynack_node_deinit(struct ath_hw *ah, struct ath_node *an)
0344 {
0345     struct ath_dynack *da = &ah->dynack;
0346
0347     spin_lock_bh(&da->qlock);
0348     list_del(&an->list);
0349     spin_unlock_bh(&da->qlock);
0350 }
0351 EXPORT_SYMBOL(ath_dynack_node_deinit);
0352
0353 /**
0354  * ath_dynack_reset - reset dynack processing
0355  * @ah: ath hw
0356  *
0357  */
0358 void ath_dynack_reset(struct ath_hw *ah)
0359 {
0360     struct ath_dynack *da = &ah->dynack;
0361     struct ath_node *an;
0362
0363     spin_lock_bh(&da->qlock);
0364
0365     da->lto = jiffies + COMPUTE_TO;
0366
0367     da->st_rbf.t_rb = 0;
0368     da->st_rbf.h_rb = 0;
0369     da->ack_rbf.t_rb = 0;
0370     da->ack_rbf.h_rb = 0;
0371
0372     da->ackto = ath_dynack_get_max_to(ah);
0373     list_for_each_entry(an, &da->nodes, list)
0374         an->ackto = da->ackto;
0375
0376     /* init acktimeout */
0377     ath_dynack_set_timeout(ah, da->ackto);
0378
0379     spin_unlock_bh(&da->qlock);
0380 }
0381 EXPORT_SYMBOL(ath_dynack_reset);
0382
0383 /**
0384  * ath_dynack_init - init dynack data structure
0385  * @ah: ath hw
0386  *
0387  */
0388 void ath_dynack_init(struct ath_hw *ah)
0389 {
0390     struct ath_dynack *da = &ah->dynack;
0391
0392     memset(da, 0, sizeof(struct ath_dynack));
0393
0394     spin_lock_init(&da->qlock);
0395     INIT_LIST_HEAD(&da->nodes);
0396     /* ackto = slottime + sifs + air delay */
0397     da->ackto = 9 + 16 + 64;
0398
0399     ah->hw->wiphy->features |= NL80211_FEATURE_ACKTO_ESTIMATION;
0400 }