ath/ath9k/debug.h

0001 /*
0002  * Copyright (c) 2008-2011 Atheros Communications Inc.
0003  *
0004  * Permission to use, copy, modify, and/or distribute this software for any
0005  * purpose with or without fee is hereby granted, provided that the above
0006  * copyright notice and this permission notice appear in all copies.
0007  *
0008  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0009  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0010  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0011  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0012  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0013  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0014  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0015  */
0016
0017 #ifndef DEBUG_H
0018 #define DEBUG_H
0019
0020 #include "hw.h"
0021 #include "dfs_debug.h"
0022
0023 struct ath_txq;
0024 struct ath_buf;
0025 struct fft_sample_tlv;
0026
0027 #ifdef CONFIG_ATH9K_DEBUGFS
0028 #define TX_STAT_INC(sc, q, c)    do { (sc)->debug.stats.txstats[q].c++; } while (0)
0029 #define RX_STAT_INC(sc, c)   do { (sc)->debug.stats.rxstats.c++; } while (0)
0030 #define RESET_STAT_INC(sc, type) do { (sc)->debug.stats.reset[type]++; } while (0)
0031 #define ANT_STAT_INC(sc, i, c)   do { (sc)->debug.stats.ant_stats[i].c++; } while (0)
0032 #define ANT_LNA_INC(sc, i, c)    do { (sc)->debug.stats.ant_stats[i].lna_recv_cnt[c]++; } while (0)
0033 #else
0034 #define TX_STAT_INC(sc, q, c)    do { (void)(sc); } while (0)
0035 #define RX_STAT_INC(sc, c)   do { (void)(sc); } while (0)
0036 #define RESET_STAT_INC(sc, type) do { (void)(sc); } while (0)
0037 #define ANT_STAT_INC(sc, i, c)   do { (void)(sc); } while (0)
0038 #define ANT_LNA_INC(sc, i, c)    do { (void)(sc); } while (0)
0039 #endif
0040
0041 enum ath_reset_type {
0042     RESET_TYPE_USER,
0043     RESET_TYPE_BB_HANG,
0044     RESET_TYPE_BB_WATCHDOG,
0045     RESET_TYPE_FATAL_INT,
0046     RESET_TYPE_TX_ERROR,
0047     RESET_TYPE_TX_GTT,
0048     RESET_TYPE_TX_HANG,
0049     RESET_TYPE_PLL_HANG,
0050     RESET_TYPE_MAC_HANG,
0051     RESET_TYPE_BEACON_STUCK,
0052     RESET_TYPE_MCI,
0053     RESET_TYPE_CALIBRATION,
0054     RESET_TX_DMA_ERROR,
0055     RESET_RX_DMA_ERROR,
0056     __RESET_TYPE_MAX
0057 };
0058
0059 #ifdef CONFIG_ATH9K_DEBUGFS
0060
0061 /**
0062  * struct ath_interrupt_stats - Contains statistics about interrupts
0063  * @total: Total no. of interrupts generated so far
0064  * @rxok: RX with no errors
0065  * @rxlp: RX with low priority RX
0066  * @rxhp: RX with high priority, uapsd only
0067  * @rxeol: RX with no more RXDESC available
0068  * @rxorn: RX FIFO overrun
0069  * @txok: TX completed at the requested rate
0070  * @txurn: TX FIFO underrun
0071  * @mib: MIB regs reaching its threshold
0072  * @rxphyerr: RX with phy errors
0073  * @rx_keycache_miss: RX with key cache misses
0074  * @swba: Software Beacon Alert
0075  * @bmiss: Beacon Miss
0076  * @bnr: Beacon Not Ready
0077  * @cst: Carrier Sense TImeout
0078  * @gtt: Global TX Timeout
0079  * @tim: RX beacon TIM occurrence
0080  * @cabend: RX End of CAB traffic
0081  * @dtimsync: DTIM sync lossage
0082  * @dtim: RX Beacon with DTIM
0083  * @bb_watchdog: Baseband watchdog
0084  * @tsfoor: TSF out of range, indicates that the corrected TSF received
0085  * from a beacon differs from the PCU's internal TSF by more than a
0086  * (programmable) threshold
0087  * @local_timeout: Internal bus timeout.
0088  * @mci: MCI interrupt, specific to MCI based BTCOEX chipsets
0089  * @gen_timer: Generic hardware timer interrupt
0090  */
0091 struct ath_interrupt_stats {
0092     u32 total;
0093     u32 rxok;
0094     u32 rxlp;
0095     u32 rxhp;
0096     u32 rxeol;
0097     u32 rxorn;
0098     u32 txok;
0099     u32 txeol;
0100     u32 txurn;
0101     u32 mib;
0102     u32 rxphyerr;
0103     u32 rx_keycache_miss;
0104     u32 swba;
0105     u32 bmiss;
0106     u32 bnr;
0107     u32 cst;
0108     u32 gtt;
0109     u32 tim;
0110     u32 cabend;
0111     u32 dtimsync;
0112     u32 dtim;
0113     u32 bb_watchdog;
0114     u32 tsfoor;
0115     u32 mci;
0116     u32 gen_timer;
0117
0118     /* Sync-cause stats */
0119     u32 sync_cause_all;
0120     u32 sync_rtc_irq;
0121     u32 sync_mac_irq;
0122     u32 eeprom_illegal_access;
0123     u32 apb_timeout;
0124     u32 pci_mode_conflict;
0125     u32 host1_fatal;
0126     u32 host1_perr;
0127     u32 trcv_fifo_perr;
0128     u32 radm_cpl_ep;
0129     u32 radm_cpl_dllp_abort;
0130     u32 radm_cpl_tlp_abort;
0131     u32 radm_cpl_ecrc_err;
0132     u32 radm_cpl_timeout;
0133     u32 local_timeout;
0134     u32 pm_access;
0135     u32 mac_awake;
0136     u32 mac_asleep;
0137     u32 mac_sleep_access;
0138 };
0139
0140
0141 /**
0142  * struct ath_tx_stats - Statistics about TX
0143  * @tx_pkts_all:  No. of total frames transmitted, including ones that
0144     may have had errors.
0145  * @tx_bytes_all:  No. of total bytes transmitted, including ones that
0146     may have had errors.
0147  * @queued: Total MPDUs (non-aggr) queued
0148  * @completed: Total MPDUs (non-aggr) completed
0149  * @a_aggr: Total no. of aggregates queued
0150  * @a_queued_hw: Total AMPDUs queued to hardware
0151  * @a_completed: Total AMPDUs completed
0152  * @a_retries: No. of AMPDUs retried (SW)
0153  * @a_xretries: No. of AMPDUs dropped due to xretries
0154  * @txerr_filtered: No. of frames with TXERR_FILT flag set.
0155  * @fifo_underrun: FIFO underrun occurrences
0156     Valid only for:
0157         - non-aggregate condition.
0158         - first packet of aggregate.
0159  * @xtxop: No. of frames filtered because of TXOP limit
0160  * @timer_exp: Transmit timer expiry
0161  * @desc_cfg_err: Descriptor configuration errors
0162  * @data_urn: TX data underrun errors
0163  * @delim_urn: TX delimiter underrun errors
0164  * @puttxbuf: Number of times hardware was given txbuf to write.
0165  * @txstart:  Number of times hardware was told to start tx.
0166  * @txprocdesc:  Number of times tx descriptor was processed
0167  * @txfailed:  Out-of-memory or other errors in xmit path.
0168  */
0169 struct ath_tx_stats {
0170     u32 tx_pkts_all;
0171     u32 tx_bytes_all;
0172     u32 queued;
0173     u32 completed;
0174     u32 xretries;
0175     u32 a_aggr;
0176     u32 a_queued_hw;
0177     u32 a_completed;
0178     u32 a_retries;
0179     u32 a_xretries;
0180     u32 txerr_filtered;
0181     u32 fifo_underrun;
0182     u32 xtxop;
0183     u32 timer_exp;
0184     u32 desc_cfg_err;
0185     u32 data_underrun;
0186     u32 delim_underrun;
0187     u32 puttxbuf;
0188     u32 txstart;
0189     u32 txprocdesc;
0190     u32 txfailed;
0191 };
0192
0193 /*
0194  * Various utility macros to print TX/Queue counters.
0195  */
0196 #define PR_QNUM(_n) sc->tx.txq_map[_n]->axq_qnum
0197 #define TXSTATS sc->debug.stats.txstats
0198 #define PR(str, elem)                           \
0199     do {                                \
0200         seq_printf(file, "%s%13u%11u%10u%10u\n", str,       \
0201                TXSTATS[PR_QNUM(IEEE80211_AC_BE)].elem,\
0202                TXSTATS[PR_QNUM(IEEE80211_AC_BK)].elem,\
0203                TXSTATS[PR_QNUM(IEEE80211_AC_VI)].elem,\
0204                TXSTATS[PR_QNUM(IEEE80211_AC_VO)].elem); \
0205     } while(0)
0206
0207 struct ath_rx_rate_stats {
0208     struct {
0209         u32 ht20_cnt;
0210         u32 ht40_cnt;
0211         u32 sgi_cnt;
0212         u32 lgi_cnt;
0213     } ht_stats[24];
0214
0215     struct {
0216         u32 ofdm_cnt;
0217     } ofdm_stats[8];
0218
0219     struct {
0220         u32 cck_lp_cnt;
0221         u32 cck_sp_cnt;
0222     } cck_stats[4];
0223 };
0224
0225 struct ath_airtime_stats {
0226     u32 rx_airtime;
0227     u32 tx_airtime;
0228 };
0229
0230 #define ANT_MAIN 0
0231 #define ANT_ALT  1
0232
0233 struct ath_antenna_stats {
0234     u32 recv_cnt;
0235     u32 rssi_avg;
0236     u32 lna_recv_cnt[4];
0237     u32 lna_attempt_cnt[4];
0238 };
0239
0240 struct ath_stats {
0241     struct ath_interrupt_stats istats;
0242     struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
0243     struct ath_rx_stats rxstats;
0244     struct ath_dfs_stats dfs_stats;
0245     struct ath_antenna_stats ant_stats[2];
0246     u32 reset[__RESET_TYPE_MAX];
0247 };
0248
0249 struct ath9k_debug {
0250     struct dentry *debugfs_phy;
0251     u32 regidx;
0252     struct ath_stats stats;
0253 };
0254
0255 int ath9k_init_debug(struct ath_hw *ah);
0256 void ath9k_deinit_debug(struct ath_softc *sc);
0257
0258 void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
0259 void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
0260                struct ath_tx_status *ts, struct ath_txq *txq,
0261                unsigned int flags);
0262 void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
0263 int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
0264                 struct ieee80211_vif *vif, int sset);
0265 void ath9k_get_et_stats(struct ieee80211_hw *hw,
0266             struct ieee80211_vif *vif,
0267             struct ethtool_stats *stats, u64 *data);
0268 void ath9k_get_et_strings(struct ieee80211_hw *hw,
0269               struct ieee80211_vif *vif,
0270               u32 sset, u8 *data);
0271 void ath9k_sta_add_debugfs(struct ieee80211_hw *hw,
0272                struct ieee80211_vif *vif,
0273                struct ieee80211_sta *sta,
0274                struct dentry *dir);
0275 void ath9k_debug_stat_ant(struct ath_softc *sc,
0276               struct ath_hw_antcomb_conf *div_ant_conf,
0277               int main_rssi_avg, int alt_rssi_avg);
0278 void ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause);
0279
0280 #else
0281
0282 static inline int ath9k_init_debug(struct ath_hw *ah)
0283 {
0284     return 0;
0285 }
0286
0287 static inline void ath9k_deinit_debug(struct ath_softc *sc)
0288 {
0289 }
0290 static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
0291                         enum ath9k_int status)
0292 {
0293 }
0294 static inline void ath_debug_stat_tx(struct ath_softc *sc,
0295                      struct ath_buf *bf,
0296                      struct ath_tx_status *ts,
0297                      struct ath_txq *txq,
0298                      unsigned int flags)
0299 {
0300 }
0301 static inline void ath_debug_stat_rx(struct ath_softc *sc,
0302                      struct ath_rx_status *rs)
0303 {
0304 }
0305 static inline void ath9k_debug_stat_ant(struct ath_softc *sc,
0306                     struct ath_hw_antcomb_conf *div_ant_conf,
0307                     int main_rssi_avg, int alt_rssi_avg)
0308 {
0309
0310 }
0311
0312 static inline void
0313 ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause)
0314 {
0315 }
0316
0317 #endif /* CONFIG_ATH9K_DEBUGFS */
0318
0319 #ifdef CONFIG_ATH9K_STATION_STATISTICS
0320 void ath_debug_rate_stats(struct ath_softc *sc,
0321               struct ath_rx_status *rs,
0322               struct sk_buff *skb);
0323 #else
0324 static inline void ath_debug_rate_stats(struct ath_softc *sc,
0325                     struct ath_rx_status *rs,
0326                     struct sk_buff *skb)
0327 {
0328 }
0329 #endif /* CONFIG_ATH9K_STATION_STATISTICS */
0330
0331 #endif /* DEBUG_H */