ath/ath9k/ar9003_wow.c

0001 /*
0002  * Copyright (c) 2012 Qualcomm Atheros, Inc.
0003  *
0004  * Permission to use, copy, modify, and/or distribute this software for any
0005  * purpose with or without fee is hereby granted, provided that the above
0006  * copyright notice and this permission notice appear in all copies.
0007  *
0008  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0009  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0010  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0011  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0012  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0013  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0014  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0015  */
0016
0017 #include <linux/export.h>
0018 #include "ath9k.h"
0019 #include "reg.h"
0020 #include "reg_wow.h"
0021 #include "hw-ops.h"
0022
0023 static void ath9k_hw_set_sta_powersave(struct ath_hw *ah)
0024 {
0025     if (!ath9k_hw_mci_is_enabled(ah))
0026         goto set;
0027     /*
0028      * If MCI is being used, set PWR_SAV only when MCI's
0029      * PS state is disabled.
0030      */
0031     if (ar9003_mci_state(ah, MCI_STATE_GET_WLAN_PS_STATE) != MCI_PS_DISABLE)
0032         return;
0033 set:
0034     REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
0035 }
0036
0037 static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah)
0038 {
0039     struct ath_common *common = ath9k_hw_common(ah);
0040
0041     ath9k_hw_set_sta_powersave(ah);
0042
0043     /* set rx disable bit */
0044     REG_WRITE(ah, AR_CR, AR_CR_RXD);
0045
0046     if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) {
0047         ath_err(common, "Failed to stop Rx DMA in 10ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
0048             REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
0049         return;
0050     }
0051
0052     if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
0053         if (!REG_READ(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL))
0054             REG_CLR_BIT(ah, AR_DIRECT_CONNECT, AR_DC_TSF2_ENABLE);
0055     } else if (AR_SREV_9485(ah)){
0056         if (!(REG_READ(ah, AR_NDP2_TIMER_MODE) &
0057               AR_GEN_TIMERS2_MODE_ENABLE_MASK))
0058             REG_CLR_BIT(ah, AR_DIRECT_CONNECT, AR_DC_TSF2_ENABLE);
0059     }
0060
0061     if (ath9k_hw_mci_is_enabled(ah))
0062         REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
0063
0064     REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT);
0065 }
0066
0067 static void ath9k_wow_create_keep_alive_pattern(struct ath_hw *ah)
0068 {
0069     struct ath_common *common = ath9k_hw_common(ah);
0070     u8 sta_mac_addr[ETH_ALEN], ap_mac_addr[ETH_ALEN];
0071     u32 ctl[13] = {0};
0072     u32 data_word[KAL_NUM_DATA_WORDS];
0073     u8 i;
0074     u32 wow_ka_data_word0;
0075
0076     memcpy(sta_mac_addr, common->macaddr, ETH_ALEN);
0077     memcpy(ap_mac_addr, common->curbssid, ETH_ALEN);
0078
0079     /* set the transmit buffer */
0080     ctl[0] = (KAL_FRAME_LEN | (MAX_RATE_POWER << 16));
0081     ctl[1] = 0;
0082     ctl[4] = 0;
0083     ctl[7] = (ah->txchainmask) << 2;
0084     ctl[2] = 0xf << 16; /* tx_tries 0 */
0085
0086     if (IS_CHAN_2GHZ(ah->curchan))
0087         ctl[3] = 0x1b;  /* CCK_1M */
0088     else
0089         ctl[3] = 0xb;   /* OFDM_6M */
0090
0091     for (i = 0; i < KAL_NUM_DESC_WORDS; i++)
0092         REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
0093
0094     data_word[0] = (KAL_FRAME_TYPE << 2) | (KAL_FRAME_SUB_TYPE << 4) |
0095                (KAL_TO_DS << 8) | (KAL_DURATION_ID << 16);
0096     data_word[1] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
0097                (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
0098     data_word[2] = (sta_mac_addr[1] << 24) | (sta_mac_addr[0] << 16) |
0099                (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
0100     data_word[3] = (sta_mac_addr[5] << 24) | (sta_mac_addr[4] << 16) |
0101                (sta_mac_addr[3] << 8) | (sta_mac_addr[2]);
0102     data_word[4] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
0103                (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
0104     data_word[5] = (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
0105
0106     if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565(ah)) {
0107         /*
0108          * AR9462 2.0 and AR9565 have an extra descriptor word
0109          * (time based discard) compared to other chips.
0110          */
0111         REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0);
0112         wow_ka_data_word0 = AR_WOW_TXBUF(13);
0113     } else {
0114         wow_ka_data_word0 = AR_WOW_TXBUF(12);
0115     }
0116
0117     for (i = 0; i < KAL_NUM_DATA_WORDS; i++)
0118         REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]);
0119 }
0120
0121 int ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
0122                    u8 *user_mask, int pattern_count,
0123                    int pattern_len)
0124 {
0125     int i;
0126     u32 pattern_val, mask_val;
0127     u32 set, clr;
0128
0129     if (pattern_count >= ah->wow.max_patterns)
0130         return -ENOSPC;
0131
0132     if (pattern_count < MAX_NUM_PATTERN_LEGACY)
0133         REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count));
0134     else
0135         REG_SET_BIT(ah, AR_MAC_PCU_WOW4, BIT(pattern_count - 8));
0136
0137     for (i = 0; i < MAX_PATTERN_SIZE; i += 4) {
0138         memcpy(&pattern_val, user_pattern, 4);
0139         REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i),
0140               pattern_val);
0141         user_pattern += 4;
0142     }
0143
0144     for (i = 0; i < MAX_PATTERN_MASK_SIZE; i += 4) {
0145         memcpy(&mask_val, user_mask, 4);
0146         REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val);
0147         user_mask += 4;
0148     }
0149
0150     if (pattern_count < MAX_NUM_PATTERN_LEGACY)
0151         ah->wow.wow_event_mask |=
0152             BIT(pattern_count + AR_WOW_PAT_FOUND_SHIFT);
0153     else
0154         ah->wow.wow_event_mask2 |=
0155             BIT((pattern_count - 8) + AR_WOW_PAT_FOUND_SHIFT);
0156
0157     if (pattern_count < 4) {
0158         set = (pattern_len & AR_WOW_LENGTH_MAX) <<
0159                AR_WOW_LEN1_SHIFT(pattern_count);
0160         clr = AR_WOW_LENGTH1_MASK(pattern_count);
0161         REG_RMW(ah, AR_WOW_LENGTH1, set, clr);
0162     } else if (pattern_count < 8) {
0163         set = (pattern_len & AR_WOW_LENGTH_MAX) <<
0164                AR_WOW_LEN2_SHIFT(pattern_count);
0165         clr = AR_WOW_LENGTH2_MASK(pattern_count);
0166         REG_RMW(ah, AR_WOW_LENGTH2, set, clr);
0167     } else if (pattern_count < 12) {
0168         set = (pattern_len & AR_WOW_LENGTH_MAX) <<
0169                AR_WOW_LEN3_SHIFT(pattern_count);
0170         clr = AR_WOW_LENGTH3_MASK(pattern_count);
0171         REG_RMW(ah, AR_WOW_LENGTH3, set, clr);
0172     } else if (pattern_count < MAX_NUM_PATTERN) {
0173         set = (pattern_len & AR_WOW_LENGTH_MAX) <<
0174                AR_WOW_LEN4_SHIFT(pattern_count);
0175         clr = AR_WOW_LENGTH4_MASK(pattern_count);
0176         REG_RMW(ah, AR_WOW_LENGTH4, set, clr);
0177     }
0178
0179     return 0;
0180 }
0181 EXPORT_SYMBOL(ath9k_hw_wow_apply_pattern);
0182
0183 u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
0184 {
0185     u32 wow_status = 0;
0186     u32 val = 0, rval;
0187
0188     /*
0189      * Read the WoW status register to know
0190      * the wakeup reason.
0191      */
0192     rval = REG_READ(ah, AR_WOW_PATTERN);
0193     val = AR_WOW_STATUS(rval);
0194
0195     /*
0196      * Mask only the WoW events that we have enabled. Sometimes
0197      * we have spurious WoW events from the AR_WOW_PATTERN
0198      * register. This mask will clean it up.
0199      */
0200     val &= ah->wow.wow_event_mask;
0201
0202     if (val) {
0203         if (val & AR_WOW_MAGIC_PAT_FOUND)
0204             wow_status |= AH_WOW_MAGIC_PATTERN_EN;
0205         if (AR_WOW_PATTERN_FOUND(val))
0206             wow_status |= AH_WOW_USER_PATTERN_EN;
0207         if (val & AR_WOW_KEEP_ALIVE_FAIL)
0208             wow_status |= AH_WOW_LINK_CHANGE;
0209         if (val & AR_WOW_BEACON_FAIL)
0210             wow_status |= AH_WOW_BEACON_MISS;
0211     }
0212
0213     rval = REG_READ(ah, AR_MAC_PCU_WOW4);
0214     val = AR_WOW_STATUS2(rval);
0215     val &= ah->wow.wow_event_mask2;
0216
0217     if (val) {
0218         if (AR_WOW2_PATTERN_FOUND(val))
0219             wow_status |= AH_WOW_USER_PATTERN_EN;
0220     }
0221
0222     /*
0223      * set and clear WOW_PME_CLEAR registers for the chip to
0224      * generate next wow signal.
0225      * disable D3 before accessing other registers ?
0226      */
0227
0228     /* do we need to check the bit value 0x01000000 (7-10) ?? */
0229     REG_RMW(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_WOW_PME_CLR,
0230         AR_PMCTRL_PWR_STATE_D1D3);
0231
0232     /*
0233      * Clear all events.
0234      */
0235     REG_WRITE(ah, AR_WOW_PATTERN,
0236           AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN)));
0237     REG_WRITE(ah, AR_MAC_PCU_WOW4,
0238           AR_WOW_CLEAR_EVENTS2(REG_READ(ah, AR_MAC_PCU_WOW4)));
0239
0240     /*
0241      * restore the beacon threshold to init value
0242      */
0243     REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
0244
0245     /*
0246      * Restore the way the PCI-E reset, Power-On-Reset, external
0247      * PCIE_POR_SHORT pins are tied to its original value.
0248      * Previously just before WoW sleep, we untie the PCI-E
0249      * reset to our Chip's Power On Reset so that any PCI-E
0250      * reset from the bus will not reset our chip
0251      */
0252     if (ah->is_pciexpress)
0253         ath9k_hw_configpcipowersave(ah, false);
0254
0255     if (AR_SREV_9462(ah) || AR_SREV_9565(ah) || AR_SREV_9485(ah)) {
0256         u32 dc = REG_READ(ah, AR_DIRECT_CONNECT);
0257
0258         if (!(dc & AR_DC_TSF2_ENABLE))
0259             ath9k_hw_gen_timer_start_tsf2(ah);
0260     }
0261
0262     ah->wow.wow_event_mask = 0;
0263     ah->wow.wow_event_mask2 = 0;
0264
0265     return wow_status;
0266 }
0267 EXPORT_SYMBOL(ath9k_hw_wow_wakeup);
0268
0269 static void ath9k_hw_wow_set_arwr_reg(struct ath_hw *ah)
0270 {
0271     u32 wa_reg;
0272
0273     if (!ah->is_pciexpress)
0274         return;
0275
0276     /*
0277      * We need to untie the internal POR (power-on-reset)
0278      * to the external PCI-E reset. We also need to tie
0279      * the PCI-E Phy reset to the PCI-E reset.
0280      */
0281     wa_reg = REG_READ(ah, AR_WA);
0282     wa_reg &= ~AR_WA_UNTIE_RESET_EN;
0283     wa_reg |= AR_WA_RESET_EN;
0284     wa_reg |= AR_WA_POR_SHORT;
0285
0286     REG_WRITE(ah, AR_WA, wa_reg);
0287 }
0288
0289 void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
0290 {
0291     u32 wow_event_mask;
0292     u32 keep_alive, magic_pattern, host_pm_ctrl;
0293
0294     wow_event_mask = ah->wow.wow_event_mask;
0295
0296     /*
0297      * AR_PMCTRL_HOST_PME_EN - Override PME enable in configuration
0298      *                         space and allow MAC to generate WoW anyway.
0299      *
0300      * AR_PMCTRL_PWR_PM_CTRL_ENA - ???
0301      *
0302      * AR_PMCTRL_AUX_PWR_DET - PCI core SYS_AUX_PWR_DET signal,
0303      *                         needs to be set for WoW in PCI mode.
0304      *
0305      * AR_PMCTRL_WOW_PME_CLR - WoW Clear Signal going to the MAC.
0306      *
0307      * Set the power states appropriately and enable PME.
0308      *
0309      * Set and clear WOW_PME_CLEAR for the chip
0310      * to generate next wow signal.
0311      */
0312     REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_HOST_PME_EN |
0313                          AR_PMCTRL_PWR_PM_CTRL_ENA |
0314                          AR_PMCTRL_AUX_PWR_DET |
0315                          AR_PMCTRL_WOW_PME_CLR);
0316     REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_WOW_PME_CLR);
0317
0318     /*
0319      * Random Backoff.
0320      *
0321      * 31:28 in AR_WOW_PATTERN : Indicates the number of bits used in the
0322      *                           contention window. For value N,
0323      *                           the random backoff will be selected between
0324      *                           0 and (2 ^ N) - 1.
0325      */
0326     REG_SET_BIT(ah, AR_WOW_PATTERN,
0327             AR_WOW_BACK_OFF_SHIFT(AR_WOW_PAT_BACKOFF));
0328
0329     /*
0330      * AIFS time, Slot time, Keep Alive count.
0331      */
0332     REG_SET_BIT(ah, AR_WOW_COUNT, AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) |
0333                           AR_WOW_SLOT_CNT(AR_WOW_CNT_SLOT_CNT) |
0334                           AR_WOW_KEEP_ALIVE_CNT(AR_WOW_CNT_KA_CNT));
0335     /*
0336      * Beacon timeout.
0337      */
0338     if (pattern_enable & AH_WOW_BEACON_MISS)
0339         REG_WRITE(ah, AR_WOW_BCN_TIMO, AR_WOW_BEACON_TIMO);
0340     else
0341         REG_WRITE(ah, AR_WOW_BCN_TIMO, AR_WOW_BEACON_TIMO_MAX);
0342
0343     /*
0344      * Keep alive timeout in ms.
0345      */
0346     if (!pattern_enable)
0347         REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, AR_WOW_KEEP_ALIVE_NEVER);
0348     else
0349         REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, KAL_TIMEOUT * 32);
0350
0351     /*
0352      * Keep alive delay in us.
0353      */
0354     REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY, KAL_DELAY * 1000);
0355
0356     /*
0357      * Create keep alive pattern to respond to beacons.
0358      */
0359     ath9k_wow_create_keep_alive_pattern(ah);
0360
0361     /*
0362      * Configure keep alive register.
0363      */
0364     keep_alive = REG_READ(ah, AR_WOW_KEEP_ALIVE);
0365
0366     /* Send keep alive timeouts anyway */
0367     keep_alive &= ~AR_WOW_KEEP_ALIVE_AUTO_DIS;
0368
0369     if (pattern_enable & AH_WOW_LINK_CHANGE) {
0370         keep_alive &= ~AR_WOW_KEEP_ALIVE_FAIL_DIS;
0371         wow_event_mask |= AR_WOW_KEEP_ALIVE_FAIL;
0372     } else {
0373         keep_alive |= AR_WOW_KEEP_ALIVE_FAIL_DIS;
0374     }
0375
0376     REG_WRITE(ah, AR_WOW_KEEP_ALIVE, keep_alive);
0377
0378     /*
0379      * We are relying on a bmiss failure, ensure we have
0380      * enough threshold to prevent false positives.
0381      */
0382     REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR,
0383               AR_WOW_BMISSTHRESHOLD);
0384
0385     if (pattern_enable & AH_WOW_BEACON_MISS) {
0386         wow_event_mask |= AR_WOW_BEACON_FAIL;
0387         REG_SET_BIT(ah, AR_WOW_BCN_EN, AR_WOW_BEACON_FAIL_EN);
0388     } else {
0389         REG_CLR_BIT(ah, AR_WOW_BCN_EN, AR_WOW_BEACON_FAIL_EN);
0390     }
0391
0392     /*
0393      * Enable the magic packet registers.
0394      */
0395     magic_pattern = REG_READ(ah, AR_WOW_PATTERN);
0396     magic_pattern |= AR_WOW_MAC_INTR_EN;
0397
0398     if (pattern_enable & AH_WOW_MAGIC_PATTERN_EN) {
0399         magic_pattern |= AR_WOW_MAGIC_EN;
0400         wow_event_mask |= AR_WOW_MAGIC_PAT_FOUND;
0401     } else {
0402         magic_pattern &= ~AR_WOW_MAGIC_EN;
0403     }
0404
0405     REG_WRITE(ah, AR_WOW_PATTERN, magic_pattern);
0406
0407     /*
0408      * Enable pattern matching for packets which are less
0409      * than 256 bytes.
0410      */
0411     REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B,
0412           AR_WOW_PATTERN_SUPPORTED);
0413
0414     /*
0415      * Set the power states appropriately and enable PME.
0416      */
0417     host_pm_ctrl = REG_READ(ah, AR_PCIE_PM_CTRL);
0418     host_pm_ctrl |= AR_PMCTRL_PWR_STATE_D1D3 |
0419             AR_PMCTRL_HOST_PME_EN |
0420             AR_PMCTRL_PWR_PM_CTRL_ENA;
0421     host_pm_ctrl &= ~AR_PCIE_PM_CTRL_ENA;
0422
0423     if (AR_SREV_9462(ah)) {
0424         /*
0425          * This is needed to prevent the chip waking up
0426          * the host within 3-4 seconds with certain
0427          * platform/BIOS.
0428          */
0429         host_pm_ctrl &= ~AR_PMCTRL_PWR_STATE_D1D3;
0430         host_pm_ctrl |= AR_PMCTRL_PWR_STATE_D1D3_REAL;
0431     }
0432
0433     REG_WRITE(ah, AR_PCIE_PM_CTRL, host_pm_ctrl);
0434
0435     /*
0436      * Enable sequence number generation when asleep.
0437      */
0438     REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
0439
0440     /* To bring down WOW power low margin */
0441     REG_SET_BIT(ah, AR_PCIE_PHY_REG3, BIT(13));
0442
0443     ath9k_hw_wow_set_arwr_reg(ah);
0444
0445     if (ath9k_hw_mci_is_enabled(ah))
0446         REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
0447
0448     /* HW WoW */
0449     REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, BIT(5));
0450
0451     ath9k_hw_set_powermode_wow_sleep(ah);
0452     ah->wow.wow_event_mask = wow_event_mask;
0453 }
0454 EXPORT_SYMBOL(ath9k_hw_wow_enable);