ath/ath9k/ar9003_mci.h

0001 /*
0002  * Copyright (c) 2010-2011 Atheros Communications Inc.
0003  *
0004  * Permission to use, copy, modify, and/or distribute this software for any
0005  * purpose with or without fee is hereby granted, provided that the above
0006  * copyright notice and this permission notice appear in all copies.
0007  *
0008  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0009  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0010  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0011  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0012  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0013  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0014  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0015  */
0016
0017 #ifndef AR9003_MCI_H
0018 #define AR9003_MCI_H
0019
0020 #define MCI_FLAG_DISABLE_TIMESTAMP      0x00000001      /* Disable time stamp */
0021 #define MCI_RECOVERY_DUR_TSF        (100 * 1000)    /* 100 ms */
0022
0023 /* Default remote BT device MCI COEX version */
0024 #define MCI_GPM_COEX_MAJOR_VERSION_DEFAULT  3
0025 #define MCI_GPM_COEX_MINOR_VERSION_DEFAULT  0
0026
0027 /* Local WLAN MCI COEX version */
0028 #define MCI_GPM_COEX_MAJOR_VERSION_WLAN     3
0029 #define MCI_GPM_COEX_MINOR_VERSION_WLAN     0
0030
0031 enum mci_gpm_coex_query_type {
0032     MCI_GPM_COEX_QUERY_BT_ALL_INFO      = BIT(0),
0033     MCI_GPM_COEX_QUERY_BT_TOPOLOGY      = BIT(1),
0034     MCI_GPM_COEX_QUERY_BT_DEBUG         = BIT(2),
0035 };
0036
0037 enum mci_gpm_coex_halt_bt_gpm {
0038     MCI_GPM_COEX_BT_GPM_UNHALT,
0039     MCI_GPM_COEX_BT_GPM_HALT
0040 };
0041
0042 enum mci_gpm_coex_bt_update_flags_op {
0043     MCI_GPM_COEX_BT_FLAGS_READ,
0044     MCI_GPM_COEX_BT_FLAGS_SET,
0045     MCI_GPM_COEX_BT_FLAGS_CLEAR
0046 };
0047
0048 #define MCI_NUM_BT_CHANNELS     79
0049
0050 #define MCI_BT_MCI_FLAGS_UPDATE_CORR          0x00000002
0051 #define MCI_BT_MCI_FLAGS_UPDATE_HDR           0x00000004
0052 #define MCI_BT_MCI_FLAGS_UPDATE_PLD           0x00000008
0053 #define MCI_BT_MCI_FLAGS_LNA_CTRL             0x00000010
0054 #define MCI_BT_MCI_FLAGS_DEBUG                0x00000020
0055 #define MCI_BT_MCI_FLAGS_SCHED_MSG            0x00000040
0056 #define MCI_BT_MCI_FLAGS_CONT_MSG             0x00000080
0057 #define MCI_BT_MCI_FLAGS_COEX_GPM             0x00000100
0058 #define MCI_BT_MCI_FLAGS_CPU_INT_MSG          0x00000200
0059 #define MCI_BT_MCI_FLAGS_MCI_MODE             0x00000400
0060 #define MCI_BT_MCI_FLAGS_AR9462_MODE          0x00001000
0061 #define MCI_BT_MCI_FLAGS_OTHER                0x00010000
0062
0063 #define MCI_DEFAULT_BT_MCI_FLAGS              0x00011dde
0064
0065 #define MCI_TOGGLE_BT_MCI_FLAGS  (MCI_BT_MCI_FLAGS_UPDATE_CORR | \
0066                   MCI_BT_MCI_FLAGS_UPDATE_HDR  | \
0067                   MCI_BT_MCI_FLAGS_UPDATE_PLD  | \
0068                   MCI_BT_MCI_FLAGS_MCI_MODE)
0069
0070 #define MCI_2G_FLAGS_CLEAR_MASK   0x00000000
0071 #define MCI_2G_FLAGS_SET_MASK     MCI_TOGGLE_BT_MCI_FLAGS
0072 #define MCI_2G_FLAGS              MCI_DEFAULT_BT_MCI_FLAGS
0073
0074 #define MCI_5G_FLAGS_CLEAR_MASK   MCI_TOGGLE_BT_MCI_FLAGS
0075 #define MCI_5G_FLAGS_SET_MASK     0x00000000
0076 #define MCI_5G_FLAGS              (MCI_DEFAULT_BT_MCI_FLAGS & \
0077                    ~MCI_TOGGLE_BT_MCI_FLAGS)
0078
0079 /*
0080  * Default value for AR9462 is 0x00002201
0081  */
0082 #define ATH_MCI_CONFIG_CONCUR_TX            0x00000003
0083 #define ATH_MCI_CONFIG_MCI_OBS_MCI          0x00000004
0084 #define ATH_MCI_CONFIG_MCI_OBS_TXRX         0x00000008
0085 #define ATH_MCI_CONFIG_MCI_OBS_BT           0x00000010
0086 #define ATH_MCI_CONFIG_DISABLE_MCI_CAL      0x00000020
0087 #define ATH_MCI_CONFIG_DISABLE_OSLA         0x00000040
0088 #define ATH_MCI_CONFIG_DISABLE_FTP_STOMP    0x00000080
0089 #define ATH_MCI_CONFIG_AGGR_THRESH          0x00000700
0090 #define ATH_MCI_CONFIG_AGGR_THRESH_S        8
0091 #define ATH_MCI_CONFIG_DISABLE_AGGR_THRESH  0x00000800
0092 #define ATH_MCI_CONFIG_CLK_DIV              0x00003000
0093 #define ATH_MCI_CONFIG_CLK_DIV_S            12
0094 #define ATH_MCI_CONFIG_DISABLE_TUNING       0x00004000
0095 #define ATH_MCI_CONFIG_DISABLE_AIC          0x00008000
0096 #define ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN     0x007f0000
0097 #define ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN_S   16
0098 #define ATH_MCI_CONFIG_NO_QUIET_ACK         0x00800000
0099 #define ATH_MCI_CONFIG_NO_QUIET_ACK_S       23
0100 #define ATH_MCI_CONFIG_ANT_ARCH             0x07000000
0101 #define ATH_MCI_CONFIG_ANT_ARCH_S           24
0102 #define ATH_MCI_CONFIG_FORCE_QUIET_ACK      0x08000000
0103 #define ATH_MCI_CONFIG_FORCE_QUIET_ACK_S    27
0104 #define ATH_MCI_CONFIG_FORCE_2CHAIN_ACK     0x10000000
0105 #define ATH_MCI_CONFIG_MCI_STAT_DBG         0x20000000
0106 #define ATH_MCI_CONFIG_MCI_WEIGHT_DBG       0x40000000
0107 #define ATH_MCI_CONFIG_DISABLE_MCI          0x80000000
0108
0109 #define ATH_MCI_CONFIG_MCI_OBS_MASK     (ATH_MCI_CONFIG_MCI_OBS_MCI  | \
0110                      ATH_MCI_CONFIG_MCI_OBS_TXRX | \
0111                      ATH_MCI_CONFIG_MCI_OBS_BT)
0112
0113 #define ATH_MCI_CONFIG_MCI_OBS_GPIO     0x0000002F
0114
0115 #define ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_NON_SHARED 0x00
0116 #define ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_SHARED     0x01
0117 #define ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_NON_SHARED 0x02
0118 #define ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_SHARED     0x03
0119 #define ATH_MCI_ANT_ARCH_3_ANT                   0x04
0120
0121 #define MCI_ANT_ARCH_PA_LNA_SHARED(mci)                 \
0122     ((MS(mci->config, ATH_MCI_CONFIG_ANT_ARCH) == ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_SHARED) || \
0123      (MS(mci->config, ATH_MCI_CONFIG_ANT_ARCH) == ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_SHARED))
0124
0125 enum mci_message_header {       /* length of payload */
0126     MCI_LNA_CTRL     = 0x10,        /* len = 0 */
0127     MCI_CONT_NACK    = 0x20,        /* len = 0 */
0128     MCI_CONT_INFO    = 0x30,        /* len = 4 */
0129     MCI_CONT_RST     = 0x40,        /* len = 0 */
0130     MCI_SCHD_INFO    = 0x50,        /* len = 16 */
0131     MCI_CPU_INT      = 0x60,        /* len = 4 */
0132     MCI_SYS_WAKING   = 0x70,        /* len = 0 */
0133     MCI_GPM          = 0x80,        /* len = 16 */
0134     MCI_LNA_INFO     = 0x90,        /* len = 1 */
0135     MCI_LNA_STATE    = 0x94,
0136     MCI_LNA_TAKE     = 0x98,
0137     MCI_LNA_TRANS    = 0x9c,
0138     MCI_SYS_SLEEPING = 0xa0,        /* len = 0 */
0139     MCI_REQ_WAKE     = 0xc0,        /* len = 0 */
0140     MCI_DEBUG_16     = 0xfe,        /* len = 2 */
0141     MCI_REMOTE_RESET = 0xff         /* len = 16 */
0142 };
0143
0144 enum ath_mci_gpm_coex_profile_type {
0145     MCI_GPM_COEX_PROFILE_UNKNOWN,
0146     MCI_GPM_COEX_PROFILE_RFCOMM,
0147     MCI_GPM_COEX_PROFILE_A2DP,
0148     MCI_GPM_COEX_PROFILE_HID,
0149     MCI_GPM_COEX_PROFILE_BNEP,
0150     MCI_GPM_COEX_PROFILE_VOICE,
0151     MCI_GPM_COEX_PROFILE_A2DPVO,
0152     MCI_GPM_COEX_PROFILE_MAX
0153 };
0154
0155 /* MCI GPM/Coex opcode/type definitions */
0156 enum {
0157     MCI_GPM_COEX_W_GPM_PAYLOAD      = 1,
0158     MCI_GPM_COEX_B_GPM_TYPE         = 4,
0159     MCI_GPM_COEX_B_GPM_OPCODE       = 5,
0160     /* MCI_GPM_WLAN_CAL_REQ, MCI_GPM_WLAN_CAL_DONE */
0161     MCI_GPM_WLAN_CAL_W_SEQUENCE     = 2,
0162
0163     /* MCI_GPM_COEX_VERSION_QUERY */
0164     /* MCI_GPM_COEX_VERSION_RESPONSE */
0165     MCI_GPM_COEX_B_MAJOR_VERSION    = 6,
0166     MCI_GPM_COEX_B_MINOR_VERSION    = 7,
0167     /* MCI_GPM_COEX_STATUS_QUERY */
0168     MCI_GPM_COEX_B_BT_BITMAP        = 6,
0169     MCI_GPM_COEX_B_WLAN_BITMAP      = 7,
0170     /* MCI_GPM_COEX_HALT_BT_GPM */
0171     MCI_GPM_COEX_B_HALT_STATE       = 6,
0172     /* MCI_GPM_COEX_WLAN_CHANNELS */
0173     MCI_GPM_COEX_B_CHANNEL_MAP      = 6,
0174     /* MCI_GPM_COEX_BT_PROFILE_INFO */
0175     MCI_GPM_COEX_B_PROFILE_TYPE     = 6,
0176     MCI_GPM_COEX_B_PROFILE_LINKID   = 7,
0177     MCI_GPM_COEX_B_PROFILE_STATE    = 8,
0178     MCI_GPM_COEX_B_PROFILE_ROLE     = 9,
0179     MCI_GPM_COEX_B_PROFILE_RATE     = 10,
0180     MCI_GPM_COEX_B_PROFILE_VOTYPE   = 11,
0181     MCI_GPM_COEX_H_PROFILE_T        = 12,
0182     MCI_GPM_COEX_B_PROFILE_W        = 14,
0183     MCI_GPM_COEX_B_PROFILE_A        = 15,
0184     /* MCI_GPM_COEX_BT_STATUS_UPDATE */
0185     MCI_GPM_COEX_B_STATUS_TYPE      = 6,
0186     MCI_GPM_COEX_B_STATUS_LINKID    = 7,
0187     MCI_GPM_COEX_B_STATUS_STATE     = 8,
0188     /* MCI_GPM_COEX_BT_UPDATE_FLAGS */
0189     MCI_GPM_COEX_W_BT_FLAGS         = 6,
0190     MCI_GPM_COEX_B_BT_FLAGS_OP      = 10
0191 };
0192
0193 enum mci_gpm_subtype {
0194     MCI_GPM_BT_CAL_REQ      = 0,
0195     MCI_GPM_BT_CAL_GRANT    = 1,
0196     MCI_GPM_BT_CAL_DONE     = 2,
0197     MCI_GPM_WLAN_CAL_REQ    = 3,
0198     MCI_GPM_WLAN_CAL_GRANT  = 4,
0199     MCI_GPM_WLAN_CAL_DONE   = 5,
0200     MCI_GPM_COEX_AGENT      = 0x0c,
0201     MCI_GPM_RSVD_PATTERN    = 0xfe,
0202     MCI_GPM_RSVD_PATTERN32  = 0xfefefefe,
0203     MCI_GPM_BT_DEBUG        = 0xff
0204 };
0205
0206 enum mci_bt_state {
0207     MCI_BT_SLEEP,
0208     MCI_BT_AWAKE,
0209     MCI_BT_CAL_START,
0210     MCI_BT_CAL
0211 };
0212
0213 enum mci_ps_state {
0214     MCI_PS_DISABLE,
0215     MCI_PS_ENABLE,
0216     MCI_PS_ENABLE_OFF,
0217     MCI_PS_ENABLE_ON
0218 };
0219
0220 /* Type of state query */
0221 enum mci_state_type {
0222     MCI_STATE_ENABLE,
0223     MCI_STATE_INIT_GPM_OFFSET,
0224     MCI_STATE_CHECK_GPM_OFFSET,
0225     MCI_STATE_NEXT_GPM_OFFSET,
0226     MCI_STATE_LAST_GPM_OFFSET,
0227     MCI_STATE_BT,
0228     MCI_STATE_SET_BT_SLEEP,
0229     MCI_STATE_SET_BT_AWAKE,
0230     MCI_STATE_SET_BT_CAL_START,
0231     MCI_STATE_SET_BT_CAL,
0232     MCI_STATE_LAST_SCHD_MSG_OFFSET,
0233     MCI_STATE_REMOTE_SLEEP,
0234     MCI_STATE_CONT_STATUS,
0235     MCI_STATE_RESET_REQ_WAKE,
0236     MCI_STATE_SEND_WLAN_COEX_VERSION,
0237     MCI_STATE_SET_BT_COEX_VERSION,
0238     MCI_STATE_SEND_WLAN_CHANNELS,
0239     MCI_STATE_SEND_VERSION_QUERY,
0240     MCI_STATE_SEND_STATUS_QUERY,
0241     MCI_STATE_NEED_FLUSH_BT_INFO,
0242     MCI_STATE_SET_CONCUR_TX_PRI,
0243     MCI_STATE_RECOVER_RX,
0244     MCI_STATE_NEED_FTP_STOMP,
0245     MCI_STATE_NEED_TUNING,
0246     MCI_STATE_NEED_STAT_DEBUG,
0247     MCI_STATE_SHARED_CHAIN_CONCUR_TX,
0248     MCI_STATE_AIC_CAL,
0249     MCI_STATE_AIC_START,
0250     MCI_STATE_AIC_CAL_RESET,
0251     MCI_STATE_AIC_CAL_SINGLE,
0252     MCI_STATE_IS_AR9462,
0253     MCI_STATE_IS_AR9565_1ANT,
0254     MCI_STATE_IS_AR9565_2ANT,
0255     MCI_STATE_WLAN_WEAK_SIGNAL,
0256     MCI_STATE_SET_WLAN_PS_STATE,
0257     MCI_STATE_GET_WLAN_PS_STATE,
0258     MCI_STATE_DEBUG,
0259     MCI_STATE_STAT_DEBUG,
0260     MCI_STATE_ALLOW_FCS,
0261     MCI_STATE_SET_2G_CONTENTION,
0262     MCI_STATE_MAX
0263 };
0264
0265 enum mci_gpm_coex_opcode {
0266     MCI_GPM_COEX_VERSION_QUERY,
0267     MCI_GPM_COEX_VERSION_RESPONSE,
0268     MCI_GPM_COEX_STATUS_QUERY,
0269     MCI_GPM_COEX_HALT_BT_GPM,
0270     MCI_GPM_COEX_WLAN_CHANNELS,
0271     MCI_GPM_COEX_BT_PROFILE_INFO,
0272     MCI_GPM_COEX_BT_STATUS_UPDATE,
0273     MCI_GPM_COEX_BT_UPDATE_FLAGS,
0274     MCI_GPM_COEX_NOOP,
0275 };
0276
0277 #define MCI_GPM_NOMORE  0
0278 #define MCI_GPM_MORE    1
0279 #define MCI_GPM_INVALID 0xffffffff
0280
0281 #define MCI_GPM_RECYCLE(_p_gpm) do {              \
0282     *(((u32 *)_p_gpm) + MCI_GPM_COEX_W_GPM_PAYLOAD) = \
0283                 MCI_GPM_RSVD_PATTERN32;   \
0284 } while (0)
0285
0286 #define MCI_GPM_TYPE(_p_gpm)    \
0287     (*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) & 0xff)
0288
0289 #define MCI_GPM_OPCODE(_p_gpm)  \
0290     (*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) & 0xff)
0291
0292 #define MCI_GPM_SET_CAL_TYPE(_p_gpm, _cal_type) do {               \
0293     *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_cal_type) & 0xff;\
0294 } while (0)
0295
0296 #define MCI_GPM_SET_TYPE_OPCODE(_p_gpm, _type, _opcode) do {           \
0297     *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_type) & 0xff;    \
0298     *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) = (_opcode) & 0xff;\
0299 } while (0)
0300
0301 #define MCI_GPM_IS_CAL_TYPE(_type) ((_type) <= MCI_GPM_WLAN_CAL_DONE)
0302
0303 /*
0304  * Functions that are available to the MCI driver core.
0305  */
0306 bool ar9003_mci_send_message(struct ath_hw *ah, u8 header, u32 flag,
0307                  u32 *payload, u8 len, bool wait_done,
0308                  bool check_bt);
0309 u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type);
0310 int ar9003_mci_setup(struct ath_hw *ah, u32 gpm_addr, void *gpm_buf,
0311              u16 len, u32 sched_addr);
0312 void ar9003_mci_cleanup(struct ath_hw *ah);
0313 void ar9003_mci_get_interrupt(struct ath_hw *ah, u32 *raw_intr,
0314                   u32 *rx_msg_intr);
0315 u32 ar9003_mci_get_next_gpm_offset(struct ath_hw *ah, u32 *more);
0316 void ar9003_mci_set_bt_version(struct ath_hw *ah, u8 major, u8 minor);
0317 void ar9003_mci_send_wlan_channels(struct ath_hw *ah);
0318 /*
0319  * These functions are used by ath9k_hw.
0320  */
0321
0322 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
0323
0324 void ar9003_mci_stop_bt(struct ath_hw *ah, bool save_fullsleep);
0325 void ar9003_mci_init_cal_req(struct ath_hw *ah, bool *is_reusable);
0326 void ar9003_mci_init_cal_done(struct ath_hw *ah);
0327 void ar9003_mci_set_full_sleep(struct ath_hw *ah);
0328 void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool force);
0329 void ar9003_mci_check_bt(struct ath_hw *ah);
0330 bool ar9003_mci_start_reset(struct ath_hw *ah, struct ath9k_channel *chan);
0331 int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan,
0332              struct ath9k_hw_cal_data *caldata);
0333 int ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
0334              bool is_full_sleep);
0335 void ar9003_mci_get_isr(struct ath_hw *ah, enum ath9k_int *masked);
0336 void ar9003_mci_bt_gain_ctrl(struct ath_hw *ah);
0337 void ar9003_mci_set_power_awake(struct ath_hw *ah);
0338 void ar9003_mci_check_gpm_offset(struct ath_hw *ah);
0339 u16 ar9003_mci_get_max_txpower(struct ath_hw *ah, u8 ctlmode);
0340
0341 #else
0342
0343 static inline void ar9003_mci_stop_bt(struct ath_hw *ah, bool save_fullsleep)
0344 {
0345 }
0346 static inline void ar9003_mci_init_cal_req(struct ath_hw *ah, bool *is_reusable)
0347 {
0348 }
0349 static inline void ar9003_mci_init_cal_done(struct ath_hw *ah)
0350 {
0351 }
0352 static inline void ar9003_mci_set_full_sleep(struct ath_hw *ah)
0353 {
0354 }
0355 static inline void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool wait_done)
0356 {
0357 }
0358 static inline void ar9003_mci_check_bt(struct ath_hw *ah)
0359 {
0360 }
0361 static inline bool ar9003_mci_start_reset(struct ath_hw *ah, struct ath9k_channel *chan)
0362 {
0363     return false;
0364 }
0365 static inline int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan,
0366                        struct ath9k_hw_cal_data *caldata)
0367 {
0368     return 0;
0369 }
0370 static inline void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
0371                     bool is_full_sleep)
0372 {
0373 }
0374 static inline void ar9003_mci_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
0375 {
0376 }
0377 static inline void ar9003_mci_bt_gain_ctrl(struct ath_hw *ah)
0378 {
0379 }
0380 static inline void ar9003_mci_set_power_awake(struct ath_hw *ah)
0381 {
0382 }
0383 static inline void ar9003_mci_check_gpm_offset(struct ath_hw *ah)
0384 {
0385 }
0386 static inline u16 ar9003_mci_get_max_txpower(struct ath_hw *ah, u8 ctlmode)
0387 {
0388     return -1;
0389 }
0390 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
0391
0392 #endif