ath/ath9k/ar9003_mac.h

0001 /*
0002  * Copyright (c) 2010-2011 Atheros Communications Inc.
0003  *
0004  * Permission to use, copy, modify, and/or distribute this software for any
0005  * purpose with or without fee is hereby granted, provided that the above
0006  * copyright notice and this permission notice appear in all copies.
0007  *
0008  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0009  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0010  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0011  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0012  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0013  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0014  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0015  */
0016
0017 #ifndef AR9003_MAC_H
0018 #define AR9003_MAC_H
0019
0020 #define AR_DescId   0xffff0000
0021 #define AR_DescId_S 16
0022 #define AR_CtrlStat 0x00004000
0023 #define AR_CtrlStat_S   14
0024 #define AR_TxRxDesc 0x00008000
0025 #define AR_TxRxDesc_S   15
0026 #define AR_TxQcuNum 0x00000f00
0027 #define AR_TxQcuNum_S   8
0028
0029 #define AR_BufLen   0x0fff0000
0030 #define AR_BufLen_S 16
0031
0032 #define AR_TxDescId 0xffff0000
0033 #define AR_TxDescId_S   16
0034 #define AR_TxPtrChkSum  0x0000ffff
0035
0036 #define AR_LowRxChain   0x00004000
0037
0038 #define AR_Not_Sounding 0x20000000
0039
0040 /* ctl 12 */
0041 #define AR_PAPRDChainMask   0x00000e00
0042 #define AR_PAPRDChainMask_S 9
0043
0044 #define MAP_ISR_S2_CST          6
0045 #define MAP_ISR_S2_GTT          6
0046 #define MAP_ISR_S2_TIM          3
0047 #define MAP_ISR_S2_CABEND       0
0048 #define MAP_ISR_S2_DTIMSYNC     7
0049 #define MAP_ISR_S2_DTIM         7
0050 #define MAP_ISR_S2_TSFOOR       4
0051 #define MAP_ISR_S2_BB_WATCHDOG  6
0052
0053 #define AR9003TXC_CONST(_ds) ((const struct ar9003_txc *) _ds)
0054
0055 struct ar9003_rxs {
0056     u32 ds_info;
0057     u32 status1;
0058     u32 status2;
0059     u32 status3;
0060     u32 status4;
0061     u32 status5;
0062     u32 status6;
0063     u32 status7;
0064     u32 status8;
0065     u32 status9;
0066     u32 status10;
0067     u32 status11;
0068 } __packed __aligned(4);
0069
0070 /* Transmit Control Descriptor */
0071 struct ar9003_txc {
0072     u32 info;   /* descriptor information */
0073     u32 link;   /* link pointer */
0074     u32 data0;  /* data pointer to 1st buffer */
0075     u32 ctl3;   /* DMA control 3  */
0076     u32 data1;  /* data pointer to 2nd buffer */
0077     u32 ctl5;   /* DMA control 5  */
0078     u32 data2;  /* data pointer to 3rd buffer */
0079     u32 ctl7;   /* DMA control 7  */
0080     u32 data3;  /* data pointer to 4th buffer */
0081     u32 ctl9;   /* DMA control 9  */
0082     u32 ctl10;  /* DMA control 10 */
0083     u32 ctl11;  /* DMA control 11 */
0084     u32 ctl12;  /* DMA control 12 */
0085     u32 ctl13;  /* DMA control 13 */
0086     u32 ctl14;  /* DMA control 14 */
0087     u32 ctl15;  /* DMA control 15 */
0088     u32 ctl16;  /* DMA control 16 */
0089     u32 ctl17;  /* DMA control 17 */
0090     u32 ctl18;  /* DMA control 18 */
0091     u32 ctl19;  /* DMA control 19 */
0092     u32 ctl20;  /* DMA control 20 */
0093     u32 ctl21;  /* DMA control 21 */
0094     u32 ctl22;  /* DMA control 22 */
0095     u32 ctl23;  /* DMA control 23 */
0096     u32 pad[8]; /* pad to cache line (128 bytes/32 dwords) */
0097 } __packed __aligned(4);
0098
0099 struct ar9003_txs {
0100     u32 ds_info;
0101     u32 status1;
0102     u32 status2;
0103     u32 status3;
0104     u32 status4;
0105     u32 status5;
0106     u32 status6;
0107     u32 status7;
0108     u32 status8;
0109 } __packed __aligned(4);
0110
0111 void ar9003_hw_attach_mac_ops(struct ath_hw *hw);
0112 void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size);
0113 void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
0114                 enum ath9k_rx_qtype qtype);
0115
0116 int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah,
0117                  struct ath_rx_status *rxs,
0118                  void *buf_addr);
0119 void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah);
0120 void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
0121                    u32 ts_paddr_start,
0122                    u16 size);
0123 #endif