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OSCL-LXR
 
 

     

0001 /*
0002  * Copyright (c) 2008-2011 Atheros Communications Inc.
0003  *
0004  * Permission to use, copy, modify, and/or distribute this software for any
0005  * purpose with or without fee is hereby granted, provided that the above
0006  * copyright notice and this permission notice appear in all copies.
0007  *
0008  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0009  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0010  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0011  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0012  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0013  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0014  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0015  */
0016 
0017 #include "hw.h"
0018 #include "ar9003_mac.h"
0019 #include "ar9003_2p2_initvals.h"
0020 #include "ar9003_buffalo_initvals.h"
0021 #include "ar9485_initvals.h"
0022 #include "ar9340_initvals.h"
0023 #include "ar9330_1p1_initvals.h"
0024 #include "ar9330_1p2_initvals.h"
0025 #include "ar955x_1p0_initvals.h"
0026 #include "ar9580_1p0_initvals.h"
0027 #include "ar9462_2p0_initvals.h"
0028 #include "ar9462_2p1_initvals.h"
0029 #include "ar9565_1p0_initvals.h"
0030 #include "ar9565_1p1_initvals.h"
0031 #include "ar953x_initvals.h"
0032 #include "ar956x_initvals.h"
0033 
0034 /* General hardware code for the AR9003 hadware family */
0035 
0036 /*
0037  * The AR9003 family uses a new INI format (pre, core, post
0038  * arrays per subsystem). This provides support for the
0039  * AR9003 2.2 chipsets.
0040  */
0041 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
0042 {
0043     if (AR_SREV_9330_11(ah)) {
0044         /* mac */
0045         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
0046                 ar9331_1p1_mac_core);
0047         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
0048                 ar9331_1p1_mac_postamble);
0049 
0050         /* bb */
0051         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
0052                 ar9331_1p1_baseband_core);
0053         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
0054                 ar9331_1p1_baseband_postamble);
0055 
0056         /* radio */
0057         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
0058                 ar9331_1p1_radio_core);
0059 
0060         /* soc */
0061         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
0062                 ar9331_1p1_soc_preamble);
0063         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
0064                 ar9331_1p1_soc_postamble);
0065 
0066         /* rx/tx gain */
0067         INIT_INI_ARRAY(&ah->iniModesRxGain,
0068                 ar9331_common_rx_gain_1p1);
0069         INIT_INI_ARRAY(&ah->iniModesTxGain,
0070                 ar9331_modes_lowest_ob_db_tx_gain_1p1);
0071 
0072         /* Japan 2484 Mhz CCK */
0073         INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
0074                    ar9331_1p1_baseband_core_txfir_coeff_japan_2484);
0075 
0076         /* additional clock settings */
0077         if (ah->is_clk_25mhz)
0078             INIT_INI_ARRAY(&ah->iniAdditional,
0079                     ar9331_1p1_xtal_25M);
0080         else
0081             INIT_INI_ARRAY(&ah->iniAdditional,
0082                     ar9331_1p1_xtal_40M);
0083     } else if (AR_SREV_9330_12(ah)) {
0084         /* mac */
0085         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
0086                 ar9331_1p2_mac_core);
0087         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
0088                 ar9331_1p2_mac_postamble);
0089 
0090         /* bb */
0091         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
0092                 ar9331_1p2_baseband_core);
0093         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
0094                 ar9331_1p2_baseband_postamble);
0095 
0096         /* radio */
0097         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
0098                 ar9331_1p2_radio_core);
0099 
0100         /* soc */
0101         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
0102                 ar9331_1p2_soc_preamble);
0103         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
0104                 ar9331_1p2_soc_postamble);
0105 
0106         /* rx/tx gain */
0107         INIT_INI_ARRAY(&ah->iniModesRxGain,
0108                 ar9331_common_rx_gain_1p2);
0109         INIT_INI_ARRAY(&ah->iniModesTxGain,
0110                 ar9331_modes_lowest_ob_db_tx_gain_1p2);
0111 
0112         /* Japan 2484 Mhz CCK */
0113         INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
0114                    ar9331_1p2_baseband_core_txfir_coeff_japan_2484);
0115 
0116         /* additional clock settings */
0117         if (ah->is_clk_25mhz)
0118             INIT_INI_ARRAY(&ah->iniAdditional,
0119                     ar9331_1p2_xtal_25M);
0120         else
0121             INIT_INI_ARRAY(&ah->iniAdditional,
0122                     ar9331_1p2_xtal_40M);
0123     } else if (AR_SREV_9340(ah)) {
0124         /* mac */
0125         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
0126                 ar9340_1p0_mac_core);
0127         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
0128                 ar9340_1p0_mac_postamble);
0129 
0130         /* bb */
0131         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
0132                 ar9340_1p0_baseband_core);
0133         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
0134                 ar9340_1p0_baseband_postamble);
0135 
0136         /* radio */
0137         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
0138                 ar9340_1p0_radio_core);
0139         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
0140                 ar9340_1p0_radio_postamble);
0141 
0142         /* soc */
0143         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
0144                 ar9340_1p0_soc_preamble);
0145         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
0146                 ar9340_1p0_soc_postamble);
0147 
0148         /* rx/tx gain */
0149         INIT_INI_ARRAY(&ah->iniModesRxGain,
0150                 ar9340Common_wo_xlna_rx_gain_table_1p0);
0151         INIT_INI_ARRAY(&ah->iniModesTxGain,
0152                 ar9340Modes_high_ob_db_tx_gain_table_1p0);
0153 
0154         INIT_INI_ARRAY(&ah->iniModesFastClock,
0155                    ar9340Modes_fast_clock_1p0);
0156         INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
0157                    ar9340_1p0_baseband_core_txfir_coeff_japan_2484);
0158         INIT_INI_ARRAY(&ah->ini_dfs,
0159                    ar9340_1p0_baseband_postamble_dfs_channel);
0160 
0161         if (!ah->is_clk_25mhz)
0162             INIT_INI_ARRAY(&ah->iniAdditional,
0163                        ar9340_1p0_radio_core_40M);
0164     } else if (AR_SREV_9485_11_OR_LATER(ah)) {
0165         /* mac */
0166         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
0167                 ar9485_1_1_mac_core);
0168         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
0169                 ar9485_1_1_mac_postamble);
0170 
0171         /* bb */
0172         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1);
0173         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
0174                 ar9485_1_1_baseband_core);
0175         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
0176                 ar9485_1_1_baseband_postamble);
0177 
0178         /* radio */
0179         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
0180                 ar9485_1_1_radio_core);
0181         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
0182                 ar9485_1_1_radio_postamble);
0183 
0184         /* soc */
0185         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
0186                 ar9485_1_1_soc_preamble);
0187 
0188         /* rx/tx gain */
0189         INIT_INI_ARRAY(&ah->iniModesRxGain,
0190                 ar9485Common_wo_xlna_rx_gain_1_1);
0191         INIT_INI_ARRAY(&ah->iniModesTxGain,
0192                 ar9485_modes_lowest_ob_db_tx_gain_1_1);
0193 
0194         /* Japan 2484 Mhz CCK */
0195         INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
0196                    ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
0197 
0198         if (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) {
0199             INIT_INI_ARRAY(&ah->iniPcieSerdes,
0200                        ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
0201             INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
0202                        ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
0203         } else {
0204             INIT_INI_ARRAY(&ah->iniPcieSerdes,
0205                        ar9485_1_1_pcie_phy_clkreq_disable_L1);
0206             INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
0207                        ar9485_1_1_pcie_phy_clkreq_disable_L1);
0208         }
0209     } else if (AR_SREV_9462_21(ah)) {
0210         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
0211                    ar9462_2p1_mac_core);
0212         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
0213                    ar9462_2p1_mac_postamble);
0214         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
0215                    ar9462_2p1_baseband_core);
0216         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
0217                    ar9462_2p1_baseband_postamble);
0218         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
0219                    ar9462_2p1_radio_core);
0220         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
0221                    ar9462_2p1_radio_postamble);
0222         INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
0223                    ar9462_2p1_radio_postamble_sys2ant);
0224         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
0225                    ar9462_2p1_soc_preamble);
0226         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
0227                    ar9462_2p1_soc_postamble);
0228         INIT_INI_ARRAY(&ah->iniModesRxGain,
0229                    ar9462_2p1_common_rx_gain);
0230         INIT_INI_ARRAY(&ah->iniModesFastClock,
0231                    ar9462_2p1_modes_fast_clock);
0232         INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
0233                    ar9462_2p1_baseband_core_txfir_coeff_japan_2484);
0234 
0235         /* Awake -> Sleep Setting */
0236         if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
0237             (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {
0238             INIT_INI_ARRAY(&ah->iniPcieSerdes,
0239                        ar9462_2p1_pciephy_clkreq_disable_L1);
0240         }
0241 
0242         /* Sleep -> Awake Setting */
0243         if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
0244             (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {
0245             INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
0246                        ar9462_2p1_pciephy_clkreq_disable_L1);
0247         }
0248     } else if (AR_SREV_9462_20(ah)) {
0249 
0250         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
0251         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
0252                 ar9462_2p0_mac_postamble);
0253 
0254         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
0255                 ar9462_2p0_baseband_core);
0256         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
0257                 ar9462_2p0_baseband_postamble);
0258 
0259         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
0260                 ar9462_2p0_radio_core);
0261         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
0262                 ar9462_2p0_radio_postamble);
0263         INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
0264                 ar9462_2p0_radio_postamble_sys2ant);
0265 
0266         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
0267                 ar9462_2p0_soc_preamble);
0268         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
0269                 ar9462_2p0_soc_postamble);
0270 
0271         INIT_INI_ARRAY(&ah->iniModesRxGain,
0272                 ar9462_2p0_common_rx_gain);
0273 
0274         /* Awake -> Sleep Setting */
0275         if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
0276             (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {
0277             INIT_INI_ARRAY(&ah->iniPcieSerdes,
0278                        ar9462_2p0_pciephy_clkreq_disable_L1);
0279         }
0280 
0281         /* Sleep -> Awake Setting */
0282         if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
0283             (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {
0284             INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
0285                        ar9462_2p0_pciephy_clkreq_disable_L1);
0286         }
0287 
0288         /* Fast clock modal settings */
0289         INIT_INI_ARRAY(&ah->iniModesFastClock,
0290                 ar9462_2p0_modes_fast_clock);
0291 
0292         INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
0293                    ar9462_2p0_baseband_core_txfir_coeff_japan_2484);
0294     } else if (AR_SREV_9550(ah)) {
0295         /* mac */
0296         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
0297                 ar955x_1p0_mac_core);
0298         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
0299                 ar955x_1p0_mac_postamble);
0300 
0301         /* bb */
0302         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
0303                 ar955x_1p0_baseband_core);
0304         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
0305                 ar955x_1p0_baseband_postamble);
0306 
0307         /* radio */
0308         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
0309                 ar955x_1p0_radio_core);
0310         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
0311                 ar955x_1p0_radio_postamble);
0312 
0313         /* soc */
0314         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
0315                 ar955x_1p0_soc_preamble);
0316         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
0317                 ar955x_1p0_soc_postamble);
0318 
0319         /* rx/tx gain */
0320         INIT_INI_ARRAY(&ah->iniModesRxGain,
0321             ar955x_1p0_common_wo_xlna_rx_gain_table);
0322         INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
0323             ar955x_1p0_common_wo_xlna_rx_gain_bounds);
0324         INIT_INI_ARRAY(&ah->iniModesTxGain,
0325                 ar955x_1p0_modes_xpa_tx_gain_table);
0326 
0327         /* Fast clock modal settings */
0328         INIT_INI_ARRAY(&ah->iniModesFastClock,
0329                 ar955x_1p0_modes_fast_clock);
0330     } else if (AR_SREV_9531(ah)) {
0331         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
0332                    qca953x_1p0_mac_core);
0333         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
0334                    qca953x_1p0_mac_postamble);
0335         if (AR_SREV_9531_20(ah)) {
0336             INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
0337                        qca953x_2p0_baseband_core);
0338             INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
0339                        qca953x_2p0_baseband_postamble);
0340         } else {
0341             INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
0342                        qca953x_1p0_baseband_core);
0343             INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
0344                        qca953x_1p0_baseband_postamble);
0345         }
0346         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
0347                    qca953x_1p0_radio_core);
0348         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
0349                    qca953x_1p0_radio_postamble);
0350         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
0351                    qca953x_1p0_soc_preamble);
0352         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
0353                    qca953x_1p0_soc_postamble);
0354 
0355         if (AR_SREV_9531_20(ah)) {
0356             INIT_INI_ARRAY(&ah->iniModesRxGain,
0357                        qca953x_2p0_common_wo_xlna_rx_gain_table);
0358             INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
0359                        qca953x_2p0_common_wo_xlna_rx_gain_bounds);
0360         } else {
0361             INIT_INI_ARRAY(&ah->iniModesRxGain,
0362                        qca953x_1p0_common_wo_xlna_rx_gain_table);
0363             INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
0364                        qca953x_1p0_common_wo_xlna_rx_gain_bounds);
0365         }
0366 
0367         if (AR_SREV_9531_20(ah))
0368             INIT_INI_ARRAY(&ah->iniModesTxGain,
0369                        qca953x_2p0_modes_no_xpa_tx_gain_table);
0370         else if (AR_SREV_9531_11(ah))
0371             INIT_INI_ARRAY(&ah->iniModesTxGain,
0372                        qca953x_1p1_modes_no_xpa_tx_gain_table);
0373         else
0374             INIT_INI_ARRAY(&ah->iniModesTxGain,
0375                        qca953x_1p0_modes_no_xpa_tx_gain_table);
0376 
0377         INIT_INI_ARRAY(&ah->iniModesFastClock,
0378                    qca953x_1p0_modes_fast_clock);
0379     } else if (AR_SREV_9561(ah)) {
0380         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
0381                    qca956x_1p0_mac_core);
0382         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
0383                    qca956x_1p0_mac_postamble);
0384 
0385         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
0386                    qca956x_1p0_baseband_core);
0387         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
0388                    qca956x_1p0_baseband_postamble);
0389 
0390         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
0391                    qca956x_1p0_radio_core);
0392         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
0393                    qca956x_1p0_radio_postamble);
0394 
0395         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
0396                    qca956x_1p0_soc_preamble);
0397         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
0398                    qca956x_1p0_soc_postamble);
0399 
0400         INIT_INI_ARRAY(&ah->iniModesRxGain,
0401                    qca956x_1p0_common_wo_xlna_rx_gain_table);
0402         INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
0403                    qca956x_1p0_common_wo_xlna_rx_gain_bounds);
0404         INIT_INI_ARRAY(&ah->iniModesTxGain,
0405                    qca956x_1p0_modes_no_xpa_tx_gain_table);
0406 
0407         INIT_INI_ARRAY(&ah->ini_dfs,
0408                    qca956x_1p0_baseband_postamble_dfs_channel);
0409         INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
0410                    qca956x_1p0_baseband_core_txfir_coeff_japan_2484);
0411         INIT_INI_ARRAY(&ah->iniModesFastClock,
0412                    qca956x_1p0_modes_fast_clock);
0413     } else if (AR_SREV_9580(ah)) {
0414         /* mac */
0415         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
0416                 ar9580_1p0_mac_core);
0417         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
0418                 ar9580_1p0_mac_postamble);
0419 
0420         /* bb */
0421         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
0422                 ar9580_1p0_baseband_core);
0423         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
0424                 ar9580_1p0_baseband_postamble);
0425 
0426         /* radio */
0427         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
0428                 ar9580_1p0_radio_core);
0429         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
0430                 ar9580_1p0_radio_postamble);
0431 
0432         /* soc */
0433         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
0434                 ar9580_1p0_soc_preamble);
0435         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
0436                 ar9580_1p0_soc_postamble);
0437 
0438         /* rx/tx gain */
0439         INIT_INI_ARRAY(&ah->iniModesRxGain,
0440                 ar9580_1p0_rx_gain_table);
0441         INIT_INI_ARRAY(&ah->iniModesTxGain,
0442                 ar9580_1p0_low_ob_db_tx_gain_table);
0443 
0444         INIT_INI_ARRAY(&ah->iniModesFastClock,
0445                    ar9580_1p0_modes_fast_clock);
0446         INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
0447                    ar9580_1p0_baseband_core_txfir_coeff_japan_2484);
0448         INIT_INI_ARRAY(&ah->ini_dfs,
0449                    ar9580_1p0_baseband_postamble_dfs_channel);
0450     } else if (AR_SREV_9565_11_OR_LATER(ah)) {
0451         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
0452                    ar9565_1p1_mac_core);
0453         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
0454                    ar9565_1p1_mac_postamble);
0455 
0456         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
0457                    ar9565_1p1_baseband_core);
0458         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
0459                    ar9565_1p1_baseband_postamble);
0460 
0461         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
0462                    ar9565_1p1_radio_core);
0463         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
0464                    ar9565_1p1_radio_postamble);
0465 
0466         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
0467                    ar9565_1p1_soc_preamble);
0468         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
0469                    ar9565_1p1_soc_postamble);
0470 
0471         INIT_INI_ARRAY(&ah->iniModesRxGain,
0472                    ar9565_1p1_Common_rx_gain_table);
0473         INIT_INI_ARRAY(&ah->iniModesTxGain,
0474                    ar9565_1p1_Modes_lowest_ob_db_tx_gain_table);
0475 
0476         /* Awake -> Sleep Setting */
0477         if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
0478             (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {
0479             INIT_INI_ARRAY(&ah->iniPcieSerdes,
0480                        ar9565_1p1_pciephy_clkreq_disable_L1);
0481         }
0482 
0483         /* Sleep -> Awake Setting */
0484         if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
0485             (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {
0486             INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
0487                        ar9565_1p1_pciephy_clkreq_disable_L1);
0488         }
0489 
0490         INIT_INI_ARRAY(&ah->iniModesFastClock,
0491                 ar9565_1p1_modes_fast_clock);
0492         INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
0493                    ar9565_1p1_baseband_core_txfir_coeff_japan_2484);
0494     } else if (AR_SREV_9565(ah)) {
0495         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
0496                    ar9565_1p0_mac_core);
0497         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
0498                    ar9565_1p0_mac_postamble);
0499 
0500         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
0501                    ar9565_1p0_baseband_core);
0502         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
0503                    ar9565_1p0_baseband_postamble);
0504 
0505         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
0506                    ar9565_1p0_radio_core);
0507         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
0508                    ar9565_1p0_radio_postamble);
0509 
0510         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
0511                    ar9565_1p0_soc_preamble);
0512         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
0513                    ar9565_1p0_soc_postamble);
0514 
0515         INIT_INI_ARRAY(&ah->iniModesRxGain,
0516                    ar9565_1p0_Common_rx_gain_table);
0517         INIT_INI_ARRAY(&ah->iniModesTxGain,
0518                    ar9565_1p0_Modes_lowest_ob_db_tx_gain_table);
0519 
0520         /* Awake -> Sleep Setting */
0521         if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
0522             (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {
0523             INIT_INI_ARRAY(&ah->iniPcieSerdes,
0524                        ar9565_1p0_pciephy_clkreq_disable_L1);
0525         }
0526 
0527         /* Sleep -> Awake Setting */
0528         if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&
0529             (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {
0530             INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
0531                        ar9565_1p0_pciephy_clkreq_disable_L1);
0532         }
0533 
0534         INIT_INI_ARRAY(&ah->iniModesFastClock,
0535                 ar9565_1p0_modes_fast_clock);
0536         INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
0537                    ar9565_1p0_baseband_core_txfir_coeff_japan_2484);
0538     } else {
0539         /* mac */
0540         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
0541                 ar9300_2p2_mac_core);
0542         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
0543                 ar9300_2p2_mac_postamble);
0544 
0545         /* bb */
0546         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
0547                 ar9300_2p2_baseband_core);
0548         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
0549                 ar9300_2p2_baseband_postamble);
0550 
0551         /* radio */
0552         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
0553                 ar9300_2p2_radio_core);
0554         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
0555                 ar9300_2p2_radio_postamble);
0556 
0557         /* soc */
0558         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
0559                 ar9300_2p2_soc_preamble);
0560         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
0561                 ar9300_2p2_soc_postamble);
0562 
0563         /* rx/tx gain */
0564         INIT_INI_ARRAY(&ah->iniModesRxGain,
0565                 ar9300Common_rx_gain_table_2p2);
0566         INIT_INI_ARRAY(&ah->iniModesTxGain,
0567                 ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
0568 
0569         /* Load PCIE SERDES settings from INI */
0570 
0571         /* Awake Setting */
0572 
0573         INIT_INI_ARRAY(&ah->iniPcieSerdes,
0574                 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
0575 
0576         /* Sleep Setting */
0577 
0578         INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
0579                 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
0580 
0581         /* Fast clock modal settings */
0582         INIT_INI_ARRAY(&ah->iniModesFastClock,
0583                    ar9300Modes_fast_clock_2p2);
0584         INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
0585                    ar9300_2p2_baseband_core_txfir_coeff_japan_2484);
0586         INIT_INI_ARRAY(&ah->ini_dfs,
0587                    ar9300_2p2_baseband_postamble_dfs_channel);
0588     }
0589 }
0590 
0591 static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
0592 {
0593     if (AR_SREV_9330_12(ah))
0594         INIT_INI_ARRAY(&ah->iniModesTxGain,
0595             ar9331_modes_lowest_ob_db_tx_gain_1p2);
0596     else if (AR_SREV_9330_11(ah))
0597         INIT_INI_ARRAY(&ah->iniModesTxGain,
0598             ar9331_modes_lowest_ob_db_tx_gain_1p1);
0599     else if (AR_SREV_9340(ah))
0600         INIT_INI_ARRAY(&ah->iniModesTxGain,
0601             ar9340Modes_lowest_ob_db_tx_gain_table_1p0);
0602     else if (AR_SREV_9485_11_OR_LATER(ah))
0603         INIT_INI_ARRAY(&ah->iniModesTxGain,
0604             ar9485_modes_lowest_ob_db_tx_gain_1_1);
0605     else if (AR_SREV_9550(ah))
0606         INIT_INI_ARRAY(&ah->iniModesTxGain,
0607             ar955x_1p0_modes_xpa_tx_gain_table);
0608     else if (AR_SREV_9531_10(ah))
0609         INIT_INI_ARRAY(&ah->iniModesTxGain,
0610                    qca953x_1p0_modes_xpa_tx_gain_table);
0611     else if (AR_SREV_9531_11(ah))
0612         INIT_INI_ARRAY(&ah->iniModesTxGain,
0613                    qca953x_1p1_modes_xpa_tx_gain_table);
0614     else if (AR_SREV_9531_20(ah))
0615         INIT_INI_ARRAY(&ah->iniModesTxGain,
0616                    qca953x_2p0_modes_xpa_tx_gain_table);
0617     else if (AR_SREV_9561(ah))
0618         INIT_INI_ARRAY(&ah->iniModesTxGain,
0619                    qca956x_1p0_modes_xpa_tx_gain_table);
0620     else if (AR_SREV_9580(ah))
0621         INIT_INI_ARRAY(&ah->iniModesTxGain,
0622             ar9580_1p0_lowest_ob_db_tx_gain_table);
0623     else if (AR_SREV_9462_21(ah))
0624         INIT_INI_ARRAY(&ah->iniModesTxGain,
0625             ar9462_2p1_modes_low_ob_db_tx_gain);
0626     else if (AR_SREV_9462_20(ah))
0627         INIT_INI_ARRAY(&ah->iniModesTxGain,
0628             ar9462_2p0_modes_low_ob_db_tx_gain);
0629     else if (AR_SREV_9565_11(ah))
0630         INIT_INI_ARRAY(&ah->iniModesTxGain,
0631                    ar9565_1p1_modes_low_ob_db_tx_gain_table);
0632     else if (AR_SREV_9565(ah))
0633         INIT_INI_ARRAY(&ah->iniModesTxGain,
0634                    ar9565_1p0_modes_low_ob_db_tx_gain_table);
0635     else
0636         INIT_INI_ARRAY(&ah->iniModesTxGain,
0637             ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
0638 }
0639 
0640 static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
0641 {
0642     if (AR_SREV_9330_12(ah))
0643         INIT_INI_ARRAY(&ah->iniModesTxGain,
0644             ar9331_modes_high_ob_db_tx_gain_1p2);
0645     else if (AR_SREV_9330_11(ah))
0646         INIT_INI_ARRAY(&ah->iniModesTxGain,
0647             ar9331_modes_high_ob_db_tx_gain_1p1);
0648     else if (AR_SREV_9340(ah))
0649         INIT_INI_ARRAY(&ah->iniModesTxGain,
0650             ar9340Modes_high_ob_db_tx_gain_table_1p0);
0651     else if (AR_SREV_9485_11_OR_LATER(ah))
0652         INIT_INI_ARRAY(&ah->iniModesTxGain,
0653             ar9485Modes_high_ob_db_tx_gain_1_1);
0654     else if (AR_SREV_9580(ah))
0655         INIT_INI_ARRAY(&ah->iniModesTxGain,
0656             ar9580_1p0_high_ob_db_tx_gain_table);
0657     else if (AR_SREV_9550(ah))
0658         INIT_INI_ARRAY(&ah->iniModesTxGain,
0659             ar955x_1p0_modes_no_xpa_tx_gain_table);
0660     else if (AR_SREV_9531(ah)) {
0661         if (AR_SREV_9531_20(ah))
0662             INIT_INI_ARRAY(&ah->iniModesTxGain,
0663                        qca953x_2p0_modes_no_xpa_tx_gain_table);
0664         else if (AR_SREV_9531_11(ah))
0665             INIT_INI_ARRAY(&ah->iniModesTxGain,
0666                        qca953x_1p1_modes_no_xpa_tx_gain_table);
0667         else
0668             INIT_INI_ARRAY(&ah->iniModesTxGain,
0669                        qca953x_1p0_modes_no_xpa_tx_gain_table);
0670     } else if (AR_SREV_9561(ah))
0671         INIT_INI_ARRAY(&ah->iniModesTxGain,
0672                    qca956x_1p0_modes_no_xpa_tx_gain_table);
0673     else if (AR_SREV_9462_21(ah))
0674         INIT_INI_ARRAY(&ah->iniModesTxGain,
0675             ar9462_2p1_modes_high_ob_db_tx_gain);
0676     else if (AR_SREV_9462_20(ah))
0677         INIT_INI_ARRAY(&ah->iniModesTxGain,
0678             ar9462_2p0_modes_high_ob_db_tx_gain);
0679     else if (AR_SREV_9565_11(ah))
0680         INIT_INI_ARRAY(&ah->iniModesTxGain,
0681                    ar9565_1p1_modes_high_ob_db_tx_gain_table);
0682     else if (AR_SREV_9565(ah))
0683         INIT_INI_ARRAY(&ah->iniModesTxGain,
0684                    ar9565_1p0_modes_high_ob_db_tx_gain_table);
0685     else
0686         INIT_INI_ARRAY(&ah->iniModesTxGain,
0687             ar9300Modes_high_ob_db_tx_gain_table_2p2);
0688 }
0689 
0690 static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
0691 {
0692     if (AR_SREV_9330_12(ah))
0693         INIT_INI_ARRAY(&ah->iniModesTxGain,
0694             ar9331_modes_low_ob_db_tx_gain_1p2);
0695     else if (AR_SREV_9330_11(ah))
0696         INIT_INI_ARRAY(&ah->iniModesTxGain,
0697             ar9331_modes_low_ob_db_tx_gain_1p1);
0698     else if (AR_SREV_9340(ah))
0699         INIT_INI_ARRAY(&ah->iniModesTxGain,
0700             ar9340Modes_low_ob_db_tx_gain_table_1p0);
0701     else if (AR_SREV_9531_11(ah))
0702         INIT_INI_ARRAY(&ah->iniModesTxGain,
0703                    qca953x_1p1_modes_no_xpa_low_power_tx_gain_table);
0704     else if (AR_SREV_9485_11_OR_LATER(ah))
0705         INIT_INI_ARRAY(&ah->iniModesTxGain,
0706             ar9485Modes_low_ob_db_tx_gain_1_1);
0707     else if (AR_SREV_9580(ah))
0708         INIT_INI_ARRAY(&ah->iniModesTxGain,
0709             ar9580_1p0_low_ob_db_tx_gain_table);
0710     else if (AR_SREV_9561(ah))
0711         INIT_INI_ARRAY(&ah->iniModesTxGain,
0712                    qca956x_1p0_modes_no_xpa_low_ob_db_tx_gain_table);
0713     else if (AR_SREV_9565_11(ah))
0714         INIT_INI_ARRAY(&ah->iniModesTxGain,
0715                    ar9565_1p1_modes_low_ob_db_tx_gain_table);
0716     else if (AR_SREV_9565(ah))
0717         INIT_INI_ARRAY(&ah->iniModesTxGain,
0718                    ar9565_1p0_modes_low_ob_db_tx_gain_table);
0719     else
0720         INIT_INI_ARRAY(&ah->iniModesTxGain,
0721             ar9300Modes_low_ob_db_tx_gain_table_2p2);
0722 }
0723 
0724 static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
0725 {
0726     if (AR_SREV_9330_12(ah))
0727         INIT_INI_ARRAY(&ah->iniModesTxGain,
0728             ar9331_modes_high_power_tx_gain_1p2);
0729     else if (AR_SREV_9330_11(ah))
0730         INIT_INI_ARRAY(&ah->iniModesTxGain,
0731             ar9331_modes_high_power_tx_gain_1p1);
0732     else if (AR_SREV_9340(ah))
0733         INIT_INI_ARRAY(&ah->iniModesTxGain,
0734             ar9340Modes_high_power_tx_gain_table_1p0);
0735     else if (AR_SREV_9485_11_OR_LATER(ah))
0736         INIT_INI_ARRAY(&ah->iniModesTxGain,
0737             ar9485Modes_high_power_tx_gain_1_1);
0738     else if (AR_SREV_9580(ah))
0739         INIT_INI_ARRAY(&ah->iniModesTxGain,
0740             ar9580_1p0_high_power_tx_gain_table);
0741     else if (AR_SREV_9565_11(ah))
0742         INIT_INI_ARRAY(&ah->iniModesTxGain,
0743                    ar9565_1p1_modes_high_power_tx_gain_table);
0744     else if (AR_SREV_9565(ah))
0745         INIT_INI_ARRAY(&ah->iniModesTxGain,
0746                    ar9565_1p0_modes_high_power_tx_gain_table);
0747     else {
0748         if (ah->config.tx_gain_buffalo)
0749             INIT_INI_ARRAY(&ah->iniModesTxGain,
0750                        ar9300Modes_high_power_tx_gain_table_buffalo);
0751         else
0752             INIT_INI_ARRAY(&ah->iniModesTxGain,
0753                        ar9300Modes_high_power_tx_gain_table_2p2);
0754     }
0755 }
0756 
0757 static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
0758 {
0759     if (AR_SREV_9340(ah))
0760         INIT_INI_ARRAY(&ah->iniModesTxGain,
0761             ar9340Modes_mixed_ob_db_tx_gain_table_1p0);
0762     else if (AR_SREV_9580(ah))
0763         INIT_INI_ARRAY(&ah->iniModesTxGain,
0764             ar9580_1p0_mixed_ob_db_tx_gain_table);
0765     else if (AR_SREV_9462_21(ah))
0766         INIT_INI_ARRAY(&ah->iniModesTxGain,
0767                ar9462_2p1_modes_mix_ob_db_tx_gain);
0768     else if (AR_SREV_9462_20(ah))
0769         INIT_INI_ARRAY(&ah->iniModesTxGain,
0770                ar9462_2p0_modes_mix_ob_db_tx_gain);
0771     else
0772         INIT_INI_ARRAY(&ah->iniModesTxGain,
0773             ar9300Modes_mixed_ob_db_tx_gain_table_2p2);
0774 }
0775 
0776 static void ar9003_tx_gain_table_mode5(struct ath_hw *ah)
0777 {
0778     if (AR_SREV_9485_11_OR_LATER(ah))
0779         INIT_INI_ARRAY(&ah->iniModesTxGain,
0780             ar9485Modes_green_ob_db_tx_gain_1_1);
0781     else if (AR_SREV_9580(ah))
0782         INIT_INI_ARRAY(&ah->iniModesTxGain,
0783             ar9580_1p0_type5_tx_gain_table);
0784     else if (AR_SREV_9561(ah))
0785         INIT_INI_ARRAY(&ah->iniModesTxGain,
0786                    qca956x_1p0_modes_no_xpa_green_tx_gain_table);
0787     else if (AR_SREV_9300_22(ah))
0788         INIT_INI_ARRAY(&ah->iniModesTxGain,
0789             ar9300Modes_type5_tx_gain_table_2p2);
0790 }
0791 
0792 static void ar9003_tx_gain_table_mode6(struct ath_hw *ah)
0793 {
0794     if (AR_SREV_9340(ah))
0795         INIT_INI_ARRAY(&ah->iniModesTxGain,
0796             ar9340Modes_low_ob_db_and_spur_tx_gain_table_1p0);
0797     else if (AR_SREV_9485_11_OR_LATER(ah))
0798         INIT_INI_ARRAY(&ah->iniModesTxGain,
0799             ar9485Modes_green_spur_ob_db_tx_gain_1_1);
0800     else if (AR_SREV_9580(ah))
0801         INIT_INI_ARRAY(&ah->iniModesTxGain,
0802             ar9580_1p0_type6_tx_gain_table);
0803 }
0804 
0805 static void ar9003_tx_gain_table_mode7(struct ath_hw *ah)
0806 {
0807     if (AR_SREV_9340(ah))
0808         INIT_INI_ARRAY(&ah->iniModesTxGain,
0809                    ar9340_cus227_tx_gain_table_1p0);
0810 }
0811 
0812 typedef void (*ath_txgain_tab)(struct ath_hw *ah);
0813 
0814 static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
0815 {
0816     static const ath_txgain_tab modes[] = {
0817         ar9003_tx_gain_table_mode0,
0818         ar9003_tx_gain_table_mode1,
0819         ar9003_tx_gain_table_mode2,
0820         ar9003_tx_gain_table_mode3,
0821         ar9003_tx_gain_table_mode4,
0822         ar9003_tx_gain_table_mode5,
0823         ar9003_tx_gain_table_mode6,
0824         ar9003_tx_gain_table_mode7,
0825     };
0826     int idx = ar9003_hw_get_tx_gain_idx(ah);
0827 
0828     if (idx >= ARRAY_SIZE(modes))
0829         idx = 0;
0830 
0831     modes[idx](ah);
0832 }
0833 
0834 static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
0835 {
0836     if (AR_SREV_9330_12(ah))
0837         INIT_INI_ARRAY(&ah->iniModesRxGain,
0838                 ar9331_common_rx_gain_1p2);
0839     else if (AR_SREV_9330_11(ah))
0840         INIT_INI_ARRAY(&ah->iniModesRxGain,
0841                 ar9331_common_rx_gain_1p1);
0842     else if (AR_SREV_9340(ah))
0843         INIT_INI_ARRAY(&ah->iniModesRxGain,
0844                 ar9340Common_rx_gain_table_1p0);
0845     else if (AR_SREV_9485_11_OR_LATER(ah))
0846         INIT_INI_ARRAY(&ah->iniModesRxGain,
0847                    ar9485_common_rx_gain_1_1);
0848     else if (AR_SREV_9550(ah)) {
0849         INIT_INI_ARRAY(&ah->iniModesRxGain,
0850                 ar955x_1p0_common_rx_gain_table);
0851         INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
0852                 ar955x_1p0_common_rx_gain_bounds);
0853     } else if (AR_SREV_9531(ah)) {
0854         INIT_INI_ARRAY(&ah->iniModesRxGain,
0855                    qca953x_1p0_common_rx_gain_table);
0856         INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
0857                    qca953x_1p0_common_rx_gain_bounds);
0858     } else if (AR_SREV_9561(ah)) {
0859         INIT_INI_ARRAY(&ah->iniModesRxGain,
0860                    qca956x_1p0_common_rx_gain_table);
0861         INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
0862                    qca956x_1p0_common_rx_gain_bounds);
0863         INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna,
0864                    qca956x_1p0_xlna_only);
0865     } else if (AR_SREV_9580(ah))
0866         INIT_INI_ARRAY(&ah->iniModesRxGain,
0867                 ar9580_1p0_rx_gain_table);
0868     else if (AR_SREV_9462_21(ah))
0869         INIT_INI_ARRAY(&ah->iniModesRxGain,
0870                 ar9462_2p1_common_rx_gain);
0871     else if (AR_SREV_9462_20(ah))
0872         INIT_INI_ARRAY(&ah->iniModesRxGain,
0873                 ar9462_2p0_common_rx_gain);
0874     else if (AR_SREV_9565_11(ah))
0875         INIT_INI_ARRAY(&ah->iniModesRxGain,
0876                    ar9565_1p1_Common_rx_gain_table);
0877     else if (AR_SREV_9565(ah))
0878         INIT_INI_ARRAY(&ah->iniModesRxGain,
0879                    ar9565_1p0_Common_rx_gain_table);
0880     else
0881         INIT_INI_ARRAY(&ah->iniModesRxGain,
0882                 ar9300Common_rx_gain_table_2p2);
0883 }
0884 
0885 static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
0886 {
0887     if (AR_SREV_9330_12(ah))
0888         INIT_INI_ARRAY(&ah->iniModesRxGain,
0889             ar9331_common_wo_xlna_rx_gain_1p2);
0890     else if (AR_SREV_9330_11(ah))
0891         INIT_INI_ARRAY(&ah->iniModesRxGain,
0892             ar9331_common_wo_xlna_rx_gain_1p1);
0893     else if (AR_SREV_9340(ah))
0894         INIT_INI_ARRAY(&ah->iniModesRxGain,
0895             ar9340Common_wo_xlna_rx_gain_table_1p0);
0896     else if (AR_SREV_9485_11_OR_LATER(ah))
0897         INIT_INI_ARRAY(&ah->iniModesRxGain,
0898             ar9485Common_wo_xlna_rx_gain_1_1);
0899     else if (AR_SREV_9462_21(ah))
0900         INIT_INI_ARRAY(&ah->iniModesRxGain,
0901             ar9462_2p1_common_wo_xlna_rx_gain);
0902     else if (AR_SREV_9462_20(ah))
0903         INIT_INI_ARRAY(&ah->iniModesRxGain,
0904             ar9462_2p0_common_wo_xlna_rx_gain);
0905     else if (AR_SREV_9550(ah)) {
0906         INIT_INI_ARRAY(&ah->iniModesRxGain,
0907             ar955x_1p0_common_wo_xlna_rx_gain_table);
0908         INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
0909             ar955x_1p0_common_wo_xlna_rx_gain_bounds);
0910     } else if (AR_SREV_9531_10(ah) || AR_SREV_9531_11(ah)) {
0911         INIT_INI_ARRAY(&ah->iniModesRxGain,
0912                    qca953x_1p0_common_wo_xlna_rx_gain_table);
0913         INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
0914                    qca953x_1p0_common_wo_xlna_rx_gain_bounds);
0915     } else if (AR_SREV_9531_20(ah)) {
0916         INIT_INI_ARRAY(&ah->iniModesRxGain,
0917                    qca953x_2p0_common_wo_xlna_rx_gain_table);
0918         INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
0919                    qca953x_2p0_common_wo_xlna_rx_gain_bounds);
0920     } else if (AR_SREV_9561(ah)) {
0921         INIT_INI_ARRAY(&ah->iniModesRxGain,
0922                    qca956x_1p0_common_wo_xlna_rx_gain_table);
0923         INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
0924                    qca956x_1p0_common_wo_xlna_rx_gain_bounds);
0925     } else if (AR_SREV_9580(ah))
0926         INIT_INI_ARRAY(&ah->iniModesRxGain,
0927             ar9580_1p0_wo_xlna_rx_gain_table);
0928     else if (AR_SREV_9565_11(ah))
0929         INIT_INI_ARRAY(&ah->iniModesRxGain,
0930                    ar9565_1p1_common_wo_xlna_rx_gain_table);
0931     else if (AR_SREV_9565(ah))
0932         INIT_INI_ARRAY(&ah->iniModesRxGain,
0933                    ar9565_1p0_common_wo_xlna_rx_gain_table);
0934     else
0935         INIT_INI_ARRAY(&ah->iniModesRxGain,
0936             ar9300Common_wo_xlna_rx_gain_table_2p2);
0937 }
0938 
0939 static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
0940 {
0941     if (AR_SREV_9462_21(ah)) {
0942         INIT_INI_ARRAY(&ah->iniModesRxGain,
0943                    ar9462_2p1_common_mixed_rx_gain);
0944         INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
0945                    ar9462_2p1_baseband_core_mix_rxgain);
0946         INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
0947                    ar9462_2p1_baseband_postamble_mix_rxgain);
0948         INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna,
0949                    ar9462_2p1_baseband_postamble_5g_xlna);
0950     } else if (AR_SREV_9462_20(ah)) {
0951         INIT_INI_ARRAY(&ah->iniModesRxGain,
0952                    ar9462_2p0_common_mixed_rx_gain);
0953         INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
0954                    ar9462_2p0_baseband_core_mix_rxgain);
0955         INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
0956                    ar9462_2p0_baseband_postamble_mix_rxgain);
0957         INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna,
0958                    ar9462_2p0_baseband_postamble_5g_xlna);
0959     }
0960 }
0961 
0962 static void ar9003_rx_gain_table_mode3(struct ath_hw *ah)
0963 {
0964     if (AR_SREV_9462_21(ah)) {
0965         INIT_INI_ARRAY(&ah->iniModesRxGain,
0966                    ar9462_2p1_common_5g_xlna_only_rxgain);
0967         INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna,
0968                    ar9462_2p1_baseband_postamble_5g_xlna);
0969     } else if (AR_SREV_9462_20(ah)) {
0970         INIT_INI_ARRAY(&ah->iniModesRxGain,
0971                    ar9462_2p0_common_5g_xlna_only_rxgain);
0972         INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna,
0973                    ar9462_2p0_baseband_postamble_5g_xlna);
0974     }
0975 }
0976 
0977 static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
0978 {
0979     switch (ar9003_hw_get_rx_gain_idx(ah)) {
0980     case 0:
0981     default:
0982         ar9003_rx_gain_table_mode0(ah);
0983         break;
0984     case 1:
0985         ar9003_rx_gain_table_mode1(ah);
0986         break;
0987     case 2:
0988         ar9003_rx_gain_table_mode2(ah);
0989         break;
0990     case 3:
0991         ar9003_rx_gain_table_mode3(ah);
0992         break;
0993     }
0994 }
0995 
0996 /* set gain table pointers according to values read from the eeprom */
0997 static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
0998 {
0999     ar9003_tx_gain_table_apply(ah);
1000     ar9003_rx_gain_table_apply(ah);
1001 }
1002 
1003 /*
1004  * Helper for ASPM support.
1005  *
1006  * Disable PLL when in L0s as well as receiver clock when in L1.
1007  * This power saving option must be enabled through the SerDes.
1008  *
1009  * Programming the SerDes must go through the same 288 bit serial shift
1010  * register as the other analog registers.  Hence the 9 writes.
1011  */
1012 static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
1013                      bool power_off)
1014 {
1015     unsigned int i;
1016     struct ar5416IniArray *array;
1017 
1018     /*
1019      * Increase L1 Entry Latency. Some WB222 boards don't have
1020      * this change in eeprom/OTP.
1021      *
1022      */
1023     if (AR_SREV_9462(ah)) {
1024         u32 val = ah->config.aspm_l1_fix;
1025         if ((val & 0xff000000) == 0x17000000) {
1026             val &= 0x00ffffff;
1027             val |= 0x27000000;
1028             REG_WRITE(ah, 0x570c, val);
1029         }
1030     }
1031 
1032     /* Nothing to do on restore for 11N */
1033     if (!power_off /* !restore */) {
1034         /* set bit 19 to allow forcing of pcie core into L1 state */
1035         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
1036         REG_WRITE(ah, AR_WA, ah->WARegVal);
1037     }
1038 
1039     /*
1040      * Configure PCIE after Ini init. SERDES values now come from ini file
1041      * This enables PCIe low power mode.
1042      */
1043     array = power_off ? &ah->iniPcieSerdes :
1044         &ah->iniPcieSerdesLowPower;
1045 
1046     for (i = 0; i < array->ia_rows; i++) {
1047         REG_WRITE(ah,
1048               INI_RA(array, i, 0),
1049               INI_RA(array, i, 1));
1050     }
1051 }
1052 
1053 static void ar9003_hw_init_hang_checks(struct ath_hw *ah)
1054 {
1055     /*
1056      * All chips support detection of BB/MAC hangs.
1057      */
1058     ah->config.hw_hang_checks |= HW_BB_WATCHDOG;
1059     ah->config.hw_hang_checks |= HW_MAC_HANG;
1060 
1061     /*
1062      * This is not required for AR9580 1.0
1063      */
1064     if (AR_SREV_9300_22(ah))
1065         ah->config.hw_hang_checks |= HW_PHYRESTART_CLC_WAR;
1066 
1067     if (AR_SREV_9330(ah))
1068         ah->bb_watchdog_timeout_ms = 85;
1069     else
1070         ah->bb_watchdog_timeout_ms = 25;
1071 }
1072 
1073 /*
1074  * MAC HW hang check
1075  * =================
1076  *
1077  * Signature: dcu_chain_state is 0x6 and dcu_complete_state is 0x1.
1078  *
1079  * The state of each DCU chain (mapped to TX queues) is available from these
1080  * DMA debug registers:
1081  *
1082  * Chain 0 state : Bits 4:0   of AR_DMADBG_4
1083  * Chain 1 state : Bits 9:5   of AR_DMADBG_4
1084  * Chain 2 state : Bits 14:10 of AR_DMADBG_4
1085  * Chain 3 state : Bits 19:15 of AR_DMADBG_4
1086  * Chain 4 state : Bits 24:20 of AR_DMADBG_4
1087  * Chain 5 state : Bits 29:25 of AR_DMADBG_4
1088  * Chain 6 state : Bits 4:0   of AR_DMADBG_5
1089  * Chain 7 state : Bits 9:5   of AR_DMADBG_5
1090  * Chain 8 state : Bits 14:10 of AR_DMADBG_5
1091  * Chain 9 state : Bits 19:15 of AR_DMADBG_5
1092  *
1093  * The DCU chain state "0x6" means "WAIT_FRDONE" - wait for TX frame to be done.
1094  */
1095 
1096 #define NUM_STATUS_READS 50
1097 
1098 static bool ath9k_hw_verify_hang(struct ath_hw *ah, unsigned int queue)
1099 {
1100     u32 dma_dbg_chain, dma_dbg_complete;
1101     u8 dcu_chain_state, dcu_complete_state;
1102     int i;
1103 
1104     for (i = 0; i < NUM_STATUS_READS; i++) {
1105         if (queue < 6)
1106             dma_dbg_chain = REG_READ(ah, AR_DMADBG_4);
1107         else
1108             dma_dbg_chain = REG_READ(ah, AR_DMADBG_5);
1109 
1110         dma_dbg_complete = REG_READ(ah, AR_DMADBG_6);
1111 
1112         dcu_chain_state = (dma_dbg_chain >> (5 * queue)) & 0x1f;
1113         dcu_complete_state = dma_dbg_complete & 0x3;
1114 
1115         if ((dcu_chain_state != 0x6) || (dcu_complete_state != 0x1))
1116             return false;
1117     }
1118 
1119     ath_dbg(ath9k_hw_common(ah), RESET,
1120         "MAC Hang signature found for queue: %d\n", queue);
1121 
1122     return true;
1123 }
1124 
1125 static bool ar9003_hw_detect_mac_hang(struct ath_hw *ah)
1126 {
1127     u32 dma_dbg_4, dma_dbg_5, dma_dbg_6, chk_dbg;
1128     u8 dcu_chain_state, dcu_complete_state;
1129     bool dcu_wait_frdone = false;
1130     unsigned long chk_dcu = 0;
1131     unsigned int i = 0;
1132 
1133     dma_dbg_4 = REG_READ(ah, AR_DMADBG_4);
1134     dma_dbg_5 = REG_READ(ah, AR_DMADBG_5);
1135     dma_dbg_6 = REG_READ(ah, AR_DMADBG_6);
1136 
1137     dcu_complete_state = dma_dbg_6 & 0x3;
1138     if (dcu_complete_state != 0x1)
1139         goto exit;
1140 
1141     for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1142         if (i < 6)
1143             chk_dbg = dma_dbg_4;
1144         else
1145             chk_dbg = dma_dbg_5;
1146 
1147         dcu_chain_state = (chk_dbg >> (5 * i)) & 0x1f;
1148         if (dcu_chain_state == 0x6) {
1149             dcu_wait_frdone = true;
1150             chk_dcu |= BIT(i);
1151         }
1152     }
1153 
1154     if ((dcu_complete_state == 0x1) && dcu_wait_frdone) {
1155         for_each_set_bit(i, &chk_dcu, ATH9K_NUM_TX_QUEUES) {
1156             if (ath9k_hw_verify_hang(ah, i))
1157                 return true;
1158         }
1159     }
1160 exit:
1161     return false;
1162 }
1163 
1164 /* Sets up the AR9003 hardware familiy callbacks */
1165 void ar9003_hw_attach_ops(struct ath_hw *ah)
1166 {
1167     struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1168     struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1169 
1170     ar9003_hw_init_mode_regs(ah);
1171 
1172     if (AR_SREV_9003_PCOEM(ah)) {
1173         WARN_ON(!ah->iniPcieSerdes.ia_array);
1174         WARN_ON(!ah->iniPcieSerdesLowPower.ia_array);
1175     }
1176 
1177     priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
1178     priv_ops->init_hang_checks = ar9003_hw_init_hang_checks;
1179     priv_ops->detect_mac_hang = ar9003_hw_detect_mac_hang;
1180 
1181     ops->config_pci_powersave = ar9003_hw_configpcipowersave;
1182 
1183     ar9003_hw_attach_phy_ops(ah);
1184     ar9003_hw_attach_calib_ops(ah);
1185     ar9003_hw_attach_mac_ops(ah);
1186     ar9003_hw_attach_aic_ops(ah);
1187 }
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