ath/ath9k/ar9003_eeprom.h

0001 /*
0002  * Copyright (c) 2010-2011 Atheros Communications Inc.
0003  *
0004  * Permission to use, copy, modify, and/or distribute this software for any
0005  * purpose with or without fee is hereby granted, provided that the above
0006  * copyright notice and this permission notice appear in all copies.
0007  *
0008  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0009  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0010  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0011  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0012  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0013  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0014  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0015  */
0016
0017 #ifndef AR9003_EEPROM_H
0018 #define AR9003_EEPROM_H
0019
0020 #include <linux/types.h>
0021
0022 #define AR9300_EEP_VER               0xD000
0023 #define AR9300_EEP_VER_MINOR_MASK    0xFFF
0024 #define AR9300_EEP_MINOR_VER_1       0x1
0025 #define AR9300_EEP_MINOR_VER         AR9300_EEP_MINOR_VER_1
0026
0027 /* 16-bit offset location start of calibration struct */
0028 #define AR9300_EEP_START_LOC         256
0029 #define AR9300_NUM_5G_CAL_PIERS      8
0030 #define AR9300_NUM_2G_CAL_PIERS      3
0031 #define AR9300_NUM_5G_20_TARGET_POWERS  8
0032 #define AR9300_NUM_5G_40_TARGET_POWERS  8
0033 #define AR9300_NUM_2G_CCK_TARGET_POWERS 2
0034 #define AR9300_NUM_2G_20_TARGET_POWERS  3
0035 #define AR9300_NUM_2G_40_TARGET_POWERS  3
0036 /* #define AR9300_NUM_CTLS              21 */
0037 #define AR9300_NUM_CTLS_5G           9
0038 #define AR9300_NUM_CTLS_2G           12
0039 #define AR9300_NUM_BAND_EDGES_5G     8
0040 #define AR9300_NUM_BAND_EDGES_2G     4
0041 #define AR9300_EEPMISC_WOW           0x02
0042 #define AR9300_CUSTOMER_DATA_SIZE    20
0043
0044 #define AR9300_MAX_CHAINS            3
0045 #define AR9300_ANT_16S               25
0046 #define AR9300_FUTURE_MODAL_SZ       6
0047
0048 #define AR9300_PAPRD_RATE_MASK      0x01ffffff
0049 #define AR9300_PAPRD_SCALE_1        0x0e000000
0050 #define AR9300_PAPRD_SCALE_1_S      25
0051 #define AR9300_PAPRD_SCALE_2        0x70000000
0052 #define AR9300_PAPRD_SCALE_2_S      28
0053
0054 #define AR9300_EEP_ANTDIV_CONTROL_DEFAULT_VALUE 0xc9
0055
0056 /* Delta from which to start power to pdadc table */
0057 /* This offset is used in both open loop and closed loop power control
0058  * schemes. In open loop power control, it is not really needed, but for
0059  * the "sake of consistency" it was kept. For certain AP designs, this
0060  * value is overwritten by the value in the flag "pwrTableOffset" just
0061  * before writing the pdadc vs pwr into the chip registers.
0062  */
0063 #define AR9300_PWR_TABLE_OFFSET  0
0064
0065 /* Noise power data definitions
0066  * units are: 4 x dBm - NOISE_PWR_DATA_OFFSET
0067  * (e.g. -25 = (-25/4 - 90) = -96.25 dBm)
0068  * range (for 6 signed bits) is (-32 to 31) + offset => -122dBm to -59dBm
0069  * resolution (2 bits) is 0.25dBm
0070  */
0071 #define NOISE_PWR_DATA_OFFSET   -90
0072 #define NOISE_PWR_DBM_2_INT(_p) ((((_p) + 3) >> 2) + NOISE_PWR_DATA_OFFSET)
0073 #define N2DBM(_p)       NOISE_PWR_DBM_2_INT(_p)
0074
0075 /* byte addressable */
0076 #define AR9300_EEPROM_SIZE (16*1024)
0077
0078 #define AR9300_BASE_ADDR_4K 0xfff
0079 #define AR9300_BASE_ADDR 0x3ff
0080 #define AR9300_BASE_ADDR_512 0x1ff
0081
0082 /* AR5416_EEPMISC_BIG_ENDIAN not set indicates little endian */
0083 #define AR9300_EEPMISC_LITTLE_ENDIAN 0
0084
0085 #define AR9300_OTP_BASE \
0086         ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x30000 : 0x14000)
0087 #define AR9300_OTP_STATUS \
0088         ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x31018 : 0x15f18)
0089 #define AR9300_OTP_STATUS_TYPE      0x7
0090 #define AR9300_OTP_STATUS_VALID     0x4
0091 #define AR9300_OTP_STATUS_ACCESS_BUSY   0x2
0092 #define AR9300_OTP_STATUS_SM_BUSY   0x1
0093 #define AR9300_OTP_READ_DATA \
0094         ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x3101c : 0x15f1c)
0095
0096 enum targetPowerHTRates {
0097     HT_TARGET_RATE_0_8_16,
0098     HT_TARGET_RATE_1_3_9_11_17_19,
0099     HT_TARGET_RATE_4,
0100     HT_TARGET_RATE_5,
0101     HT_TARGET_RATE_6,
0102     HT_TARGET_RATE_7,
0103     HT_TARGET_RATE_12,
0104     HT_TARGET_RATE_13,
0105     HT_TARGET_RATE_14,
0106     HT_TARGET_RATE_15,
0107     HT_TARGET_RATE_20,
0108     HT_TARGET_RATE_21,
0109     HT_TARGET_RATE_22,
0110     HT_TARGET_RATE_23
0111 };
0112
0113 enum targetPowerLegacyRates {
0114     LEGACY_TARGET_RATE_6_24,
0115     LEGACY_TARGET_RATE_36,
0116     LEGACY_TARGET_RATE_48,
0117     LEGACY_TARGET_RATE_54
0118 };
0119
0120 enum targetPowerCckRates {
0121     LEGACY_TARGET_RATE_1L_5L,
0122     LEGACY_TARGET_RATE_5S,
0123     LEGACY_TARGET_RATE_11L,
0124     LEGACY_TARGET_RATE_11S
0125 };
0126
0127 enum ar9300_Rates {
0128     ALL_TARGET_LEGACY_6_24,
0129     ALL_TARGET_LEGACY_36,
0130     ALL_TARGET_LEGACY_48,
0131     ALL_TARGET_LEGACY_54,
0132     ALL_TARGET_LEGACY_1L_5L,
0133     ALL_TARGET_LEGACY_5S,
0134     ALL_TARGET_LEGACY_11L,
0135     ALL_TARGET_LEGACY_11S,
0136     ALL_TARGET_HT20_0_8_16,
0137     ALL_TARGET_HT20_1_3_9_11_17_19,
0138     ALL_TARGET_HT20_4,
0139     ALL_TARGET_HT20_5,
0140     ALL_TARGET_HT20_6,
0141     ALL_TARGET_HT20_7,
0142     ALL_TARGET_HT20_12,
0143     ALL_TARGET_HT20_13,
0144     ALL_TARGET_HT20_14,
0145     ALL_TARGET_HT20_15,
0146     ALL_TARGET_HT20_20,
0147     ALL_TARGET_HT20_21,
0148     ALL_TARGET_HT20_22,
0149     ALL_TARGET_HT20_23,
0150     ALL_TARGET_HT40_0_8_16,
0151     ALL_TARGET_HT40_1_3_9_11_17_19,
0152     ALL_TARGET_HT40_4,
0153     ALL_TARGET_HT40_5,
0154     ALL_TARGET_HT40_6,
0155     ALL_TARGET_HT40_7,
0156     ALL_TARGET_HT40_12,
0157     ALL_TARGET_HT40_13,
0158     ALL_TARGET_HT40_14,
0159     ALL_TARGET_HT40_15,
0160     ALL_TARGET_HT40_20,
0161     ALL_TARGET_HT40_21,
0162     ALL_TARGET_HT40_22,
0163     ALL_TARGET_HT40_23,
0164     ar9300RateSize,
0165 };
0166
0167
0168 struct eepFlags {
0169     u8 opFlags;
0170     u8 eepMisc;
0171 } __packed;
0172
0173 enum CompressAlgorithm {
0174     _CompressNone = 0,
0175     _CompressLzma,
0176     _CompressPairs,
0177     _CompressBlock,
0178     _Compress4,
0179     _Compress5,
0180     _Compress6,
0181     _Compress7,
0182 };
0183
0184 struct ar9300_base_eep_hdr {
0185     __le16 regDmn[2];
0186     /* 4 bits tx and 4 bits rx */
0187     u8 txrxMask;
0188     struct eepFlags opCapFlags;
0189     u8 rfSilent;
0190     u8 blueToothOptions;
0191     u8 deviceCap;
0192     /* takes lower byte in eeprom location */
0193     u8 deviceType;
0194     /* offset in dB to be added to beginning
0195      * of pdadc table in calibration
0196      */
0197     int8_t pwrTableOffset;
0198     u8 params_for_tuning_caps[2];
0199     /*
0200      * bit0 - enable tx temp comp
0201      * bit1 - enable tx volt comp
0202      * bit2 - enable fastClock - default to 1
0203      * bit3 - enable doubling - default to 1
0204      * bit4 - enable internal regulator - default to 1
0205      */
0206     u8 featureEnable;
0207     /* misc flags: bit0 - turn down drivestrength */
0208     u8 miscConfiguration;
0209     u8 eepromWriteEnableGpio;
0210     u8 wlanDisableGpio;
0211     u8 wlanLedGpio;
0212     u8 rxBandSelectGpio;
0213     u8 txrxgain;
0214     /* SW controlled internal regulator fields */
0215     __le32 swreg;
0216 } __packed;
0217
0218 struct ar9300_modal_eep_header {
0219     /* 4 idle, t1, t2, b (4 bits per setting) */
0220     __le32 antCtrlCommon;
0221     /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
0222     __le32 antCtrlCommon2;
0223     /* 6 idle, t, r, rx1, rx12, b (2 bits each) */
0224     __le16 antCtrlChain[AR9300_MAX_CHAINS];
0225     /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
0226     u8 xatten1DB[AR9300_MAX_CHAINS];
0227     /* 3  xatten1_margin for merlin (0xa20c/b20c 16:12 */
0228     u8 xatten1Margin[AR9300_MAX_CHAINS];
0229     int8_t tempSlope;
0230     int8_t voltSlope;
0231     /* spur channels in usual fbin coding format */
0232     u8 spurChans[AR_EEPROM_MODAL_SPURS];
0233     /* 3  Check if the register is per chain */
0234     int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
0235     u8 reserved[11];
0236     int8_t quick_drop;
0237     u8 xpaBiasLvl;
0238     u8 txFrameToDataStart;
0239     u8 txFrameToPaOn;
0240     u8 txClip;
0241     int8_t antennaGain;
0242     u8 switchSettling;
0243     int8_t adcDesiredSize;
0244     u8 txEndToXpaOff;
0245     u8 txEndToRxOn;
0246     u8 txFrameToXpaOn;
0247     u8 thresh62;
0248     __le32 papdRateMaskHt20;
0249     __le32 papdRateMaskHt40;
0250     __le16 switchcomspdt;
0251     u8 xlna_bias_strength;
0252     u8 futureModal[7];
0253 } __packed;
0254
0255 struct ar9300_cal_data_per_freq_op_loop {
0256     int8_t refPower;
0257     /* pdadc voltage at power measurement */
0258     u8 voltMeas;
0259     /* pcdac used for power measurement   */
0260     u8 tempMeas;
0261     /* range is -60 to -127 create a mapping equation 1db resolution */
0262     int8_t rxNoisefloorCal;
0263     /*range is same as noisefloor */
0264     int8_t rxNoisefloorPower;
0265     /* temp measured when noisefloor cal was performed */
0266     u8 rxTempMeas;
0267 } __packed;
0268
0269 struct cal_tgt_pow_legacy {
0270     u8 tPow2x[4];
0271 } __packed;
0272
0273 struct cal_tgt_pow_ht {
0274     u8 tPow2x[14];
0275 } __packed;
0276
0277 struct cal_ctl_data_2g {
0278     u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G];
0279 } __packed;
0280
0281 struct cal_ctl_data_5g {
0282     u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G];
0283 } __packed;
0284
0285 #define MAX_BASE_EXTENSION_FUTURE 2
0286
0287 struct ar9300_BaseExtension_1 {
0288     u8 ant_div_control;
0289     u8 future[MAX_BASE_EXTENSION_FUTURE];
0290     /*
0291      * misc_enable:
0292      *
0293      * BIT 0   - TX Gain Cap enable.
0294      * BIT 1   - Uncompressed Checksum enable.
0295      * BIT 2/3 - MinCCApwr enable 2g/5g.
0296      */
0297     u8 misc_enable;
0298     int8_t tempslopextension[8];
0299     int8_t quick_drop_low;
0300     int8_t quick_drop_high;
0301 } __packed;
0302
0303 struct ar9300_BaseExtension_2 {
0304     int8_t    tempSlopeLow;
0305     int8_t    tempSlopeHigh;
0306     u8   xatten1DBLow[AR9300_MAX_CHAINS];
0307     u8   xatten1MarginLow[AR9300_MAX_CHAINS];
0308     u8   xatten1DBHigh[AR9300_MAX_CHAINS];
0309     u8   xatten1MarginHigh[AR9300_MAX_CHAINS];
0310 } __packed;
0311
0312 struct ar9300_eeprom {
0313     u8 eepromVersion;
0314     u8 templateVersion;
0315     u8 macAddr[6];
0316     u8 custData[AR9300_CUSTOMER_DATA_SIZE];
0317
0318     struct ar9300_base_eep_hdr baseEepHeader;
0319
0320     struct ar9300_modal_eep_header modalHeader2G;
0321     struct ar9300_BaseExtension_1 base_ext1;
0322     u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
0323     struct ar9300_cal_data_per_freq_op_loop
0324      calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
0325     u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
0326     u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
0327     u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
0328     u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
0329     struct cal_tgt_pow_legacy
0330      calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
0331     struct cal_tgt_pow_legacy
0332      calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
0333     struct cal_tgt_pow_ht
0334      calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
0335     struct cal_tgt_pow_ht
0336      calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
0337     u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];
0338     u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
0339     struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
0340     struct ar9300_modal_eep_header modalHeader5G;
0341     struct ar9300_BaseExtension_2 base_ext2;
0342     u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
0343     struct ar9300_cal_data_per_freq_op_loop
0344      calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
0345     u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
0346     u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
0347     u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
0348     struct cal_tgt_pow_legacy
0349      calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
0350     struct cal_tgt_pow_ht
0351      calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
0352     struct cal_tgt_pow_ht
0353      calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
0354     u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];
0355     u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
0356     struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
0357 } __packed;
0358
0359 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
0360 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
0361 u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz);
0362 u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz);
0363
0364 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz);
0365
0366 u32 ar9003_get_paprd_rate_mask_ht20(struct ath_hw *ah, bool is2ghz);
0367 u32 ar9003_get_paprd_rate_mask_ht40(struct ath_hw *ah, bool is2ghz);
0368 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
0369                        struct ath9k_channel *chan);
0370
0371 void ar9003_hw_internal_regulator_apply(struct ath_hw *ah);
0372 int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray);
0373
0374 #endif