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0017 #ifndef AR9003_AIC_H
0018 #define AR9003_AIC_H
0019
0020 #define ATH_AIC_MAX_COM_ATT_DB_TABLE 6
0021 #define ATH_AIC_MAX_AIC_LIN_TABLE 69
0022 #define ATH_AIC_MIN_ROT_DIR_ATT_DB 0
0023 #define ATH_AIC_MIN_ROT_QUAD_ATT_DB 0
0024 #define ATH_AIC_MAX_ROT_DIR_ATT_DB 37
0025 #define ATH_AIC_MAX_ROT_QUAD_ATT_DB 37
0026 #define ATH_AIC_SRAM_AUTO_INCREMENT 0x80000000
0027 #define ATH_AIC_SRAM_GAIN_TABLE_OFFSET 0x280
0028 #define ATH_AIC_SRAM_CAL_OFFSET 0x140
0029 #define ATH_AIC_SRAM_OFFSET 0x00
0030 #define ATH_AIC_MEAS_MAG_THRESH 20
0031 #define ATH_AIC_BT_JUPITER_CTRL 0x66820
0032 #define ATH_AIC_BT_AIC_ENABLE 0x02
0033
0034 enum aic_cal_state {
0035 AIC_CAL_STATE_IDLE = 0,
0036 AIC_CAL_STATE_STARTED,
0037 AIC_CAL_STATE_DONE,
0038 AIC_CAL_STATE_ERROR
0039 };
0040
0041 struct ath_aic_sram_info {
0042 bool valid:1;
0043 bool vga_quad_sign:1;
0044 bool vga_dir_sign:1;
0045 u8 rot_quad_att_db;
0046 u8 rot_dir_att_db;
0047 u8 com_att_6db;
0048 };
0049
0050 struct ath_aic_out_info {
0051 int16_t dir_path_gain_lin;
0052 int16_t quad_path_gain_lin;
0053 };
0054
0055 u8 ar9003_aic_calibration(struct ath_hw *ah);
0056 u8 ar9003_aic_start_normal(struct ath_hw *ah);
0057 u8 ar9003_aic_cal_reset(struct ath_hw *ah);
0058 u8 ar9003_aic_calibration_single(struct ath_hw *ah);
0059
0060 #endif