ath/ath6kl/hif.h

0001 /*
0002  * Copyright (c) 2004-2011 Atheros Communications Inc.
0003  * Copyright (c) 2011 Qualcomm Atheros, Inc.
0004  *
0005  * Permission to use, copy, modify, and/or distribute this software for any
0006  * purpose with or without fee is hereby granted, provided that the above
0007  * copyright notice and this permission notice appear in all copies.
0008  *
0009  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0010  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0011  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0012  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0013  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0014  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0015  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0016  */
0017
0018 #ifndef HIF_H
0019 #define HIF_H
0020
0021 #include "common.h"
0022 #include "core.h"
0023
0024 #include <linux/scatterlist.h>
0025
0026 #define BUS_REQUEST_MAX_NUM                64
0027 #define HIF_MBOX_BLOCK_SIZE                128
0028 #define HIF_MBOX0_BLOCK_SIZE               1
0029
0030 #define HIF_DMA_BUFFER_SIZE (32 * 1024)
0031 #define CMD53_FIXED_ADDRESS 1
0032 #define CMD53_INCR_ADDRESS  2
0033
0034 #define MAX_SCATTER_REQUESTS             4
0035 #define MAX_SCATTER_ENTRIES_PER_REQ      16
0036 #define MAX_SCATTER_REQ_TRANSFER_SIZE    (32 * 1024)
0037
0038 /* Mailbox address in SDIO address space */
0039 #define HIF_MBOX_BASE_ADDR                 0x800
0040 #define HIF_MBOX_WIDTH                     0x800
0041
0042 #define HIF_MBOX_END_ADDR  (HTC_MAILBOX_NUM_MAX * HIF_MBOX_WIDTH - 1)
0043
0044 /* version 1 of the chip has only a 12K extended mbox range */
0045 #define HIF_MBOX0_EXT_BASE_ADDR  0x4000
0046 #define HIF_MBOX0_EXT_WIDTH      (12*1024)
0047
0048 /* GMBOX addresses */
0049 #define HIF_GMBOX_BASE_ADDR                0x7000
0050 #define HIF_GMBOX_WIDTH                    0x4000
0051
0052 /* interrupt mode register */
0053 #define CCCR_SDIO_IRQ_MODE_REG         0xF0
0054
0055 /* mode to enable special 4-bit interrupt assertion without clock */
0056 #define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ   (1 << 0)
0057
0058 /* HTC runs over mailbox 0 */
0059 #define HTC_MAILBOX 0
0060
0061 #define ATH6KL_TARGET_DEBUG_INTR_MASK     0x01
0062
0063 /* FIXME: are these duplicates with MAX_SCATTER_ values in hif.h? */
0064 #define ATH6KL_SCATTER_ENTRIES_PER_REQ            16
0065 #define ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER      (16 * 1024)
0066 #define ATH6KL_SCATTER_REQS                       4
0067
0068 #define ATH6KL_HIF_COMMUNICATION_TIMEOUT    1000
0069
0070 struct bus_request {
0071     struct list_head list;
0072
0073     /* request data */
0074     u32 address;
0075
0076     u8 *buffer;
0077     u32 length;
0078     u32 request;
0079     struct htc_packet *packet;
0080     int status;
0081
0082     /* this is a scatter request */
0083     struct hif_scatter_req *scat_req;
0084 };
0085
0086 /* direction of transfer (read/write) */
0087 #define HIF_READ                    0x00000001
0088 #define HIF_WRITE                   0x00000002
0089 #define HIF_DIR_MASK                (HIF_READ | HIF_WRITE)
0090
0091 /*
0092  *     emode - This indicates the whether the command is to be executed in a
0093  *             blocking or non-blocking fashion (HIF_SYNCHRONOUS/
0094  *             HIF_ASYNCHRONOUS). The read/write data paths in HTC have been
0095  *             implemented using the asynchronous mode allowing the bus
0096  *             driver to indicate the completion of operation through the
0097  *             registered callback routine. The requirement primarily comes
0098  *             from the contexts these operations get called from (a driver's
0099  *             transmit context or the ISR context in case of receive).
0100  *             Support for both of these modes is essential.
0101  */
0102 #define HIF_SYNCHRONOUS             0x00000010
0103 #define HIF_ASYNCHRONOUS            0x00000020
0104 #define HIF_EMODE_MASK              (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS)
0105
0106 /*
0107  *     dmode - An interface may support different kinds of commands based on
0108  *             the tradeoff between the amount of data it can carry and the
0109  *             setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/
0110  *             HIF_BLOCK_BASIS). In case of latter, the data is rounded off
0111  *             to the nearest block size by padding. The size of the block is
0112  *             configurable at compile time using the HIF_BLOCK_SIZE and is
0113  *             negotiated with the target during initialization after the
0114  *             ATH6KL interrupts are enabled.
0115  */
0116 #define HIF_BYTE_BASIS              0x00000040
0117 #define HIF_BLOCK_BASIS             0x00000080
0118 #define HIF_DMODE_MASK              (HIF_BYTE_BASIS | HIF_BLOCK_BASIS)
0119
0120 /*
0121  *     amode - This indicates if the address has to be incremented on ATH6KL
0122  *             after every read/write operation (HIF?FIXED_ADDRESS/
0123  *             HIF_INCREMENTAL_ADDRESS).
0124  */
0125 #define HIF_FIXED_ADDRESS           0x00000100
0126 #define HIF_INCREMENTAL_ADDRESS     0x00000200
0127 #define HIF_AMODE_MASK        (HIF_FIXED_ADDRESS | HIF_INCREMENTAL_ADDRESS)
0128
0129 #define HIF_WR_ASYNC_BYTE_INC                   \
0130     (HIF_WRITE | HIF_ASYNCHRONOUS |             \
0131      HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
0132
0133 #define HIF_WR_ASYNC_BLOCK_INC                  \
0134     (HIF_WRITE | HIF_ASYNCHRONOUS |             \
0135      HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
0136
0137 #define HIF_WR_SYNC_BYTE_FIX                    \
0138     (HIF_WRITE | HIF_SYNCHRONOUS |              \
0139      HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
0140
0141 #define HIF_WR_SYNC_BYTE_INC                    \
0142     (HIF_WRITE | HIF_SYNCHRONOUS |              \
0143      HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
0144
0145 #define HIF_WR_SYNC_BLOCK_INC                   \
0146     (HIF_WRITE | HIF_SYNCHRONOUS |              \
0147      HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
0148
0149 #define HIF_RD_SYNC_BYTE_INC                        \
0150     (HIF_READ | HIF_SYNCHRONOUS |                   \
0151      HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
0152
0153 #define HIF_RD_SYNC_BYTE_FIX                        \
0154     (HIF_READ | HIF_SYNCHRONOUS |                   \
0155      HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
0156
0157 #define HIF_RD_ASYNC_BLOCK_FIX                      \
0158     (HIF_READ | HIF_ASYNCHRONOUS |                  \
0159      HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
0160
0161 #define HIF_RD_SYNC_BLOCK_FIX                       \
0162     (HIF_READ | HIF_SYNCHRONOUS |                   \
0163      HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
0164
0165 struct hif_scatter_item {
0166     u8 *buf;
0167     int len;
0168     struct htc_packet *packet;
0169 };
0170
0171 struct hif_scatter_req {
0172     struct list_head list;
0173     /* address for the read/write operation */
0174     u32 addr;
0175
0176     /* request flags */
0177     u32 req;
0178
0179     /* total length of entire transfer */
0180     u32 len;
0181
0182     bool virt_scat;
0183
0184     void (*complete) (struct htc_target *, struct hif_scatter_req *);
0185     int status;
0186     int scat_entries;
0187
0188     struct bus_request *busrequest;
0189     struct scatterlist *sgentries;
0190
0191     /* bounce buffer for upper layers to copy to/from */
0192     u8 *virt_dma_buf;
0193
0194     u32 scat_q_depth;
0195
0196     struct hif_scatter_item scat_list[];
0197 };
0198
0199 struct ath6kl_irq_proc_registers {
0200     u8 host_int_status;
0201     u8 cpu_int_status;
0202     u8 error_int_status;
0203     u8 counter_int_status;
0204     u8 mbox_frame;
0205     u8 rx_lkahd_valid;
0206     u8 host_int_status2;
0207     u8 gmbox_rx_avail;
0208     __le32 rx_lkahd[2];
0209     __le32 rx_gmbox_lkahd_alias[2];
0210 } __packed;
0211
0212 struct ath6kl_irq_enable_reg {
0213     u8 int_status_en;
0214     u8 cpu_int_status_en;
0215     u8 err_int_status_en;
0216     u8 cntr_int_status_en;
0217 } __packed;
0218
0219 struct ath6kl_device {
0220     /* protects irq_proc_reg and irq_en_reg below */
0221     spinlock_t lock;
0222     struct ath6kl_irq_proc_registers irq_proc_reg;
0223     struct ath6kl_irq_enable_reg irq_en_reg;
0224     struct htc_target *htc_cnxt;
0225     struct ath6kl *ar;
0226 };
0227
0228 struct ath6kl_hif_ops {
0229     int (*read_write_sync)(struct ath6kl *ar, u32 addr, u8 *buf,
0230                    u32 len, u32 request);
0231     int (*write_async)(struct ath6kl *ar, u32 address, u8 *buffer,
0232                u32 length, u32 request, struct htc_packet *packet);
0233
0234     void (*irq_enable)(struct ath6kl *ar);
0235     void (*irq_disable)(struct ath6kl *ar);
0236
0237     struct hif_scatter_req *(*scatter_req_get)(struct ath6kl *ar);
0238     void (*scatter_req_add)(struct ath6kl *ar,
0239                 struct hif_scatter_req *s_req);
0240     int (*enable_scatter)(struct ath6kl *ar);
0241     int (*scat_req_rw) (struct ath6kl *ar,
0242                 struct hif_scatter_req *scat_req);
0243     void (*cleanup_scatter)(struct ath6kl *ar);
0244     int (*suspend)(struct ath6kl *ar, struct cfg80211_wowlan *wow);
0245     int (*resume)(struct ath6kl *ar);
0246     int (*diag_read32)(struct ath6kl *ar, u32 address, u32 *value);
0247     int (*diag_write32)(struct ath6kl *ar, u32 address, __le32 value);
0248     int (*bmi_read)(struct ath6kl *ar, u8 *buf, u32 len);
0249     int (*bmi_write)(struct ath6kl *ar, u8 *buf, u32 len);
0250     int (*power_on)(struct ath6kl *ar);
0251     int (*power_off)(struct ath6kl *ar);
0252     void (*stop)(struct ath6kl *ar);
0253     int (*pipe_send)(struct ath6kl *ar, u8 pipe, struct sk_buff *hdr_buf,
0254              struct sk_buff *buf);
0255     void (*pipe_get_default)(struct ath6kl *ar, u8 *pipe_ul, u8 *pipe_dl);
0256     int (*pipe_map_service)(struct ath6kl *ar, u16 service_id, u8 *pipe_ul,
0257                 u8 *pipe_dl);
0258     u16 (*pipe_get_free_queue_number)(struct ath6kl *ar, u8 pipe);
0259 };
0260
0261 int ath6kl_hif_setup(struct ath6kl_device *dev);
0262 int ath6kl_hif_unmask_intrs(struct ath6kl_device *dev);
0263 int ath6kl_hif_mask_intrs(struct ath6kl_device *dev);
0264 int ath6kl_hif_poll_mboxmsg_rx(struct ath6kl_device *dev,
0265                    u32 *lk_ahd, int timeout);
0266 int ath6kl_hif_rx_control(struct ath6kl_device *dev, bool enable_rx);
0267 int ath6kl_hif_disable_intrs(struct ath6kl_device *dev);
0268
0269 int ath6kl_hif_rw_comp_handler(void *context, int status);
0270 int ath6kl_hif_intr_bh_handler(struct ath6kl *ar);
0271
0272 /* Scatter Function and Definitions */
0273 int ath6kl_hif_submit_scat_req(struct ath6kl_device *dev,
0274                    struct hif_scatter_req *scat_req, bool read);
0275
0276 #endif