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0018 #ifndef CORE_H
0019 #define CORE_H
0020
0021 #include <linux/etherdevice.h>
0022 #include <linux/rtnetlink.h>
0023 #include <linux/firmware.h>
0024 #include <linux/sched.h>
0025 #include <linux/circ_buf.h>
0026 #include <net/cfg80211.h>
0027 #include "htc.h"
0028 #include "wmi.h"
0029 #include "bmi.h"
0030 #include "target.h"
0031
0032 #define MAX_ATH6KL 1
0033 #define ATH6KL_MAX_RX_BUFFERS 16
0034 #define ATH6KL_BUFFER_SIZE 1664
0035 #define ATH6KL_MAX_AMSDU_RX_BUFFERS 4
0036 #define ATH6KL_AMSDU_REFILL_THRESHOLD 3
0037 #define ATH6KL_AMSDU_BUFFER_SIZE (WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH + 128)
0038 #define MAX_MSDU_SUBFRAME_PAYLOAD_LEN 1508
0039 #define MIN_MSDU_SUBFRAME_PAYLOAD_LEN 46
0040
0041 #define USER_SAVEDKEYS_STAT_INIT 0
0042 #define USER_SAVEDKEYS_STAT_RUN 1
0043
0044 #define ATH6KL_TX_TIMEOUT 10
0045 #define ATH6KL_MAX_ENDPOINTS 4
0046 #define MAX_NODE_NUM 15
0047
0048 #define ATH6KL_APSD_ALL_FRAME 0xFFFF
0049 #define ATH6KL_APSD_NUM_OF_AC 0x4
0050 #define ATH6KL_APSD_FRAME_MASK 0xF
0051
0052
0053 #define ATH6KL_HTC_ALIGN_BYTES 3
0054
0055
0056 #define MAX_DEF_COOKIE_NUM 180
0057 #define MAX_HI_COOKIE_NUM 18
0058 #define MAX_COOKIE_NUM (MAX_DEF_COOKIE_NUM + MAX_HI_COOKIE_NUM)
0059
0060 #define MAX_DEFAULT_SEND_QUEUE_DEPTH (MAX_DEF_COOKIE_NUM / WMM_NUM_AC)
0061
0062 #define DISCON_TIMER_INTVAL 10000
0063
0064
0065 #define ATH6KL_FG_SCAN_INTERVAL 50
0066
0067
0068 #define ATH6KL_FIRMWARE_MAGIC "QCA-ATH6KL"
0069
0070 enum ath6kl_fw_ie_type {
0071 ATH6KL_FW_IE_FW_VERSION = 0,
0072 ATH6KL_FW_IE_TIMESTAMP = 1,
0073 ATH6KL_FW_IE_OTP_IMAGE = 2,
0074 ATH6KL_FW_IE_FW_IMAGE = 3,
0075 ATH6KL_FW_IE_PATCH_IMAGE = 4,
0076 ATH6KL_FW_IE_RESERVED_RAM_SIZE = 5,
0077 ATH6KL_FW_IE_CAPABILITIES = 6,
0078 ATH6KL_FW_IE_PATCH_ADDR = 7,
0079 ATH6KL_FW_IE_BOARD_ADDR = 8,
0080 ATH6KL_FW_IE_VIF_MAX = 9,
0081 };
0082
0083 enum ath6kl_fw_capability {
0084 ATH6KL_FW_CAPABILITY_HOST_P2P = 0,
0085 ATH6KL_FW_CAPABILITY_SCHED_SCAN = 1,
0086
0087
0088
0089
0090
0091
0092 ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX,
0093
0094
0095
0096
0097
0098 ATH6KL_FW_CAPABILITY_INACTIVITY_TIMEOUT,
0099
0100
0101 ATH6KL_FW_CAPABILITY_RSN_CAP_OVERRIDE,
0102
0103
0104
0105
0106
0107
0108 ATH6KL_FW_CAPABILITY_WOW_MULTICAST_FILTER,
0109
0110
0111 ATH6KL_FW_CAPABILITY_BMISS_ENHANCE,
0112
0113
0114
0115
0116 ATH6KL_FW_CAPABILITY_SCHED_SCAN_MATCH_LIST,
0117
0118
0119 ATH6KL_FW_CAPABILITY_RSSI_SCAN_THOLD,
0120
0121
0122 ATH6KL_FW_CAPABILITY_CUSTOM_MAC_ADDR,
0123
0124
0125 ATH6KL_FW_CAPABILITY_TX_ERR_NOTIFY,
0126
0127
0128 ATH6KL_FW_CAPABILITY_REGDOMAIN,
0129
0130
0131 ATH6KL_FW_CAPABILITY_SCHED_SCAN_V2,
0132
0133
0134
0135
0136
0137 ATH6KL_FW_CAPABILITY_HEART_BEAT_POLL,
0138
0139
0140 ATH6KL_FW_CAPABILITY_64BIT_RATES,
0141
0142
0143 ATH6KL_FW_CAPABILITY_AP_INACTIVITY_MINS,
0144
0145
0146 ATH6KL_FW_CAPABILITY_MAP_LP_ENDPOINT,
0147
0148
0149 ATH6KL_FW_CAPABILITY_RATETABLE_MCS15,
0150
0151
0152 ATH6KL_FW_CAPABILITY_NO_IP_CHECKSUM,
0153
0154
0155 ATH6KL_FW_CAPABILITY_MAX,
0156 };
0157
0158 #define ATH6KL_CAPABILITY_LEN (ALIGN(ATH6KL_FW_CAPABILITY_MAX, 32) / 32)
0159
0160 struct ath6kl_fw_ie {
0161 __le32 id;
0162 __le32 len;
0163 u8 data[];
0164 };
0165
0166 enum ath6kl_hw_flags {
0167 ATH6KL_HW_SDIO_CRC_ERROR_WAR = BIT(3),
0168 };
0169
0170 #define ATH6KL_FW_API2_FILE "fw-2.bin"
0171 #define ATH6KL_FW_API3_FILE "fw-3.bin"
0172 #define ATH6KL_FW_API4_FILE "fw-4.bin"
0173 #define ATH6KL_FW_API5_FILE "fw-5.bin"
0174
0175
0176 #define AR6003_HW_1_0_VERSION 0x300002ba
0177
0178
0179 #define AR6003_HW_2_0_VERSION 0x30000384
0180 #define AR6003_HW_2_0_PATCH_DOWNLOAD_ADDRESS 0x57e910
0181 #define AR6003_HW_2_0_FW_DIR "ath6k/AR6003/hw2.0"
0182 #define AR6003_HW_2_0_OTP_FILE "otp.bin.z77"
0183 #define AR6003_HW_2_0_FIRMWARE_FILE "athwlan.bin.z77"
0184 #define AR6003_HW_2_0_TCMD_FIRMWARE_FILE "athtcmd_ram.bin"
0185 #define AR6003_HW_2_0_PATCH_FILE "data.patch.bin"
0186 #define AR6003_HW_2_0_BOARD_DATA_FILE AR6003_HW_2_0_FW_DIR "/bdata.bin"
0187 #define AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE \
0188 AR6003_HW_2_0_FW_DIR "/bdata.SD31.bin"
0189
0190
0191 #define AR6003_HW_2_1_1_VERSION 0x30000582
0192 #define AR6003_HW_2_1_1_FW_DIR "ath6k/AR6003/hw2.1.1"
0193 #define AR6003_HW_2_1_1_OTP_FILE "otp.bin"
0194 #define AR6003_HW_2_1_1_FIRMWARE_FILE "athwlan.bin"
0195 #define AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE "athtcmd_ram.bin"
0196 #define AR6003_HW_2_1_1_UTF_FIRMWARE_FILE "utf.bin"
0197 #define AR6003_HW_2_1_1_TESTSCRIPT_FILE "nullTestFlow.bin"
0198 #define AR6003_HW_2_1_1_PATCH_FILE "data.patch.bin"
0199 #define AR6003_HW_2_1_1_BOARD_DATA_FILE AR6003_HW_2_1_1_FW_DIR "/bdata.bin"
0200 #define AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE \
0201 AR6003_HW_2_1_1_FW_DIR "/bdata.SD31.bin"
0202
0203
0204 #define AR6004_HW_1_0_VERSION 0x30000623
0205 #define AR6004_HW_1_0_FW_DIR "ath6k/AR6004/hw1.0"
0206 #define AR6004_HW_1_0_FIRMWARE_FILE "fw.ram.bin"
0207 #define AR6004_HW_1_0_BOARD_DATA_FILE AR6004_HW_1_0_FW_DIR "/bdata.bin"
0208 #define AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE \
0209 AR6004_HW_1_0_FW_DIR "/bdata.DB132.bin"
0210
0211
0212 #define AR6004_HW_1_1_VERSION 0x30000001
0213 #define AR6004_HW_1_1_FW_DIR "ath6k/AR6004/hw1.1"
0214 #define AR6004_HW_1_1_FIRMWARE_FILE "fw.ram.bin"
0215 #define AR6004_HW_1_1_BOARD_DATA_FILE AR6004_HW_1_1_FW_DIR "/bdata.bin"
0216 #define AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE \
0217 AR6004_HW_1_1_FW_DIR "/bdata.DB132.bin"
0218
0219
0220 #define AR6004_HW_1_2_VERSION 0x300007e8
0221 #define AR6004_HW_1_2_FW_DIR "ath6k/AR6004/hw1.2"
0222 #define AR6004_HW_1_2_FIRMWARE_FILE "fw.ram.bin"
0223 #define AR6004_HW_1_2_BOARD_DATA_FILE AR6004_HW_1_2_FW_DIR "/bdata.bin"
0224 #define AR6004_HW_1_2_DEFAULT_BOARD_DATA_FILE \
0225 AR6004_HW_1_2_FW_DIR "/bdata.bin"
0226
0227
0228 #define AR6004_HW_1_3_VERSION 0x31c8088a
0229 #define AR6004_HW_1_3_FW_DIR "ath6k/AR6004/hw1.3"
0230 #define AR6004_HW_1_3_FIRMWARE_FILE "fw.ram.bin"
0231 #define AR6004_HW_1_3_TCMD_FIRMWARE_FILE "utf.bin"
0232 #define AR6004_HW_1_3_UTF_FIRMWARE_FILE "utf.bin"
0233 #define AR6004_HW_1_3_TESTSCRIPT_FILE "nullTestFlow.bin"
0234 #define AR6004_HW_1_3_BOARD_DATA_FILE AR6004_HW_1_3_FW_DIR "/bdata.bin"
0235 #define AR6004_HW_1_3_DEFAULT_BOARD_DATA_FILE AR6004_HW_1_3_FW_DIR "/bdata.bin"
0236
0237
0238 #define AR6004_HW_3_0_VERSION 0x31C809F8
0239 #define AR6004_HW_3_0_FW_DIR "ath6k/AR6004/hw3.0"
0240 #define AR6004_HW_3_0_FIRMWARE_FILE "fw.ram.bin"
0241 #define AR6004_HW_3_0_TCMD_FIRMWARE_FILE "utf.bin"
0242 #define AR6004_HW_3_0_UTF_FIRMWARE_FILE "utf.bin"
0243 #define AR6004_HW_3_0_TESTSCRIPT_FILE "nullTestFlow.bin"
0244 #define AR6004_HW_3_0_BOARD_DATA_FILE AR6004_HW_3_0_FW_DIR "/bdata.bin"
0245 #define AR6004_HW_3_0_DEFAULT_BOARD_DATA_FILE AR6004_HW_3_0_FW_DIR "/bdata.bin"
0246
0247
0248 #define STA_PS_AWAKE BIT(0)
0249 #define STA_PS_SLEEP BIT(1)
0250 #define STA_PS_POLLED BIT(2)
0251 #define STA_PS_APSD_TRIGGER BIT(3)
0252 #define STA_PS_APSD_EOSP BIT(4)
0253
0254
0255 #define ATH6KL_CONTROL_PKT_TAG HTC_TX_PACKET_TAG_USER_DEFINED
0256 #define ATH6KL_DATA_PKT_TAG (ATH6KL_CONTROL_PKT_TAG + 1)
0257
0258 #define AR6003_CUST_DATA_SIZE 16
0259
0260 #define AGGR_WIN_IDX(x, y) ((x) % (y))
0261 #define AGGR_INCR_IDX(x, y) AGGR_WIN_IDX(((x) + 1), (y))
0262 #define AGGR_DCRM_IDX(x, y) AGGR_WIN_IDX(((x) - 1), (y))
0263 #define ATH6KL_MAX_SEQ_NO 0xFFF
0264 #define ATH6KL_NEXT_SEQ_NO(x) (((x) + 1) & ATH6KL_MAX_SEQ_NO)
0265
0266 #define NUM_OF_TIDS 8
0267 #define AGGR_SZ_DEFAULT 8
0268
0269 #define AGGR_WIN_SZ_MIN 2
0270 #define AGGR_WIN_SZ_MAX 8
0271
0272 #define TID_WINDOW_SZ(_x) ((_x) << 1)
0273
0274 #define AGGR_NUM_OF_FREE_NETBUFS 16
0275
0276 #define AGGR_RX_TIMEOUT 100
0277
0278 #define WMI_TIMEOUT (2 * HZ)
0279
0280 #define MBOX_YIELD_LIMIT 99
0281
0282 #define ATH6KL_DEFAULT_LISTEN_INTVAL 100
0283 #define ATH6KL_DEFAULT_BMISS_TIME 1500
0284 #define ATH6KL_MAX_WOW_LISTEN_INTL 300
0285 #define ATH6KL_MAX_BMISS_TIME 5000
0286
0287
0288
0289
0290
0291
0292
0293
0294
0295
0296 #define ATH6KL_CONF_IGNORE_ERP_BARKER BIT(0)
0297 #define ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN BIT(1)
0298 #define ATH6KL_CONF_ENABLE_11N BIT(2)
0299 #define ATH6KL_CONF_ENABLE_TX_BURST BIT(3)
0300 #define ATH6KL_CONF_UART_DEBUG BIT(4)
0301
0302 #define P2P_WILDCARD_SSID_LEN 7
0303
0304 enum wlan_low_pwr_state {
0305 WLAN_POWER_STATE_ON,
0306 WLAN_POWER_STATE_CUT_PWR,
0307 WLAN_POWER_STATE_DEEP_SLEEP,
0308 WLAN_POWER_STATE_WOW
0309 };
0310
0311 enum sme_state {
0312 SME_DISCONNECTED,
0313 SME_CONNECTING,
0314 SME_CONNECTED
0315 };
0316
0317 struct skb_hold_q {
0318 struct sk_buff *skb;
0319 bool is_amsdu;
0320 u16 seq_no;
0321 };
0322
0323 struct rxtid {
0324 bool aggr;
0325 bool timer_mon;
0326 u16 win_sz;
0327 u16 seq_next;
0328 u32 hold_q_sz;
0329 struct skb_hold_q *hold_q;
0330 struct sk_buff_head q;
0331
0332
0333
0334
0335
0336
0337
0338
0339
0340
0341
0342
0343 spinlock_t lock;
0344 };
0345
0346 struct rxtid_stats {
0347 u32 num_into_aggr;
0348 u32 num_dups;
0349 u32 num_oow;
0350 u32 num_mpdu;
0351 u32 num_amsdu;
0352 u32 num_delivered;
0353 u32 num_timeouts;
0354 u32 num_hole;
0355 u32 num_bar;
0356 };
0357
0358 struct aggr_info_conn {
0359 u8 aggr_sz;
0360 u8 timer_scheduled;
0361 struct timer_list timer;
0362 struct net_device *dev;
0363 struct rxtid rx_tid[NUM_OF_TIDS];
0364 struct rxtid_stats stat[NUM_OF_TIDS];
0365 struct aggr_info *aggr_info;
0366 };
0367
0368 struct aggr_info {
0369 struct aggr_info_conn *aggr_conn;
0370 struct sk_buff_head rx_amsdu_freeq;
0371 };
0372
0373 struct ath6kl_wep_key {
0374 u8 key_index;
0375 u8 key_len;
0376 u8 key[64];
0377 };
0378
0379 #define ATH6KL_KEY_SEQ_LEN 8
0380
0381 struct ath6kl_key {
0382 u8 key[WLAN_MAX_KEY_LEN];
0383 u8 key_len;
0384 u8 seq[ATH6KL_KEY_SEQ_LEN];
0385 u8 seq_len;
0386 u32 cipher;
0387 };
0388
0389 struct ath6kl_node_mapping {
0390 u8 mac_addr[ETH_ALEN];
0391 u8 ep_id;
0392 u8 tx_pend;
0393 };
0394
0395 struct ath6kl_cookie {
0396 struct sk_buff *skb;
0397 u32 map_no;
0398 struct htc_packet htc_pkt;
0399 struct ath6kl_cookie *arc_list_next;
0400 };
0401
0402 struct ath6kl_mgmt_buff {
0403 struct list_head list;
0404 u32 freq;
0405 u32 wait;
0406 u32 id;
0407 bool no_cck;
0408 size_t len;
0409 u8 buf[];
0410 };
0411
0412 struct ath6kl_sta {
0413 u16 sta_flags;
0414 u8 mac[ETH_ALEN];
0415 u8 aid;
0416 u8 keymgmt;
0417 u8 ucipher;
0418 u8 auth;
0419 u8 wpa_ie[ATH6KL_MAX_IE];
0420 struct sk_buff_head psq;
0421
0422
0423 spinlock_t psq_lock;
0424
0425 struct list_head mgmt_psq;
0426 size_t mgmt_psq_len;
0427 u8 apsd_info;
0428 struct sk_buff_head apsdq;
0429 struct aggr_info_conn *aggr_conn;
0430 };
0431
0432 struct ath6kl_version {
0433 u32 target_ver;
0434 u32 wlan_ver;
0435 u32 abi_ver;
0436 };
0437
0438 struct ath6kl_bmi {
0439 u32 cmd_credits;
0440 bool done_sent;
0441 u8 *cmd_buf;
0442 u32 max_data_size;
0443 u32 max_cmd_size;
0444 };
0445
0446 struct target_stats {
0447 u64 tx_pkt;
0448 u64 tx_byte;
0449 u64 tx_ucast_pkt;
0450 u64 tx_ucast_byte;
0451 u64 tx_mcast_pkt;
0452 u64 tx_mcast_byte;
0453 u64 tx_bcast_pkt;
0454 u64 tx_bcast_byte;
0455 u64 tx_rts_success_cnt;
0456 u64 tx_pkt_per_ac[4];
0457
0458 u64 tx_err;
0459 u64 tx_fail_cnt;
0460 u64 tx_retry_cnt;
0461 u64 tx_mult_retry_cnt;
0462 u64 tx_rts_fail_cnt;
0463
0464 u64 rx_pkt;
0465 u64 rx_byte;
0466 u64 rx_ucast_pkt;
0467 u64 rx_ucast_byte;
0468 u64 rx_mcast_pkt;
0469 u64 rx_mcast_byte;
0470 u64 rx_bcast_pkt;
0471 u64 rx_bcast_byte;
0472 u64 rx_frgment_pkt;
0473
0474 u64 rx_err;
0475 u64 rx_crc_err;
0476 u64 rx_key_cache_miss;
0477 u64 rx_decrypt_err;
0478 u64 rx_dupl_frame;
0479
0480 u64 tkip_local_mic_fail;
0481 u64 tkip_cnter_measures_invoked;
0482 u64 tkip_replays;
0483 u64 tkip_fmt_err;
0484 u64 ccmp_fmt_err;
0485 u64 ccmp_replays;
0486
0487 u64 pwr_save_fail_cnt;
0488
0489 u64 cs_bmiss_cnt;
0490 u64 cs_low_rssi_cnt;
0491 u64 cs_connect_cnt;
0492 u64 cs_discon_cnt;
0493
0494 s32 tx_ucast_rate;
0495 s32 rx_ucast_rate;
0496
0497 u32 lq_val;
0498
0499 u32 wow_pkt_dropped;
0500 u16 wow_evt_discarded;
0501
0502 s16 noise_floor_calib;
0503 s16 cs_rssi;
0504 s16 cs_ave_beacon_rssi;
0505 u8 cs_ave_beacon_snr;
0506 u8 cs_last_roam_msec;
0507 u8 cs_snr;
0508
0509 u8 wow_host_pkt_wakeups;
0510 u8 wow_host_evt_wakeups;
0511
0512 u32 arp_received;
0513 u32 arp_matched;
0514 u32 arp_replied;
0515 };
0516
0517 struct ath6kl_mbox_info {
0518 u32 htc_addr;
0519 u32 htc_ext_addr;
0520 u32 htc_ext_sz;
0521
0522 u32 block_size;
0523
0524 u32 gmbox_addr;
0525
0526 u32 gmbox_sz;
0527 };
0528
0529
0530
0531
0532
0533
0534
0535
0536
0537 #define ATH6KL_KEYBUF_SIZE 16
0538 #define ATH6KL_MICBUF_SIZE (8+8)
0539
0540 #define ATH6KL_KEY_XMIT 0x01
0541 #define ATH6KL_KEY_RECV 0x02
0542 #define ATH6KL_KEY_DEFAULT 0x80
0543
0544
0545 struct ath6kl_req_key {
0546 bool valid;
0547 u8 key_index;
0548 int key_type;
0549 u8 key[WLAN_MAX_KEY_LEN];
0550 u8 key_len;
0551 };
0552
0553 enum ath6kl_hif_type {
0554 ATH6KL_HIF_TYPE_SDIO,
0555 ATH6KL_HIF_TYPE_USB,
0556 };
0557
0558 enum ath6kl_htc_type {
0559 ATH6KL_HTC_TYPE_MBOX,
0560 ATH6KL_HTC_TYPE_PIPE,
0561 };
0562
0563
0564 #define ATH6K_MAX_MC_FILTERS_PER_LIST 7
0565 struct ath6kl_mc_filter {
0566 struct list_head list;
0567 char hw_addr[ATH6KL_MCAST_FILTER_MAC_ADDR_SIZE];
0568 };
0569
0570 struct ath6kl_htcap {
0571 bool ht_enable;
0572 u8 ampdu_factor;
0573 unsigned short cap_info;
0574 };
0575
0576
0577
0578
0579
0580 #define ATH6KL_VIF_MAX 3
0581
0582
0583 enum ath6kl_vif_state {
0584 CONNECTED,
0585 CONNECT_PEND,
0586 WMM_ENABLED,
0587 NETQ_STOPPED,
0588 DTIM_EXPIRED,
0589 CLEAR_BSSFILTER_ON_BEACON,
0590 DTIM_PERIOD_AVAIL,
0591 WLAN_ENABLED,
0592 STATS_UPDATE_PEND,
0593 HOST_SLEEP_MODE_CMD_PROCESSED,
0594 NETDEV_MCAST_ALL_ON,
0595 NETDEV_MCAST_ALL_OFF,
0596 SCHED_SCANNING,
0597 };
0598
0599 struct ath6kl_vif {
0600 struct list_head list;
0601 struct wireless_dev wdev;
0602 struct net_device *ndev;
0603 struct ath6kl *ar;
0604
0605 spinlock_t if_lock;
0606 u8 fw_vif_idx;
0607 unsigned long flags;
0608 int ssid_len;
0609 u8 ssid[IEEE80211_MAX_SSID_LEN];
0610 u8 dot11_auth_mode;
0611 u8 auth_mode;
0612 u8 prwise_crypto;
0613 u8 prwise_crypto_len;
0614 u8 grp_crypto;
0615 u8 grp_crypto_len;
0616 u8 def_txkey_index;
0617 u8 next_mode;
0618 u8 nw_type;
0619 u8 bssid[ETH_ALEN];
0620 u8 req_bssid[ETH_ALEN];
0621 u16 ch_hint;
0622 u16 bss_ch;
0623 struct ath6kl_wep_key wep_key_list[WMI_MAX_KEY_INDEX + 1];
0624 struct ath6kl_key keys[WMI_MAX_KEY_INDEX + 1];
0625 struct aggr_info *aggr_cntxt;
0626 struct ath6kl_htcap htcap[NUM_NL80211_BANDS];
0627
0628 struct timer_list disconnect_timer;
0629 struct timer_list sched_scan_timer;
0630
0631 struct cfg80211_scan_request *scan_req;
0632 enum sme_state sme_state;
0633 int reconnect_flag;
0634 u32 last_roc_id;
0635 u32 last_cancel_roc_id;
0636 u32 send_action_id;
0637 bool probe_req_report;
0638 u16 assoc_bss_beacon_int;
0639 u16 listen_intvl_t;
0640 u16 bmiss_time_t;
0641 u32 txe_intvl;
0642 u16 bg_scan_period;
0643 u8 assoc_bss_dtim_period;
0644 struct target_stats target_stats;
0645 struct wmi_connect_cmd profile;
0646 u16 rsn_capab;
0647
0648 struct list_head mc_filter;
0649 };
0650
0651 static inline struct ath6kl_vif *ath6kl_vif_from_wdev(struct wireless_dev *wdev)
0652 {
0653 return container_of(wdev, struct ath6kl_vif, wdev);
0654 }
0655
0656 #define WOW_LIST_ID 0
0657 #define WOW_HOST_REQ_DELAY 500
0658
0659 #define ATH6KL_SCHED_SCAN_RESULT_DELAY 5000
0660
0661
0662 enum ath6kl_dev_state {
0663 WMI_ENABLED,
0664 WMI_READY,
0665 WMI_CTRL_EP_FULL,
0666 TESTMODE,
0667 DESTROY_IN_PROGRESS,
0668 SKIP_SCAN,
0669 ROAM_TBL_PEND,
0670 FIRST_BOOT,
0671 RECOVERY_CLEANUP,
0672 };
0673
0674 enum ath6kl_state {
0675 ATH6KL_STATE_OFF,
0676 ATH6KL_STATE_ON,
0677 ATH6KL_STATE_SUSPENDING,
0678 ATH6KL_STATE_RESUMING,
0679 ATH6KL_STATE_DEEPSLEEP,
0680 ATH6KL_STATE_CUTPOWER,
0681 ATH6KL_STATE_WOW,
0682 ATH6KL_STATE_RECOVERY,
0683 };
0684
0685
0686 #define ATH6KL_HB_RESP_MISS_THRES 5
0687
0688 enum ath6kl_fw_err {
0689 ATH6KL_FW_ASSERT,
0690 ATH6KL_FW_HB_RESP_FAILURE,
0691 ATH6KL_FW_EP_FULL,
0692 };
0693
0694 struct ath6kl {
0695 struct device *dev;
0696 struct wiphy *wiphy;
0697
0698 enum ath6kl_state state;
0699 unsigned int testmode;
0700
0701 struct ath6kl_bmi bmi;
0702 const struct ath6kl_hif_ops *hif_ops;
0703 const struct ath6kl_htc_ops *htc_ops;
0704 struct wmi *wmi;
0705 int tx_pending[ENDPOINT_MAX];
0706 int total_tx_data_pend;
0707 struct htc_target *htc_target;
0708 enum ath6kl_hif_type hif_type;
0709 void *hif_priv;
0710 struct list_head vif_list;
0711
0712 spinlock_t list_lock;
0713 u8 num_vif;
0714 unsigned int vif_max;
0715 u8 max_norm_iface;
0716 u8 avail_idx_map;
0717
0718
0719
0720
0721
0722 spinlock_t lock;
0723
0724 struct semaphore sem;
0725 u8 lrssi_roam_threshold;
0726 struct ath6kl_version version;
0727 u32 target_type;
0728 u8 tx_pwr;
0729 struct ath6kl_node_mapping node_map[MAX_NODE_NUM];
0730 u8 ibss_ps_enable;
0731 bool ibss_if_active;
0732 u8 node_num;
0733 u8 next_ep_id;
0734 struct ath6kl_cookie *cookie_list;
0735 u32 cookie_count;
0736 enum htc_endpoint_id ac2ep_map[WMM_NUM_AC];
0737 bool ac_stream_active[WMM_NUM_AC];
0738 u8 ac_stream_pri_map[WMM_NUM_AC];
0739 u8 hiac_stream_active_pri;
0740 u8 ep2ac_map[ENDPOINT_MAX];
0741 enum htc_endpoint_id ctrl_ep;
0742 struct ath6kl_htc_credit_info credit_state_info;
0743 u32 connect_ctrl_flags;
0744 u32 user_key_ctrl;
0745 u8 usr_bss_filter;
0746 struct ath6kl_sta sta_list[AP_MAX_NUM_STA];
0747 u8 sta_list_index;
0748 struct ath6kl_req_key ap_mode_bkey;
0749 struct sk_buff_head mcastpsq;
0750 u32 want_ch_switch;
0751 u16 last_ch;
0752
0753
0754
0755
0756
0757 spinlock_t mcastpsq_lock;
0758
0759 u8 intra_bss;
0760 struct wmi_ap_mode_stat ap_stats;
0761 u8 ap_country_code[3];
0762 struct list_head amsdu_rx_buffer_queue;
0763 u8 rx_meta_ver;
0764 enum wlan_low_pwr_state wlan_pwr_state;
0765 u8 mac_addr[ETH_ALEN];
0766 #define AR_MCAST_FILTER_MAC_ADDR_SIZE 4
0767 struct {
0768 void *rx_report;
0769 size_t rx_report_len;
0770 } tm;
0771
0772 struct ath6kl_hw {
0773 u32 id;
0774 const char *name;
0775 u32 dataset_patch_addr;
0776 u32 app_load_addr;
0777 u32 app_start_override_addr;
0778 u32 board_ext_data_addr;
0779 u32 reserved_ram_size;
0780 u32 board_addr;
0781 u32 refclk_hz;
0782 u32 uarttx_pin;
0783 u32 uarttx_rate;
0784 u32 testscript_addr;
0785 u8 tx_ant;
0786 u8 rx_ant;
0787 enum wmi_phy_cap cap;
0788
0789 u32 flags;
0790
0791 struct ath6kl_hw_fw {
0792 const char *dir;
0793 const char *otp;
0794 const char *fw;
0795 const char *tcmd;
0796 const char *patch;
0797 const char *utf;
0798 const char *testscript;
0799 } fw;
0800
0801 const char *fw_board;
0802 const char *fw_default_board;
0803 } hw;
0804
0805 u16 conf_flags;
0806 u16 suspend_mode;
0807 u16 wow_suspend_mode;
0808 wait_queue_head_t event_wq;
0809 struct ath6kl_mbox_info mbox_info;
0810
0811 struct ath6kl_cookie cookie_mem[MAX_COOKIE_NUM];
0812 unsigned long flag;
0813
0814 u8 *fw_board;
0815 size_t fw_board_len;
0816
0817 u8 *fw_otp;
0818 size_t fw_otp_len;
0819
0820 u8 *fw;
0821 size_t fw_len;
0822
0823 u8 *fw_patch;
0824 size_t fw_patch_len;
0825
0826 u8 *fw_testscript;
0827 size_t fw_testscript_len;
0828
0829 unsigned int fw_api;
0830 unsigned long fw_capabilities[ATH6KL_CAPABILITY_LEN];
0831
0832 struct workqueue_struct *ath6kl_wq;
0833
0834 struct dentry *debugfs_phy;
0835
0836 bool p2p;
0837
0838 bool wiphy_registered;
0839
0840 struct ath6kl_fw_recovery {
0841 struct work_struct recovery_work;
0842 unsigned long err_reason;
0843 unsigned long hb_poll;
0844 struct timer_list hb_timer;
0845 u32 seq_num;
0846 bool hb_pending;
0847 u8 hb_misscnt;
0848 bool enable;
0849 } fw_recovery;
0850
0851 #ifdef CONFIG_ATH6KL_DEBUG
0852 struct {
0853 struct sk_buff_head fwlog_queue;
0854 struct completion fwlog_completion;
0855 bool fwlog_open;
0856
0857 u32 fwlog_mask;
0858
0859 unsigned int dbgfs_diag_reg;
0860 u32 diag_reg_addr_wr;
0861 u32 diag_reg_val_wr;
0862
0863 struct {
0864 unsigned int invalid_rate;
0865 } war_stats;
0866
0867 u8 *roam_tbl;
0868 unsigned int roam_tbl_len;
0869
0870 u8 keepalive;
0871 u8 disc_timeout;
0872 } debug;
0873 #endif
0874 };
0875
0876 static inline struct ath6kl *ath6kl_priv(struct net_device *dev)
0877 {
0878 return ((struct ath6kl_vif *) netdev_priv(dev))->ar;
0879 }
0880
0881 static inline u32 ath6kl_get_hi_item_addr(struct ath6kl *ar,
0882 u32 item_offset)
0883 {
0884 u32 addr = 0;
0885
0886 if (ar->target_type == TARGET_TYPE_AR6003)
0887 addr = ATH6KL_AR6003_HI_START_ADDR + item_offset;
0888 else if (ar->target_type == TARGET_TYPE_AR6004)
0889 addr = ATH6KL_AR6004_HI_START_ADDR + item_offset;
0890
0891 return addr;
0892 }
0893
0894 int ath6kl_configure_target(struct ath6kl *ar);
0895 void ath6kl_detect_error(unsigned long ptr);
0896 void disconnect_timer_handler(struct timer_list *t);
0897 void init_netdev(struct net_device *dev);
0898 void ath6kl_cookie_init(struct ath6kl *ar);
0899 void ath6kl_cookie_cleanup(struct ath6kl *ar);
0900 void ath6kl_rx(struct htc_target *target, struct htc_packet *packet);
0901 void ath6kl_tx_complete(struct htc_target *context,
0902 struct list_head *packet_queue);
0903 enum htc_send_full_action ath6kl_tx_queue_full(struct htc_target *target,
0904 struct htc_packet *packet);
0905 void ath6kl_stop_txrx(struct ath6kl *ar);
0906 void ath6kl_cleanup_amsdu_rxbufs(struct ath6kl *ar);
0907 int ath6kl_diag_write32(struct ath6kl *ar, u32 address, __le32 value);
0908 int ath6kl_diag_write(struct ath6kl *ar, u32 address, void *data, u32 length);
0909 int ath6kl_diag_read32(struct ath6kl *ar, u32 address, u32 *value);
0910 int ath6kl_diag_read(struct ath6kl *ar, u32 address, void *data, u32 length);
0911 int ath6kl_read_fwlogs(struct ath6kl *ar);
0912 void ath6kl_init_profile_info(struct ath6kl_vif *vif);
0913 void ath6kl_tx_data_cleanup(struct ath6kl *ar);
0914
0915 struct ath6kl_cookie *ath6kl_alloc_cookie(struct ath6kl *ar);
0916 void ath6kl_free_cookie(struct ath6kl *ar, struct ath6kl_cookie *cookie);
0917 netdev_tx_t ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev);
0918
0919 struct aggr_info *aggr_init(struct ath6kl_vif *vif);
0920 void aggr_conn_init(struct ath6kl_vif *vif, struct aggr_info *aggr_info,
0921 struct aggr_info_conn *aggr_conn);
0922 void ath6kl_rx_refill(struct htc_target *target,
0923 enum htc_endpoint_id endpoint);
0924 void ath6kl_refill_amsdu_rxbufs(struct ath6kl *ar, int count);
0925 struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target,
0926 enum htc_endpoint_id endpoint,
0927 int len);
0928 void aggr_module_destroy(struct aggr_info *aggr_info);
0929 void aggr_reset_state(struct aggr_info_conn *aggr_conn);
0930
0931 struct ath6kl_sta *ath6kl_find_sta(struct ath6kl_vif *vif, u8 *node_addr);
0932 struct ath6kl_sta *ath6kl_find_sta_by_aid(struct ath6kl *ar, u8 aid);
0933
0934 void ath6kl_ready_event(void *devt, u8 *datap, u32 sw_ver, u32 abi_ver,
0935 enum wmi_phy_cap cap);
0936 int ath6kl_control_tx(void *devt, struct sk_buff *skb,
0937 enum htc_endpoint_id eid);
0938 void ath6kl_connect_event(struct ath6kl_vif *vif, u16 channel,
0939 u8 *bssid, u16 listen_int,
0940 u16 beacon_int, enum network_type net_type,
0941 u8 beacon_ie_len, u8 assoc_req_len,
0942 u8 assoc_resp_len, u8 *assoc_info);
0943 void ath6kl_connect_ap_mode_bss(struct ath6kl_vif *vif, u16 channel);
0944 void ath6kl_connect_ap_mode_sta(struct ath6kl_vif *vif, u16 aid, u8 *mac_addr,
0945 u8 keymgmt, u8 ucipher, u8 auth,
0946 u8 assoc_req_len, u8 *assoc_info, u8 apsd_info);
0947 void ath6kl_disconnect_event(struct ath6kl_vif *vif, u8 reason,
0948 u8 *bssid, u8 assoc_resp_len,
0949 u8 *assoc_info, u16 prot_reason_status);
0950 void ath6kl_tkip_micerr_event(struct ath6kl_vif *vif, u8 keyid, bool ismcast);
0951 void ath6kl_txpwr_rx_evt(void *devt, u8 tx_pwr);
0952 void ath6kl_scan_complete_evt(struct ath6kl_vif *vif, int status);
0953 void ath6kl_tgt_stats_event(struct ath6kl_vif *vif, u8 *ptr, u32 len);
0954 void ath6kl_indicate_tx_activity(void *devt, u8 traffic_class, bool active);
0955 enum htc_endpoint_id ath6kl_ac2_endpoint_id(void *devt, u8 ac);
0956
0957 void ath6kl_pspoll_event(struct ath6kl_vif *vif, u8 aid);
0958
0959 void ath6kl_dtimexpiry_event(struct ath6kl_vif *vif);
0960 void ath6kl_disconnect(struct ath6kl_vif *vif);
0961 void aggr_recv_delba_req_evt(struct ath6kl_vif *vif, u8 tid);
0962 void aggr_recv_addba_req_evt(struct ath6kl_vif *vif, u8 tid, u16 seq_no,
0963 u8 win_sz);
0964 void ath6kl_wakeup_event(void *dev);
0965
0966 void ath6kl_init_control_info(struct ath6kl_vif *vif);
0967 struct ath6kl_vif *ath6kl_vif_first(struct ath6kl *ar);
0968 void ath6kl_cfg80211_vif_stop(struct ath6kl_vif *vif, bool wmi_ready);
0969 int ath6kl_init_hw_start(struct ath6kl *ar);
0970 int ath6kl_init_hw_stop(struct ath6kl *ar);
0971 int ath6kl_init_fetch_firmwares(struct ath6kl *ar);
0972 int ath6kl_init_hw_params(struct ath6kl *ar);
0973
0974 void ath6kl_check_wow_status(struct ath6kl *ar);
0975
0976 void ath6kl_core_tx_complete(struct ath6kl *ar, struct sk_buff *skb);
0977 void ath6kl_core_rx_complete(struct ath6kl *ar, struct sk_buff *skb, u8 pipe);
0978
0979 struct ath6kl *ath6kl_core_create(struct device *dev);
0980 int ath6kl_core_init(struct ath6kl *ar, enum ath6kl_htc_type htc_type);
0981 void ath6kl_core_cleanup(struct ath6kl *ar);
0982 void ath6kl_core_destroy(struct ath6kl *ar);
0983
0984
0985 void ath6kl_init_hw_restart(struct ath6kl *ar);
0986 void ath6kl_recovery_err_notify(struct ath6kl *ar, enum ath6kl_fw_err reason);
0987 void ath6kl_recovery_hb_event(struct ath6kl *ar, u32 cookie);
0988 void ath6kl_recovery_init(struct ath6kl *ar);
0989 void ath6kl_recovery_cleanup(struct ath6kl *ar);
0990 void ath6kl_recovery_suspend(struct ath6kl *ar);
0991 void ath6kl_recovery_resume(struct ath6kl *ar);
0992 #endif