ath/ath6kl/bmi.h

0001 /*
0002  * Copyright (c) 2004-2011 Atheros Communications Inc.
0003  * Copyright (c) 2011 Qualcomm Atheros, Inc.
0004  *
0005  * Permission to use, copy, modify, and/or distribute this software for any
0006  * purpose with or without fee is hereby granted, provided that the above
0007  * copyright notice and this permission notice appear in all copies.
0008  *
0009  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0010  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0011  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0012  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0013  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0014  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0015  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0016  */
0017
0018 #ifndef BMI_H
0019 #define BMI_H
0020
0021 /*
0022  * Bootloader Messaging Interface (BMI)
0023  *
0024  * BMI is a very simple messaging interface used during initialization
0025  * to read memory, write memory, execute code, and to define an
0026  * application entry PC.
0027  *
0028  * It is used to download an application to ATH6KL, to provide
0029  * patches to code that is already resident on ATH6KL, and generally
0030  * to examine and modify state.  The Host has an opportunity to use
0031  * BMI only once during bootup.  Once the Host issues a BMI_DONE
0032  * command, this opportunity ends.
0033  *
0034  * The Host writes BMI requests to mailbox0, and reads BMI responses
0035  * from mailbox0.   BMI requests all begin with a command
0036  * (see below for specific commands), and are followed by
0037  * command-specific data.
0038  *
0039  * Flow control:
0040  * The Host can only issue a command once the Target gives it a
0041  * "BMI Command Credit", using ATH6KL Counter #4.  As soon as the
0042  * Target has completed a command, it issues another BMI Command
0043  * Credit (so the Host can issue the next command).
0044  *
0045  * BMI handles all required Target-side cache flushing.
0046  */
0047
0048 /* BMI Commands */
0049
0050 #define BMI_NO_COMMAND                      0
0051
0052 #define BMI_DONE                            1
0053 /*
0054  * Semantics: Host is done using BMI
0055  * Request format:
0056  *    u32 command (BMI_DONE)
0057  * Response format: none
0058  */
0059
0060 #define BMI_READ_MEMORY                     2
0061 /*
0062  * Semantics: Host reads ATH6KL memory
0063  * Request format:
0064  *    u32 command (BMI_READ_MEMORY)
0065  *    u32 address
0066  *    u32 length, at most BMI_DATASZ_MAX
0067  * Response format:
0068  *    u8 data[length]
0069  */
0070
0071 #define BMI_WRITE_MEMORY                    3
0072 /*
0073  * Semantics: Host writes ATH6KL memory
0074  * Request format:
0075  *    u32 command (BMI_WRITE_MEMORY)
0076  *    u32 address
0077  *    u32 length, at most BMI_DATASZ_MAX
0078  *    u8 data[length]
0079  * Response format: none
0080  */
0081
0082 #define BMI_EXECUTE                         4
0083 /*
0084  * Semantics: Causes ATH6KL to execute code
0085  * Request format:
0086  *    u32 command (BMI_EXECUTE)
0087  *    u32 address
0088  *    u32 parameter
0089  * Response format:
0090  *    u32 return value
0091  */
0092
0093 #define BMI_SET_APP_START                   5
0094 /*
0095  * Semantics: Set Target application starting address
0096  * Request format:
0097  *    u32 command (BMI_SET_APP_START)
0098  *    u32 address
0099  * Response format: none
0100  */
0101
0102 #define BMI_READ_SOC_REGISTER               6
0103 /*
0104  * Semantics: Read a 32-bit Target SOC register.
0105  * Request format:
0106  *    u32 command (BMI_READ_REGISTER)
0107  *    u32 address
0108  * Response format:
0109  *    u32 value
0110  */
0111
0112 #define BMI_WRITE_SOC_REGISTER              7
0113 /*
0114  * Semantics: Write a 32-bit Target SOC register.
0115  * Request format:
0116  *    u32 command (BMI_WRITE_REGISTER)
0117  *    u32 address
0118  *    u32 value
0119  *
0120  * Response format: none
0121  */
0122
0123 #define BMI_GET_TARGET_ID                  8
0124 #define BMI_GET_TARGET_INFO                8
0125 /*
0126  * Semantics: Fetch the 4-byte Target information
0127  * Request format:
0128  *    u32 command (BMI_GET_TARGET_ID/INFO)
0129  * Response format1 (old firmware):
0130  *    u32 TargetVersionID
0131  * Response format2 (newer firmware):
0132  *    u32 TARGET_VERSION_SENTINAL
0133  *    struct bmi_target_info;
0134  */
0135
0136 #define TARGET_VERSION_SENTINAL 0xffffffff
0137 #define TARGET_TYPE_AR6003      3
0138 #define TARGET_TYPE_AR6004      5
0139 #define BMI_ROMPATCH_INSTALL               9
0140 /*
0141  * Semantics: Install a ROM Patch.
0142  * Request format:
0143  *    u32 command (BMI_ROMPATCH_INSTALL)
0144  *    u32 Target ROM Address
0145  *    u32 Target RAM Address or Value (depending on Target Type)
0146  *    u32 Size, in bytes
0147  *    u32 Activate? 1-->activate;
0148  *                            0-->install but do not activate
0149  * Response format:
0150  *    u32 PatchID
0151  */
0152
0153 #define BMI_ROMPATCH_UNINSTALL             10
0154 /*
0155  * Semantics: Uninstall a previously-installed ROM Patch,
0156  * automatically deactivating, if necessary.
0157  * Request format:
0158  *    u32 command (BMI_ROMPATCH_UNINSTALL)
0159  *    u32 PatchID
0160  *
0161  * Response format: none
0162  */
0163
0164 #define BMI_ROMPATCH_ACTIVATE              11
0165 /*
0166  * Semantics: Activate a list of previously-installed ROM Patches.
0167  * Request format:
0168  *    u32 command (BMI_ROMPATCH_ACTIVATE)
0169  *    u32 rompatch_count
0170  *    u32 PatchID[rompatch_count]
0171  *
0172  * Response format: none
0173  */
0174
0175 #define BMI_ROMPATCH_DEACTIVATE            12
0176 /*
0177  * Semantics: Deactivate a list of active ROM Patches.
0178  * Request format:
0179  *    u32 command (BMI_ROMPATCH_DEACTIVATE)
0180  *    u32 rompatch_count
0181  *    u32 PatchID[rompatch_count]
0182  *
0183  * Response format: none
0184  */
0185
0186
0187 #define BMI_LZ_STREAM_START                13
0188 /*
0189  * Semantics: Begin an LZ-compressed stream of input
0190  * which is to be uncompressed by the Target to an
0191  * output buffer at address.  The output buffer must
0192  * be sufficiently large to hold the uncompressed
0193  * output from the compressed input stream.  This BMI
0194  * command should be followed by a series of 1 or more
0195  * BMI_LZ_DATA commands.
0196  *    u32 command (BMI_LZ_STREAM_START)
0197  *    u32 address
0198  * Note: Not supported on all versions of ROM firmware.
0199  */
0200
0201 #define BMI_LZ_DATA                        14
0202 /*
0203  * Semantics: Host writes ATH6KL memory with LZ-compressed
0204  * data which is uncompressed by the Target.  This command
0205  * must be preceded by a BMI_LZ_STREAM_START command. A series
0206  * of BMI_LZ_DATA commands are considered part of a single
0207  * input stream until another BMI_LZ_STREAM_START is issued.
0208  * Request format:
0209  *    u32 command (BMI_LZ_DATA)
0210  *    u32 length (of compressed data),
0211  *                  at most BMI_DATASZ_MAX
0212  *    u8 CompressedData[length]
0213  * Response format: none
0214  * Note: Not supported on all versions of ROM firmware.
0215  */
0216
0217 #define BMI_COMMUNICATION_TIMEOUT       1000 /* in msec */
0218
0219 struct ath6kl;
0220 struct ath6kl_bmi_target_info {
0221     __le32 byte_count;   /* size of this structure */
0222     __le32 version;      /* target version id */
0223     __le32 type;         /* target type */
0224 } __packed;
0225
0226 #define ath6kl_bmi_write_hi32(ar, item, val)                \
0227     ({                              \
0228         u32 addr;                       \
0229         __le32 v;                       \
0230                                     \
0231         addr = ath6kl_get_hi_item_addr(ar, HI_ITEM(item));  \
0232         v = cpu_to_le32(val);                   \
0233         ath6kl_bmi_write(ar, addr, (u8 *) &v, sizeof(v));   \
0234     })
0235
0236 #define ath6kl_bmi_read_hi32(ar, item, val)             \
0237     ({                              \
0238         u32 addr, *check_type = val;                \
0239         __le32 tmp;                     \
0240         int ret;                        \
0241                                     \
0242         (void) (check_type == val);             \
0243         addr = ath6kl_get_hi_item_addr(ar, HI_ITEM(item));  \
0244         ret = ath6kl_bmi_read(ar, addr, (u8 *) &tmp, 4);    \
0245         if (!ret)                       \
0246             *val = le32_to_cpu(tmp);            \
0247         ret;                            \
0248     })
0249
0250 int ath6kl_bmi_init(struct ath6kl *ar);
0251 void ath6kl_bmi_cleanup(struct ath6kl *ar);
0252 void ath6kl_bmi_reset(struct ath6kl *ar);
0253
0254 int ath6kl_bmi_done(struct ath6kl *ar);
0255 int ath6kl_bmi_get_target_info(struct ath6kl *ar,
0256                    struct ath6kl_bmi_target_info *targ_info);
0257 int ath6kl_bmi_read(struct ath6kl *ar, u32 addr, u8 *buf, u32 len);
0258 int ath6kl_bmi_write(struct ath6kl *ar, u32 addr, u8 *buf, u32 len);
0259 int ath6kl_bmi_execute(struct ath6kl *ar,
0260                u32 addr, u32 *param);
0261 int ath6kl_bmi_set_app_start(struct ath6kl *ar,
0262                  u32 addr);
0263 int ath6kl_bmi_reg_read(struct ath6kl *ar, u32 addr, u32 *param);
0264 int ath6kl_bmi_reg_write(struct ath6kl *ar, u32 addr, u32 param);
0265 int ath6kl_bmi_lz_data(struct ath6kl *ar,
0266                u8 *buf, u32 len);
0267 int ath6kl_bmi_lz_stream_start(struct ath6kl *ar,
0268                    u32 addr);
0269 int ath6kl_bmi_fast_download(struct ath6kl *ar,
0270                  u32 addr, u8 *buf, u32 len);
0271 #endif