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0001 /*
0002  * RF Buffer handling functions
0003  *
0004  * Copyright (c) 2009 Nick Kossifidis <mickflemm@gmail.com>
0005  *
0006  * Permission to use, copy, modify, and distribute this software for any
0007  * purpose with or without fee is hereby granted, provided that the above
0008  * copyright notice and this permission notice appear in all copies.
0009  *
0010  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0011  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0012  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0013  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0014  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0015  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0016  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0017  *
0018  */
0019 
0020 
0021 /**
0022  * DOC: RF Buffer registers
0023  *
0024  * There are some special registers on the RF chip
0025  * that control various operation settings related mostly to
0026  * the analog parts (channel, gain adjustment etc).
0027  *
0028  * We don't write on those registers directly but
0029  * we send a data packet on the chip, using a special register,
0030  * that holds all the settings we need. After we've sent the
0031  * data packet, we write on another special register to notify hw
0032  * to apply the settings. This is done so that control registers
0033  * can be dynamically programmed during operation and the settings
0034  * are applied faster on the hw.
0035  *
0036  * We call each data packet an "RF Bank" and all the data we write
0037  * (all RF Banks) "RF Buffer". This file holds initial RF Buffer
0038  * data for the different RF chips, and various info to match RF
0039  * Buffer offsets with specific RF registers so that we can access
0040  * them. We tweak these settings on rfregs_init function.
0041  *
0042  * Also check out reg.h and U.S. Patent 6677779 B1 (about buffer
0043  * registers and control registers):
0044  *
0045  * https://www.google.com/patents?id=qNURAAAAEBAJ
0046  */
0047 
0048 
0049 /**
0050  * struct ath5k_ini_rfbuffer - Initial RF Buffer settings
0051  * @rfb_bank: RF Bank number
0052  * @rfb_ctrl_register: RF Buffer control register
0053  * @rfb_mode_data: RF Buffer data for each mode
0054  *
0055  * Struct to hold default mode specific RF
0056  * register values (RF Banks) for each chip.
0057  */
0058 struct ath5k_ini_rfbuffer {
0059     u8  rfb_bank;
0060     u16 rfb_ctrl_register;
0061     u32 rfb_mode_data[3];
0062 };
0063 
0064 /**
0065  * struct ath5k_rfb_field - An RF Buffer field (register/value)
0066  * @len: Field length
0067  * @pos: Offset on the raw packet
0068  * @col: Used for shifting
0069  *
0070  * Struct to hold RF Buffer field
0071  * infos used to access certain RF
0072  * analog registers
0073  */
0074 struct ath5k_rfb_field {
0075     u8  len;
0076     u16 pos;
0077     u8  col;
0078 };
0079 
0080 /**
0081  * struct ath5k_rf_reg - RF analog register definition
0082  * @bank: RF Buffer Bank number
0083  * @index: Register's index on ath5k_rf_regx_idx
0084  * @field: The &struct ath5k_rfb_field
0085  *
0086  * We use this struct to define the set of RF registers
0087  * on each chip that we want to tweak. Some RF registers
0088  * are common between different chip versions so this saves
0089  * us space and complexity because we can refer to an rf
0090  * register by it's index no matter what chip we work with
0091  * as long as it has that register.
0092  */
0093 struct ath5k_rf_reg {
0094     u8          bank;
0095     u8          index;
0096     struct ath5k_rfb_field  field;
0097 };
0098 
0099 /**
0100  * enum ath5k_rf_regs_idx - Map RF registers to indexes
0101  *
0102  * We do this to handle common bits and make our
0103  * life easier by using an index for each register
0104  * instead of a full rfb_field
0105  */
0106 enum ath5k_rf_regs_idx {
0107     /* BANK 2 */
0108     AR5K_RF_TURBO = 0,
0109     /* BANK 6 */
0110     AR5K_RF_OB_2GHZ,
0111     AR5K_RF_OB_5GHZ,
0112     AR5K_RF_DB_2GHZ,
0113     AR5K_RF_DB_5GHZ,
0114     AR5K_RF_FIXED_BIAS_A,
0115     AR5K_RF_FIXED_BIAS_B,
0116     AR5K_RF_PWD_XPD,
0117     AR5K_RF_XPD_SEL,
0118     AR5K_RF_XPD_GAIN,
0119     AR5K_RF_PD_GAIN_LO,
0120     AR5K_RF_PD_GAIN_HI,
0121     AR5K_RF_HIGH_VC_CP,
0122     AR5K_RF_MID_VC_CP,
0123     AR5K_RF_LOW_VC_CP,
0124     AR5K_RF_PUSH_UP,
0125     AR5K_RF_PAD2GND,
0126     AR5K_RF_XB2_LVL,
0127     AR5K_RF_XB5_LVL,
0128     AR5K_RF_PWD_ICLOBUF_2G,
0129     AR5K_RF_PWD_84,
0130     AR5K_RF_PWD_90,
0131     AR5K_RF_PWD_130,
0132     AR5K_RF_PWD_131,
0133     AR5K_RF_PWD_132,
0134     AR5K_RF_PWD_136,
0135     AR5K_RF_PWD_137,
0136     AR5K_RF_PWD_138,
0137     AR5K_RF_PWD_166,
0138     AR5K_RF_PWD_167,
0139     AR5K_RF_DERBY_CHAN_SEL_MODE,
0140     /* BANK 7 */
0141     AR5K_RF_GAIN_I,
0142     AR5K_RF_PLO_SEL,
0143     AR5K_RF_RFGAIN_SEL,
0144     AR5K_RF_RFGAIN_STEP,
0145     AR5K_RF_WAIT_S,
0146     AR5K_RF_WAIT_I,
0147     AR5K_RF_MAX_TIME,
0148     AR5K_RF_MIXVGA_OVR,
0149     AR5K_RF_MIXGAIN_OVR,
0150     AR5K_RF_MIXGAIN_STEP,
0151     AR5K_RF_PD_DELAY_A,
0152     AR5K_RF_PD_DELAY_B,
0153     AR5K_RF_PD_DELAY_XR,
0154     AR5K_RF_PD_PERIOD_A,
0155     AR5K_RF_PD_PERIOD_B,
0156     AR5K_RF_PD_PERIOD_XR,
0157 };
0158 
0159 
0160 /*******************\
0161 * RF5111 (Sombrero) *
0162 \*******************/
0163 
0164 /* BANK 2               len  pos col */
0165 #define AR5K_RF5111_RF_TURBO        { 1, 3,   0 }
0166 
0167 /* BANK 6               len  pos col */
0168 #define AR5K_RF5111_OB_2GHZ     { 3, 119, 0 }
0169 #define AR5K_RF5111_DB_2GHZ     { 3, 122, 0 }
0170 
0171 #define AR5K_RF5111_OB_5GHZ     { 3, 104, 0 }
0172 #define AR5K_RF5111_DB_5GHZ     { 3, 107, 0 }
0173 
0174 #define AR5K_RF5111_PWD_XPD     { 1, 95,  0 }
0175 #define AR5K_RF5111_XPD_GAIN        { 4, 96,  0 }
0176 
0177 /* Access to PWD registers */
0178 #define AR5K_RF5111_PWD(_n)     { 1, (135 - _n), 3 }
0179 
0180 /* BANK 7               len  pos col */
0181 #define AR5K_RF5111_GAIN_I      { 6, 29,  0 }
0182 #define AR5K_RF5111_PLO_SEL     { 1, 4,   0 }
0183 #define AR5K_RF5111_RFGAIN_SEL      { 1, 36,  0 }
0184 #define AR5K_RF5111_RFGAIN_STEP     { 6, 37,  0 }
0185 /* Only on AR5212 BaseBand and up */
0186 #define AR5K_RF5111_WAIT_S      { 5, 19,  0 }
0187 #define AR5K_RF5111_WAIT_I      { 5, 24,  0 }
0188 #define AR5K_RF5111_MAX_TIME        { 2, 49,  0 }
0189 
0190 static const struct ath5k_rf_reg rf_regs_5111[] = {
0191     {2, AR5K_RF_TURBO,      AR5K_RF5111_RF_TURBO},
0192     {6, AR5K_RF_OB_2GHZ,        AR5K_RF5111_OB_2GHZ},
0193     {6, AR5K_RF_DB_2GHZ,        AR5K_RF5111_DB_2GHZ},
0194     {6, AR5K_RF_OB_5GHZ,        AR5K_RF5111_OB_5GHZ},
0195     {6, AR5K_RF_DB_5GHZ,        AR5K_RF5111_DB_5GHZ},
0196     {6, AR5K_RF_PWD_XPD,        AR5K_RF5111_PWD_XPD},
0197     {6, AR5K_RF_XPD_GAIN,       AR5K_RF5111_XPD_GAIN},
0198     {6, AR5K_RF_PWD_84,     AR5K_RF5111_PWD(84)},
0199     {6, AR5K_RF_PWD_90,     AR5K_RF5111_PWD(90)},
0200     {7, AR5K_RF_GAIN_I,     AR5K_RF5111_GAIN_I},
0201     {7, AR5K_RF_PLO_SEL,        AR5K_RF5111_PLO_SEL},
0202     {7, AR5K_RF_RFGAIN_SEL,     AR5K_RF5111_RFGAIN_SEL},
0203     {7, AR5K_RF_RFGAIN_STEP,    AR5K_RF5111_RFGAIN_STEP},
0204     {7, AR5K_RF_WAIT_S,     AR5K_RF5111_WAIT_S},
0205     {7, AR5K_RF_WAIT_I,     AR5K_RF5111_WAIT_I},
0206     {7, AR5K_RF_MAX_TIME,       AR5K_RF5111_MAX_TIME}
0207 };
0208 
0209 /* Default mode specific settings */
0210 static const struct ath5k_ini_rfbuffer rfb_5111[] = {
0211     /* BANK / C.R.     A/XR         B           G      */
0212     { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0213     { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0214     { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0215     { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0216     { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0217     { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0218     { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0219     { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0220     { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0221     { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0222     { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0223     { 0, 0x989c, { 0x00380000, 0x00380000, 0x00380000 } },
0224     { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0225     { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0226     { 0, 0x989c, { 0x00000000, 0x000000c0, 0x00000080 } },
0227     { 0, 0x989c, { 0x000400f9, 0x000400ff, 0x000400fd } },
0228     { 0, 0x98d4, { 0x00000000, 0x00000004, 0x00000004 } },
0229     { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
0230     { 2, 0x98d4, { 0x00000010, 0x00000010, 0x00000010 } },
0231     { 3, 0x98d8, { 0x00601068, 0x00601068, 0x00601068 } },
0232     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0233     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0234     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0235     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0236     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0237     { 6, 0x989c, { 0x10000000, 0x10000000, 0x10000000 } },
0238     { 6, 0x989c, { 0x04000000, 0x04000000, 0x04000000 } },
0239     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0240     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0241     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0242     { 6, 0x989c, { 0x00000000, 0x0a000000, 0x00000000 } },
0243     { 6, 0x989c, { 0x003800c0, 0x023800c0, 0x003800c0 } },
0244     { 6, 0x989c, { 0x00020006, 0x00000006, 0x00020006 } },
0245     { 6, 0x989c, { 0x00000089, 0x00000089, 0x00000089 } },
0246     { 6, 0x989c, { 0x000000a0, 0x000000a0, 0x000000a0 } },
0247     { 6, 0x989c, { 0x00040007, 0x00040007, 0x00040007 } },
0248     { 6, 0x98d4, { 0x0000001a, 0x0000001a, 0x0000001a } },
0249     { 7, 0x989c, { 0x00000040, 0x00000040, 0x00000040 } },
0250     { 7, 0x989c, { 0x00000010, 0x00000010, 0x00000010 } },
0251     { 7, 0x989c, { 0x00000008, 0x00000008, 0x00000008 } },
0252     { 7, 0x989c, { 0x0000004f, 0x0000004f, 0x0000004f } },
0253     { 7, 0x989c, { 0x000000f1, 0x00000061, 0x000000f1 } },
0254     { 7, 0x989c, { 0x0000904f, 0x0000904c, 0x0000904f } },
0255     { 7, 0x989c, { 0x0000125a, 0x0000129a, 0x0000125a } },
0256     { 7, 0x98cc, { 0x0000000e, 0x0000000f, 0x0000000e } },
0257 };
0258 
0259 
0260 
0261 /***********************\
0262 * RF5112/RF2112 (Derby) *
0263 \***********************/
0264 
0265 /* BANK 2 (Common)          len  pos col */
0266 #define AR5K_RF5112X_RF_TURBO       { 1, 1,   2 }
0267 
0268 /* BANK 7 (Common)          len  pos col */
0269 #define AR5K_RF5112X_GAIN_I     { 6, 14,  0 }
0270 #define AR5K_RF5112X_MIXVGA_OVR     { 1, 36,  0 }
0271 #define AR5K_RF5112X_MIXGAIN_OVR    { 2, 37,  0 }
0272 #define AR5K_RF5112X_MIXGAIN_STEP   { 4, 32,  0 }
0273 #define AR5K_RF5112X_PD_DELAY_A     { 4, 58,  0 }
0274 #define AR5K_RF5112X_PD_DELAY_B     { 4, 62,  0 }
0275 #define AR5K_RF5112X_PD_DELAY_XR    { 4, 66,  0 }
0276 #define AR5K_RF5112X_PD_PERIOD_A    { 4, 70,  0 }
0277 #define AR5K_RF5112X_PD_PERIOD_B    { 4, 74,  0 }
0278 #define AR5K_RF5112X_PD_PERIOD_XR   { 4, 78,  0 }
0279 
0280 /* RFX112 (Derby 1) */
0281 
0282 /* BANK 6               len  pos col */
0283 #define AR5K_RF5112_OB_2GHZ     { 3, 269, 0 }
0284 #define AR5K_RF5112_DB_2GHZ     { 3, 272, 0 }
0285 
0286 #define AR5K_RF5112_OB_5GHZ     { 3, 261, 0 }
0287 #define AR5K_RF5112_DB_5GHZ     { 3, 264, 0 }
0288 
0289 #define AR5K_RF5112_FIXED_BIAS_A    { 1, 260, 0 }
0290 #define AR5K_RF5112_FIXED_BIAS_B    { 1, 259, 0 }
0291 
0292 #define AR5K_RF5112_XPD_SEL     { 1, 284, 0 }
0293 #define AR5K_RF5112_XPD_GAIN        { 2, 252, 0 }
0294 
0295 /* Access to PWD registers */
0296 #define AR5K_RF5112_PWD(_n)     { 1, (302 - _n), 3 }
0297 
0298 static const struct ath5k_rf_reg rf_regs_5112[] = {
0299     {2, AR5K_RF_TURBO,      AR5K_RF5112X_RF_TURBO},
0300     {6, AR5K_RF_OB_2GHZ,        AR5K_RF5112_OB_2GHZ},
0301     {6, AR5K_RF_DB_2GHZ,        AR5K_RF5112_DB_2GHZ},
0302     {6, AR5K_RF_OB_5GHZ,        AR5K_RF5112_OB_5GHZ},
0303     {6, AR5K_RF_DB_5GHZ,        AR5K_RF5112_DB_5GHZ},
0304     {6, AR5K_RF_FIXED_BIAS_A,   AR5K_RF5112_FIXED_BIAS_A},
0305     {6, AR5K_RF_FIXED_BIAS_B,   AR5K_RF5112_FIXED_BIAS_B},
0306     {6, AR5K_RF_XPD_SEL,        AR5K_RF5112_XPD_SEL},
0307     {6, AR5K_RF_XPD_GAIN,       AR5K_RF5112_XPD_GAIN},
0308     {6, AR5K_RF_PWD_130,        AR5K_RF5112_PWD(130)},
0309     {6, AR5K_RF_PWD_131,        AR5K_RF5112_PWD(131)},
0310     {6, AR5K_RF_PWD_132,        AR5K_RF5112_PWD(132)},
0311     {6, AR5K_RF_PWD_136,        AR5K_RF5112_PWD(136)},
0312     {6, AR5K_RF_PWD_137,        AR5K_RF5112_PWD(137)},
0313     {6, AR5K_RF_PWD_138,        AR5K_RF5112_PWD(138)},
0314     {7, AR5K_RF_GAIN_I,     AR5K_RF5112X_GAIN_I},
0315     {7, AR5K_RF_MIXVGA_OVR,     AR5K_RF5112X_MIXVGA_OVR},
0316     {7, AR5K_RF_MIXGAIN_OVR,    AR5K_RF5112X_MIXGAIN_OVR},
0317     {7, AR5K_RF_MIXGAIN_STEP,   AR5K_RF5112X_MIXGAIN_STEP},
0318     {7, AR5K_RF_PD_DELAY_A,     AR5K_RF5112X_PD_DELAY_A},
0319     {7, AR5K_RF_PD_DELAY_B,     AR5K_RF5112X_PD_DELAY_B},
0320     {7, AR5K_RF_PD_DELAY_XR,    AR5K_RF5112X_PD_DELAY_XR},
0321     {7, AR5K_RF_PD_PERIOD_A,    AR5K_RF5112X_PD_PERIOD_A},
0322     {7, AR5K_RF_PD_PERIOD_B,    AR5K_RF5112X_PD_PERIOD_B},
0323     {7, AR5K_RF_PD_PERIOD_XR,   AR5K_RF5112X_PD_PERIOD_XR},
0324 };
0325 
0326 /* Default mode specific settings */
0327 static const struct ath5k_ini_rfbuffer rfb_5112[] = {
0328     /* BANK / C.R.     A/XR         B           G      */
0329     { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
0330     { 2, 0x98d0, { 0x03060408, 0x03060408, 0x03060408 } },
0331     { 3, 0x98dc, { 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
0332     { 6, 0x989c, { 0x00a00000, 0x00a00000, 0x00a00000 } },
0333     { 6, 0x989c, { 0x000a0000, 0x000a0000, 0x000a0000 } },
0334     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0335     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0336     { 6, 0x989c, { 0x00660000, 0x00660000, 0x00660000 } },
0337     { 6, 0x989c, { 0x00db0000, 0x00db0000, 0x00db0000 } },
0338     { 6, 0x989c, { 0x00f10000, 0x00f10000, 0x00f10000 } },
0339     { 6, 0x989c, { 0x00120000, 0x00120000, 0x00120000 } },
0340     { 6, 0x989c, { 0x00120000, 0x00120000, 0x00120000 } },
0341     { 6, 0x989c, { 0x00730000, 0x00730000, 0x00730000 } },
0342     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0343     { 6, 0x989c, { 0x000c0000, 0x000c0000, 0x000c0000 } },
0344     { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
0345     { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
0346     { 6, 0x989c, { 0x008b0000, 0x008b0000, 0x008b0000 } },
0347     { 6, 0x989c, { 0x00600000, 0x00600000, 0x00600000 } },
0348     { 6, 0x989c, { 0x000c0000, 0x000c0000, 0x000c0000 } },
0349     { 6, 0x989c, { 0x00840000, 0x00840000, 0x00840000 } },
0350     { 6, 0x989c, { 0x00640000, 0x00640000, 0x00640000 } },
0351     { 6, 0x989c, { 0x00200000, 0x00200000, 0x00200000 } },
0352     { 6, 0x989c, { 0x00240000, 0x00240000, 0x00240000 } },
0353     { 6, 0x989c, { 0x00250000, 0x00250000, 0x00250000 } },
0354     { 6, 0x989c, { 0x00110000, 0x00110000, 0x00110000 } },
0355     { 6, 0x989c, { 0x00110000, 0x00110000, 0x00110000 } },
0356     { 6, 0x989c, { 0x00510000, 0x00510000, 0x00510000 } },
0357     { 6, 0x989c, { 0x1c040000, 0x1c040000, 0x1c040000 } },
0358     { 6, 0x989c, { 0x000a0000, 0x000a0000, 0x000a0000 } },
0359     { 6, 0x989c, { 0x00a10000, 0x00a10000, 0x00a10000 } },
0360     { 6, 0x989c, { 0x00400000, 0x00400000, 0x00400000 } },
0361     { 6, 0x989c, { 0x03090000, 0x03090000, 0x03090000 } },
0362     { 6, 0x989c, { 0x06000000, 0x06000000, 0x06000000 } },
0363     { 6, 0x989c, { 0x000000b0, 0x000000a8, 0x000000a8 } },
0364     { 6, 0x989c, { 0x0000002e, 0x0000002e, 0x0000002e } },
0365     { 6, 0x989c, { 0x006c4a41, 0x006c4af1, 0x006c4a61 } },
0366     { 6, 0x989c, { 0x0050892a, 0x0050892b, 0x0050892b } },
0367     { 6, 0x989c, { 0x00842400, 0x00842400, 0x00842400 } },
0368     { 6, 0x989c, { 0x00c69200, 0x00c69200, 0x00c69200 } },
0369     { 6, 0x98d0, { 0x0002000c, 0x0002000c, 0x0002000c } },
0370     { 7, 0x989c, { 0x00000094, 0x00000094, 0x00000094 } },
0371     { 7, 0x989c, { 0x00000091, 0x00000091, 0x00000091 } },
0372     { 7, 0x989c, { 0x0000000a, 0x00000012, 0x00000012 } },
0373     { 7, 0x989c, { 0x00000080, 0x00000080, 0x00000080 } },
0374     { 7, 0x989c, { 0x000000c1, 0x000000c1, 0x000000c1 } },
0375     { 7, 0x989c, { 0x00000060, 0x00000060, 0x00000060 } },
0376     { 7, 0x989c, { 0x000000f0, 0x000000f0, 0x000000f0 } },
0377     { 7, 0x989c, { 0x00000022, 0x00000022, 0x00000022 } },
0378     { 7, 0x989c, { 0x00000092, 0x00000092, 0x00000092 } },
0379     { 7, 0x989c, { 0x000000d4, 0x000000d4, 0x000000d4 } },
0380     { 7, 0x989c, { 0x000014cc, 0x000014cc, 0x000014cc } },
0381     { 7, 0x989c, { 0x0000048c, 0x0000048c, 0x0000048c } },
0382     { 7, 0x98c4, { 0x00000003, 0x00000003, 0x00000003 } },
0383 };
0384 
0385 /* RFX112A (Derby 2) */
0386 
0387 /* BANK 6               len  pos col */
0388 #define AR5K_RF5112A_OB_2GHZ        { 3, 287, 0 }
0389 #define AR5K_RF5112A_DB_2GHZ        { 3, 290, 0 }
0390 
0391 #define AR5K_RF5112A_OB_5GHZ        { 3, 279, 0 }
0392 #define AR5K_RF5112A_DB_5GHZ        { 3, 282, 0 }
0393 
0394 #define AR5K_RF5112A_FIXED_BIAS_A   { 1, 278, 0 }
0395 #define AR5K_RF5112A_FIXED_BIAS_B   { 1, 277, 0 }
0396 
0397 #define AR5K_RF5112A_XPD_SEL        { 1, 302, 0 }
0398 #define AR5K_RF5112A_PDGAINLO       { 2, 270, 0 }
0399 #define AR5K_RF5112A_PDGAINHI       { 2, 257, 0 }
0400 
0401 /* Access to PWD registers */
0402 #define AR5K_RF5112A_PWD(_n)        { 1, (306 - _n), 3 }
0403 
0404 /* Voltage regulators */
0405 #define AR5K_RF5112A_HIGH_VC_CP     { 2, 90,  2 }
0406 #define AR5K_RF5112A_MID_VC_CP      { 2, 92,  2 }
0407 #define AR5K_RF5112A_LOW_VC_CP      { 2, 94,  2 }
0408 #define AR5K_RF5112A_PUSH_UP        { 1, 254,  2 }
0409 
0410 /* Power consumption */
0411 #define AR5K_RF5112A_PAD2GND        { 1, 281, 1 }
0412 #define AR5K_RF5112A_XB2_LVL        { 2, 1,   3 }
0413 #define AR5K_RF5112A_XB5_LVL        { 2, 3,   3 }
0414 
0415 static const struct ath5k_rf_reg rf_regs_5112a[] = {
0416     {2, AR5K_RF_TURBO,      AR5K_RF5112X_RF_TURBO},
0417     {6, AR5K_RF_OB_2GHZ,        AR5K_RF5112A_OB_2GHZ},
0418     {6, AR5K_RF_DB_2GHZ,        AR5K_RF5112A_DB_2GHZ},
0419     {6, AR5K_RF_OB_5GHZ,        AR5K_RF5112A_OB_5GHZ},
0420     {6, AR5K_RF_DB_5GHZ,        AR5K_RF5112A_DB_5GHZ},
0421     {6, AR5K_RF_FIXED_BIAS_A,   AR5K_RF5112A_FIXED_BIAS_A},
0422     {6, AR5K_RF_FIXED_BIAS_B,   AR5K_RF5112A_FIXED_BIAS_B},
0423     {6, AR5K_RF_XPD_SEL,        AR5K_RF5112A_XPD_SEL},
0424     {6, AR5K_RF_PD_GAIN_LO,     AR5K_RF5112A_PDGAINLO},
0425     {6, AR5K_RF_PD_GAIN_HI,     AR5K_RF5112A_PDGAINHI},
0426     {6, AR5K_RF_PWD_130,        AR5K_RF5112A_PWD(130)},
0427     {6, AR5K_RF_PWD_131,        AR5K_RF5112A_PWD(131)},
0428     {6, AR5K_RF_PWD_132,        AR5K_RF5112A_PWD(132)},
0429     {6, AR5K_RF_PWD_136,        AR5K_RF5112A_PWD(136)},
0430     {6, AR5K_RF_PWD_137,        AR5K_RF5112A_PWD(137)},
0431     {6, AR5K_RF_PWD_138,        AR5K_RF5112A_PWD(138)},
0432     {6, AR5K_RF_PWD_166,        AR5K_RF5112A_PWD(166)},
0433     {6, AR5K_RF_PWD_167,        AR5K_RF5112A_PWD(167)},
0434     {6, AR5K_RF_HIGH_VC_CP,     AR5K_RF5112A_HIGH_VC_CP},
0435     {6, AR5K_RF_MID_VC_CP,      AR5K_RF5112A_MID_VC_CP},
0436     {6, AR5K_RF_LOW_VC_CP,      AR5K_RF5112A_LOW_VC_CP},
0437     {6, AR5K_RF_PUSH_UP,        AR5K_RF5112A_PUSH_UP},
0438     {6, AR5K_RF_PAD2GND,        AR5K_RF5112A_PAD2GND},
0439     {6, AR5K_RF_XB2_LVL,        AR5K_RF5112A_XB2_LVL},
0440     {6, AR5K_RF_XB5_LVL,        AR5K_RF5112A_XB5_LVL},
0441     {7, AR5K_RF_GAIN_I,     AR5K_RF5112X_GAIN_I},
0442     {7, AR5K_RF_MIXVGA_OVR,     AR5K_RF5112X_MIXVGA_OVR},
0443     {7, AR5K_RF_MIXGAIN_OVR,    AR5K_RF5112X_MIXGAIN_OVR},
0444     {7, AR5K_RF_MIXGAIN_STEP,   AR5K_RF5112X_MIXGAIN_STEP},
0445     {7, AR5K_RF_PD_DELAY_A,     AR5K_RF5112X_PD_DELAY_A},
0446     {7, AR5K_RF_PD_DELAY_B,     AR5K_RF5112X_PD_DELAY_B},
0447     {7, AR5K_RF_PD_DELAY_XR,    AR5K_RF5112X_PD_DELAY_XR},
0448     {7, AR5K_RF_PD_PERIOD_A,    AR5K_RF5112X_PD_PERIOD_A},
0449     {7, AR5K_RF_PD_PERIOD_B,    AR5K_RF5112X_PD_PERIOD_B},
0450     {7, AR5K_RF_PD_PERIOD_XR,   AR5K_RF5112X_PD_PERIOD_XR},
0451 };
0452 
0453 /* Default mode specific settings */
0454 static const struct ath5k_ini_rfbuffer rfb_5112a[] = {
0455     /* BANK / C.R.     A/XR         B           G      */
0456     { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
0457     { 2, 0x98d0, { 0x03060408, 0x03060408, 0x03060408 } },
0458     { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
0459     { 6, 0x989c, { 0x0f000000, 0x0f000000, 0x0f000000 } },
0460     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0461     { 6, 0x989c, { 0x00800000, 0x00800000, 0x00800000 } },
0462     { 6, 0x989c, { 0x002a0000, 0x002a0000, 0x002a0000 } },
0463     { 6, 0x989c, { 0x00010000, 0x00010000, 0x00010000 } },
0464     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0465     { 6, 0x989c, { 0x00180000, 0x00180000, 0x00180000 } },
0466     { 6, 0x989c, { 0x00600000, 0x006e0000, 0x006e0000 } },
0467     { 6, 0x989c, { 0x00c70000, 0x00c70000, 0x00c70000 } },
0468     { 6, 0x989c, { 0x004b0000, 0x004b0000, 0x004b0000 } },
0469     { 6, 0x989c, { 0x04480000, 0x04480000, 0x04480000 } },
0470     { 6, 0x989c, { 0x004c0000, 0x004c0000, 0x004c0000 } },
0471     { 6, 0x989c, { 0x00e40000, 0x00e40000, 0x00e40000 } },
0472     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0473     { 6, 0x989c, { 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
0474     { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
0475     { 6, 0x989c, { 0x043f0000, 0x043f0000, 0x043f0000 } },
0476     { 6, 0x989c, { 0x000c0000, 0x000c0000, 0x000c0000 } },
0477     { 6, 0x989c, { 0x02190000, 0x02190000, 0x02190000 } },
0478     { 6, 0x989c, { 0x00240000, 0x00240000, 0x00240000 } },
0479     { 6, 0x989c, { 0x00b40000, 0x00b40000, 0x00b40000 } },
0480     { 6, 0x989c, { 0x00990000, 0x00990000, 0x00990000 } },
0481     { 6, 0x989c, { 0x00500000, 0x00500000, 0x00500000 } },
0482     { 6, 0x989c, { 0x002a0000, 0x002a0000, 0x002a0000 } },
0483     { 6, 0x989c, { 0x00120000, 0x00120000, 0x00120000 } },
0484     { 6, 0x989c, { 0xc0320000, 0xc0320000, 0xc0320000 } },
0485     { 6, 0x989c, { 0x01740000, 0x01740000, 0x01740000 } },
0486     { 6, 0x989c, { 0x00110000, 0x00110000, 0x00110000 } },
0487     { 6, 0x989c, { 0x86280000, 0x86280000, 0x86280000 } },
0488     { 6, 0x989c, { 0x31840000, 0x31840000, 0x31840000 } },
0489     { 6, 0x989c, { 0x00f20080, 0x00f20080, 0x00f20080 } },
0490     { 6, 0x989c, { 0x00270019, 0x00270019, 0x00270019 } },
0491     { 6, 0x989c, { 0x00000003, 0x00000003, 0x00000003 } },
0492     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0493     { 6, 0x989c, { 0x000000b2, 0x000000b2, 0x000000b2 } },
0494     { 6, 0x989c, { 0x00b02084, 0x00b02084, 0x00b02084 } },
0495     { 6, 0x989c, { 0x004125a4, 0x004125a4, 0x004125a4 } },
0496     { 6, 0x989c, { 0x00119220, 0x00119220, 0x00119220 } },
0497     { 6, 0x989c, { 0x001a4800, 0x001a4800, 0x001a4800 } },
0498     { 6, 0x98d8, { 0x000b0230, 0x000b0230, 0x000b0230 } },
0499     { 7, 0x989c, { 0x00000094, 0x00000094, 0x00000094 } },
0500     { 7, 0x989c, { 0x00000091, 0x00000091, 0x00000091 } },
0501     { 7, 0x989c, { 0x00000012, 0x00000012, 0x00000012 } },
0502     { 7, 0x989c, { 0x00000080, 0x00000080, 0x00000080 } },
0503     { 7, 0x989c, { 0x000000d9, 0x000000d9, 0x000000d9 } },
0504     { 7, 0x989c, { 0x00000060, 0x00000060, 0x00000060 } },
0505     { 7, 0x989c, { 0x000000f0, 0x000000f0, 0x000000f0 } },
0506     { 7, 0x989c, { 0x000000a2, 0x000000a2, 0x000000a2 } },
0507     { 7, 0x989c, { 0x00000052, 0x00000052, 0x00000052 } },
0508     { 7, 0x989c, { 0x000000d4, 0x000000d4, 0x000000d4 } },
0509     { 7, 0x989c, { 0x000014cc, 0x000014cc, 0x000014cc } },
0510     { 7, 0x989c, { 0x0000048c, 0x0000048c, 0x0000048c } },
0511     { 7, 0x98c4, { 0x00000003, 0x00000003, 0x00000003 } },
0512 };
0513 
0514 
0515 
0516 /******************\
0517 * RF2413 (Griffin) *
0518 \******************/
0519 
0520 /* BANK 2               len  pos col */
0521 #define AR5K_RF2413_RF_TURBO        { 1, 1,   2 }
0522 
0523 /* BANK 6               len  pos col */
0524 #define AR5K_RF2413_OB_2GHZ     { 3, 168, 0 }
0525 #define AR5K_RF2413_DB_2GHZ     { 3, 165, 0 }
0526 
0527 static const struct ath5k_rf_reg rf_regs_2413[] = {
0528     {2, AR5K_RF_TURBO,      AR5K_RF2413_RF_TURBO},
0529     {6, AR5K_RF_OB_2GHZ,        AR5K_RF2413_OB_2GHZ},
0530     {6, AR5K_RF_DB_2GHZ,        AR5K_RF2413_DB_2GHZ},
0531 };
0532 
0533 /* Default mode specific settings
0534  * XXX: a/aTurbo ???
0535  */
0536 static const struct ath5k_ini_rfbuffer rfb_2413[] = {
0537     /* BANK / C.R.     A/XR         B           G      */
0538     { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
0539     { 2, 0x98d0, { 0x02001408, 0x02001408, 0x02001408 } },
0540     { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
0541     { 6, 0x989c, { 0xf0000000, 0xf0000000, 0xf0000000 } },
0542     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0543     { 6, 0x989c, { 0x03000000, 0x03000000, 0x03000000 } },
0544     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0545     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0546     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0547     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0548     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0549     { 6, 0x989c, { 0x40400000, 0x40400000, 0x40400000 } },
0550     { 6, 0x989c, { 0x65050000, 0x65050000, 0x65050000 } },
0551     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0552     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0553     { 6, 0x989c, { 0x00420000, 0x00420000, 0x00420000 } },
0554     { 6, 0x989c, { 0x00b50000, 0x00b50000, 0x00b50000 } },
0555     { 6, 0x989c, { 0x00030000, 0x00030000, 0x00030000 } },
0556     { 6, 0x989c, { 0x00f70000, 0x00f70000, 0x00f70000 } },
0557     { 6, 0x989c, { 0x009d0000, 0x009d0000, 0x009d0000 } },
0558     { 6, 0x989c, { 0x00220000, 0x00220000, 0x00220000 } },
0559     { 6, 0x989c, { 0x04220000, 0x04220000, 0x04220000 } },
0560     { 6, 0x989c, { 0x00230018, 0x00230018, 0x00230018 } },
0561     { 6, 0x989c, { 0x00280000, 0x00280060, 0x00280060 } },
0562     { 6, 0x989c, { 0x005000c0, 0x005000c3, 0x005000c3 } },
0563     { 6, 0x989c, { 0x0004007f, 0x0004007f, 0x0004007f } },
0564     { 6, 0x989c, { 0x00000458, 0x00000458, 0x00000458 } },
0565     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0566     { 6, 0x989c, { 0x0000c000, 0x0000c000, 0x0000c000 } },
0567     { 6, 0x98d8, { 0x00400230, 0x00400230, 0x00400230 } },
0568     { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
0569     { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
0570     { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
0571 };
0572 
0573 
0574 
0575 /***************************\
0576 * RF2315/RF2316 (Cobra SoC) *
0577 \***************************/
0578 
0579 /* BANK 2               len  pos col */
0580 #define AR5K_RF2316_RF_TURBO        { 1, 1,   2 }
0581 
0582 /* BANK 6               len  pos col */
0583 #define AR5K_RF2316_OB_2GHZ     { 3, 178, 0 }
0584 #define AR5K_RF2316_DB_2GHZ     { 3, 175, 0 }
0585 
0586 static const struct ath5k_rf_reg rf_regs_2316[] = {
0587     {2, AR5K_RF_TURBO,      AR5K_RF2316_RF_TURBO},
0588     {6, AR5K_RF_OB_2GHZ,        AR5K_RF2316_OB_2GHZ},
0589     {6, AR5K_RF_DB_2GHZ,        AR5K_RF2316_DB_2GHZ},
0590 };
0591 
0592 /* Default mode specific settings */
0593 static const struct ath5k_ini_rfbuffer rfb_2316[] = {
0594     /* BANK / C.R.     A/XR         B           G      */
0595     { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
0596     { 2, 0x98d0, { 0x02001408, 0x02001408, 0x02001408 } },
0597     { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
0598     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0599     { 6, 0x989c, { 0xc0000000, 0xc0000000, 0xc0000000 } },
0600     { 6, 0x989c, { 0x0f000000, 0x0f000000, 0x0f000000 } },
0601     { 6, 0x989c, { 0x02000000, 0x02000000, 0x02000000 } },
0602     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0603     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0604     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0605     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0606     { 6, 0x989c, { 0xf8000000, 0xf8000000, 0xf8000000 } },
0607     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0608     { 6, 0x989c, { 0x95150000, 0x95150000, 0x95150000 } },
0609     { 6, 0x989c, { 0xc1000000, 0xc1000000, 0xc1000000 } },
0610     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0611     { 6, 0x989c, { 0x00080000, 0x00080000, 0x00080000 } },
0612     { 6, 0x989c, { 0x00d50000, 0x00d50000, 0x00d50000 } },
0613     { 6, 0x989c, { 0x000e0000, 0x000e0000, 0x000e0000 } },
0614     { 6, 0x989c, { 0x00dc0000, 0x00dc0000, 0x00dc0000 } },
0615     { 6, 0x989c, { 0x00770000, 0x00770000, 0x00770000 } },
0616     { 6, 0x989c, { 0x008a0000, 0x008a0000, 0x008a0000 } },
0617     { 6, 0x989c, { 0x10880000, 0x10880000, 0x10880000 } },
0618     { 6, 0x989c, { 0x008c0060, 0x008c0060, 0x008c0060 } },
0619     { 6, 0x989c, { 0x00a00000, 0x00a00080, 0x00a00080 } },
0620     { 6, 0x989c, { 0x00400000, 0x0040000d, 0x0040000d } },
0621     { 6, 0x989c, { 0x00110400, 0x00110400, 0x00110400 } },
0622     { 6, 0x989c, { 0x00000060, 0x00000060, 0x00000060 } },
0623     { 6, 0x989c, { 0x00000001, 0x00000001, 0x00000001 } },
0624     { 6, 0x989c, { 0x00000b00, 0x00000b00, 0x00000b00 } },
0625     { 6, 0x989c, { 0x00000be8, 0x00000be8, 0x00000be8 } },
0626     { 6, 0x98c0, { 0x00010000, 0x00010000, 0x00010000 } },
0627     { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
0628     { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
0629     { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
0630 };
0631 
0632 
0633 
0634 /******************************\
0635 * RF5413/RF5424 (Eagle/Condor) *
0636 \******************************/
0637 
0638 /* BANK 6               len  pos col */
0639 #define AR5K_RF5413_OB_2GHZ     { 3, 241, 0 }
0640 #define AR5K_RF5413_DB_2GHZ     { 3, 238, 0 }
0641 
0642 #define AR5K_RF5413_OB_5GHZ     { 3, 247, 0 }
0643 #define AR5K_RF5413_DB_5GHZ     { 3, 244, 0 }
0644 
0645 #define AR5K_RF5413_PWD_ICLOBUF2G   { 3, 131, 3 }
0646 #define AR5K_RF5413_DERBY_CHAN_SEL_MODE { 1, 291, 2 }
0647 
0648 static const struct ath5k_rf_reg rf_regs_5413[] = {
0649     {6, AR5K_RF_OB_2GHZ,         AR5K_RF5413_OB_2GHZ},
0650     {6, AR5K_RF_DB_2GHZ,         AR5K_RF5413_DB_2GHZ},
0651     {6, AR5K_RF_OB_5GHZ,         AR5K_RF5413_OB_5GHZ},
0652     {6, AR5K_RF_DB_5GHZ,         AR5K_RF5413_DB_5GHZ},
0653     {6, AR5K_RF_PWD_ICLOBUF_2G,  AR5K_RF5413_PWD_ICLOBUF2G},
0654     {6, AR5K_RF_DERBY_CHAN_SEL_MODE, AR5K_RF5413_DERBY_CHAN_SEL_MODE},
0655 };
0656 
0657 /* Default mode specific settings */
0658 static const struct ath5k_ini_rfbuffer rfb_5413[] = {
0659     /* BANK / C.R.     A/XR         B           G      */
0660     { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
0661     { 2, 0x98d0, { 0x00000008, 0x00000008, 0x00000008 } },
0662     { 3, 0x98dc, { 0x00a000c0, 0x00e000c0, 0x00e000c0 } },
0663     { 6, 0x989c, { 0x33000000, 0x33000000, 0x33000000 } },
0664     { 6, 0x989c, { 0x01000000, 0x01000000, 0x01000000 } },
0665     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0666     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0667     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0668     { 6, 0x989c, { 0x1f000000, 0x1f000000, 0x1f000000 } },
0669     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0670     { 6, 0x989c, { 0x00b80000, 0x00b80000, 0x00b80000 } },
0671     { 6, 0x989c, { 0x00b70000, 0x00b70000, 0x00b70000 } },
0672     { 6, 0x989c, { 0x00840000, 0x00840000, 0x00840000 } },
0673     { 6, 0x989c, { 0x00980000, 0x00980000, 0x00980000 } },
0674     { 6, 0x989c, { 0x00c00000, 0x00c00000, 0x00c00000 } },
0675     { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
0676     { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
0677     { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
0678     { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
0679     { 6, 0x989c, { 0x00d70000, 0x00d70000, 0x00d70000 } },
0680     { 6, 0x989c, { 0x00610000, 0x00610000, 0x00610000 } },
0681     { 6, 0x989c, { 0x00fe0000, 0x00fe0000, 0x00fe0000 } },
0682     { 6, 0x989c, { 0x00de0000, 0x00de0000, 0x00de0000 } },
0683     { 6, 0x989c, { 0x007f0000, 0x007f0000, 0x007f0000 } },
0684     { 6, 0x989c, { 0x043d0000, 0x043d0000, 0x043d0000 } },
0685     { 6, 0x989c, { 0x00770000, 0x00770000, 0x00770000 } },
0686     { 6, 0x989c, { 0x00440000, 0x00440000, 0x00440000 } },
0687     { 6, 0x989c, { 0x00980000, 0x00980000, 0x00980000 } },
0688     { 6, 0x989c, { 0x00100080, 0x00100080, 0x00100080 } },
0689     { 6, 0x989c, { 0x0005c034, 0x0005c034, 0x0005c034 } },
0690     { 6, 0x989c, { 0x003100f0, 0x003100f0, 0x003100f0 } },
0691     { 6, 0x989c, { 0x000c011f, 0x000c011f, 0x000c011f } },
0692     { 6, 0x989c, { 0x00510040, 0x00510040, 0x00510040 } },
0693     { 6, 0x989c, { 0x005000da, 0x005000da, 0x005000da } },
0694     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0695     { 6, 0x989c, { 0x00004044, 0x00004044, 0x00004044 } },
0696     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0697     { 6, 0x989c, { 0x000060c0, 0x000060c0, 0x000060c0 } },
0698     { 6, 0x989c, { 0x00002c00, 0x00003600, 0x00003600 } },
0699     { 6, 0x98c8, { 0x00000403, 0x00040403, 0x00040403 } },
0700     { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
0701     { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
0702     { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
0703 };
0704 
0705 
0706 
0707 /***************************\
0708 * RF2425/RF2417 (Swan/Nala) *
0709 * AR2317 (Spider SoC)       *
0710 \***************************/
0711 
0712 /* BANK 2               len  pos col */
0713 #define AR5K_RF2425_RF_TURBO        { 1, 1,   2 }
0714 
0715 /* BANK 6               len  pos col */
0716 #define AR5K_RF2425_OB_2GHZ     { 3, 193, 0 }
0717 #define AR5K_RF2425_DB_2GHZ     { 3, 190, 0 }
0718 
0719 static const struct ath5k_rf_reg rf_regs_2425[] = {
0720     {2, AR5K_RF_TURBO,      AR5K_RF2425_RF_TURBO},
0721     {6, AR5K_RF_OB_2GHZ,        AR5K_RF2425_OB_2GHZ},
0722     {6, AR5K_RF_DB_2GHZ,        AR5K_RF2425_DB_2GHZ},
0723 };
0724 
0725 /* Default mode specific settings
0726  */
0727 static const struct ath5k_ini_rfbuffer rfb_2425[] = {
0728     /* BANK / C.R.     A/XR         B           G      */
0729     { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
0730     { 2, 0x98d0, { 0x02001408, 0x02001408, 0x02001408 } },
0731     { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
0732     { 6, 0x989c, { 0x10000000, 0x10000000, 0x10000000 } },
0733     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0734     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0735     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0736     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0737     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0738     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0739     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0740     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0741     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0742     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0743     { 6, 0x989c, { 0x002a0000, 0x002a0000, 0x002a0000 } },
0744     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0745     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0746     { 6, 0x989c, { 0x00100000, 0x00100000, 0x00100000 } },
0747     { 6, 0x989c, { 0x00020000, 0x00020000, 0x00020000 } },
0748     { 6, 0x989c, { 0x00730000, 0x00730000, 0x00730000 } },
0749     { 6, 0x989c, { 0x00f80000, 0x00f80000, 0x00f80000 } },
0750     { 6, 0x989c, { 0x00e70000, 0x00e70000, 0x00e70000 } },
0751     { 6, 0x989c, { 0x00140000, 0x00140000, 0x00140000 } },
0752     { 6, 0x989c, { 0x00910040, 0x00910040, 0x00910040 } },
0753     { 6, 0x989c, { 0x0007001a, 0x0007001a, 0x0007001a } },
0754     { 6, 0x989c, { 0x00410000, 0x00410000, 0x00410000 } },
0755     { 6, 0x989c, { 0x00810000, 0x00810060, 0x00810060 } },
0756     { 6, 0x989c, { 0x00020800, 0x00020803, 0x00020803 } },
0757     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0758     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0759     { 6, 0x989c, { 0x00001660, 0x00001660, 0x00001660 } },
0760     { 6, 0x989c, { 0x00001688, 0x00001688, 0x00001688 } },
0761     { 6, 0x98c4, { 0x00000001, 0x00000001, 0x00000001 } },
0762     { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
0763     { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
0764     { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
0765 };
0766 
0767 /*
0768  * TODO: Handle the few differences with swan during
0769  * bank modification and get rid of this
0770  */
0771 static const struct ath5k_ini_rfbuffer rfb_2317[] = {
0772     /* BANK / C.R.     A/XR         B           G      */
0773     { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
0774     { 2, 0x98d0, { 0x02001408, 0x02001408, 0x02001408 } },
0775     { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
0776     { 6, 0x989c, { 0x10000000, 0x10000000, 0x10000000 } },
0777     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0778     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0779     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0780     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0781     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0782     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0783     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0784     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0785     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0786     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0787     { 6, 0x989c, { 0x002a0000, 0x002a0000, 0x002a0000 } },
0788     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0789     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0790     { 6, 0x989c, { 0x00100000, 0x00100000, 0x00100000 } },
0791     { 6, 0x989c, { 0x00020000, 0x00020000, 0x00020000 } },
0792     { 6, 0x989c, { 0x00730000, 0x00730000, 0x00730000 } },
0793     { 6, 0x989c, { 0x00f80000, 0x00f80000, 0x00f80000 } },
0794     { 6, 0x989c, { 0x00e70000, 0x00e70000, 0x00e70000 } },
0795     { 6, 0x989c, { 0x00140100, 0x00140100, 0x00140100 } },
0796     { 6, 0x989c, { 0x00910040, 0x00910040, 0x00910040 } },
0797     { 6, 0x989c, { 0x0007001a, 0x0007001a, 0x0007001a } },
0798     { 6, 0x989c, { 0x00410000, 0x00410000, 0x00410000 } },
0799     { 6, 0x989c, { 0x00810000, 0x00810060, 0x00810060 } },
0800     { 6, 0x989c, { 0x00020800, 0x00020803, 0x00020803 } },
0801     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0802     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0803     { 6, 0x989c, { 0x00001660, 0x00001660, 0x00001660 } },
0804     { 6, 0x989c, { 0x00009688, 0x00009688, 0x00009688 } },
0805     { 6, 0x98c4, { 0x00000001, 0x00000001, 0x00000001 } },
0806     { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
0807     { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
0808     { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
0809 };
0810 
0811 /*
0812  * TODO: Handle the few differences with swan during
0813  * bank modification and get rid of this
0814  */
0815 static const struct ath5k_ini_rfbuffer rfb_2417[] = {
0816     /* BANK / C.R.     A/XR         B           G      */
0817     { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
0818     { 2, 0x98d0, { 0x02001408, 0x02001408, 0x02001408 } },
0819     { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
0820     { 6, 0x989c, { 0x10000000, 0x10000000, 0x10000000 } },
0821     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0822     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0823     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0824     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0825     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0826     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0827     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0828     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0829     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0830     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0831     { 6, 0x989c, { 0x002a0000, 0x002a0000, 0x002a0000 } },
0832     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0833     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0834     { 6, 0x989c, { 0x00100000, 0x00100000, 0x00100000 } },
0835     { 6, 0x989c, { 0x00020000, 0x00020000, 0x00020000 } },
0836     { 6, 0x989c, { 0x00730000, 0x00730000, 0x00730000 } },
0837     { 6, 0x989c, { 0x00f80000, 0x00f80000, 0x00f80000 } },
0838     { 6, 0x989c, { 0x00e70000, 0x80e70000, 0x80e70000 } },
0839     { 6, 0x989c, { 0x00140000, 0x00140000, 0x00140000 } },
0840     { 6, 0x989c, { 0x00910040, 0x00910040, 0x00910040 } },
0841     { 6, 0x989c, { 0x0007001a, 0x0207001a, 0x0207001a } },
0842     { 6, 0x989c, { 0x00410000, 0x00410000, 0x00410000 } },
0843     { 6, 0x989c, { 0x00810000, 0x00810060, 0x00810060 } },
0844     { 6, 0x989c, { 0x00020800, 0x00020803, 0x00020803 } },
0845     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0846     { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
0847     { 6, 0x989c, { 0x00001660, 0x00001660, 0x00001660 } },
0848     { 6, 0x989c, { 0x00001688, 0x00001688, 0x00001688 } },
0849     { 6, 0x98c4, { 0x00000001, 0x00000001, 0x00000001 } },
0850     { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
0851     { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
0852     { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
0853 };
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