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0001 /*
0002  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
0003  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
0004  * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
0005  * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
0006  * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
0007  *
0008  * Permission to use, copy, modify, and distribute this software for any
0009  * purpose with or without fee is hereby granted, provided that the above
0010  * copyright notice and this permission notice appear in all copies.
0011  *
0012  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0013  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0014  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0015  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0016  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0017  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0018  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0019  *
0020  */
0021 
0022 /****************************\
0023   Reset function and helpers
0024 \****************************/
0025 
0026 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0027 
0028 #include <asm/unaligned.h>
0029 
0030 #include <linux/pci.h>      /* To determine if a card is pci-e */
0031 #include <linux/log2.h>
0032 #include <linux/platform_device.h>
0033 #include "ath5k.h"
0034 #include "reg.h"
0035 #include "debug.h"
0036 
0037 
0038 /**
0039  * DOC: Reset function and helpers
0040  *
0041  * Here we implement the main reset routine, used to bring the card
0042  * to a working state and ready to receive. We also handle routines
0043  * that don't fit on other places such as clock, sleep and power control
0044  */
0045 
0046 
0047 /******************\
0048 * Helper functions *
0049 \******************/
0050 
0051 /**
0052  * ath5k_hw_register_timeout() - Poll a register for a flag/field change
0053  * @ah: The &struct ath5k_hw
0054  * @reg: The register to read
0055  * @flag: The flag/field to check on the register
0056  * @val: The field value we expect (if we check a field)
0057  * @is_set: Instead of checking if the flag got cleared, check if it got set
0058  *
0059  * Some registers contain flags that indicate that an operation is
0060  * running. We use this function to poll these registers and check
0061  * if these flags get cleared. We also use it to poll a register
0062  * field (containing multiple flags) until it gets a specific value.
0063  *
0064  * Returns -EAGAIN if we exceeded AR5K_TUNE_REGISTER_TIMEOUT * 15us or 0
0065  */
0066 int
0067 ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
0068                   bool is_set)
0069 {
0070     int i;
0071     u32 data;
0072 
0073     for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
0074         data = ath5k_hw_reg_read(ah, reg);
0075         if (is_set && (data & flag))
0076             break;
0077         else if ((data & flag) == val)
0078             break;
0079         udelay(15);
0080     }
0081 
0082     return (i <= 0) ? -EAGAIN : 0;
0083 }
0084 
0085 
0086 /*************************\
0087 * Clock related functions *
0088 \*************************/
0089 
0090 /**
0091  * ath5k_hw_htoclock() - Translate usec to hw clock units
0092  * @ah: The &struct ath5k_hw
0093  * @usec: value in microseconds
0094  *
0095  * Translate usecs to hw clock units based on the current
0096  * hw clock rate.
0097  *
0098  * Returns number of clock units
0099  */
0100 unsigned int
0101 ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
0102 {
0103     struct ath_common *common = ath5k_hw_common(ah);
0104     return usec * common->clockrate;
0105 }
0106 
0107 /**
0108  * ath5k_hw_clocktoh() - Translate hw clock units to usec
0109  * @ah: The &struct ath5k_hw
0110  * @clock: value in hw clock units
0111  *
0112  * Translate hw clock units to usecs based on the current
0113  * hw clock rate.
0114  *
0115  * Returns number of usecs
0116  */
0117 unsigned int
0118 ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
0119 {
0120     struct ath_common *common = ath5k_hw_common(ah);
0121     return clock / common->clockrate;
0122 }
0123 
0124 /**
0125  * ath5k_hw_init_core_clock() - Initialize core clock
0126  * @ah: The &struct ath5k_hw
0127  *
0128  * Initialize core clock parameters (usec, usec32, latencies etc),
0129  * based on current bwmode and chipset properties.
0130  */
0131 static void
0132 ath5k_hw_init_core_clock(struct ath5k_hw *ah)
0133 {
0134     struct ieee80211_channel *channel = ah->ah_current_channel;
0135     struct ath_common *common = ath5k_hw_common(ah);
0136     u32 usec_reg, txlat, rxlat, usec, clock, sclock, txf2txs;
0137 
0138     /*
0139      * Set core clock frequency
0140      */
0141     switch (channel->hw_value) {
0142     case AR5K_MODE_11A:
0143         clock = 40;
0144         break;
0145     case AR5K_MODE_11B:
0146         clock = 22;
0147         break;
0148     case AR5K_MODE_11G:
0149     default:
0150         clock = 44;
0151         break;
0152     }
0153 
0154     /* Use clock multiplier for non-default
0155      * bwmode */
0156     switch (ah->ah_bwmode) {
0157     case AR5K_BWMODE_40MHZ:
0158         clock *= 2;
0159         break;
0160     case AR5K_BWMODE_10MHZ:
0161         clock /= 2;
0162         break;
0163     case AR5K_BWMODE_5MHZ:
0164         clock /= 4;
0165         break;
0166     default:
0167         break;
0168     }
0169 
0170     common->clockrate = clock;
0171 
0172     /*
0173      * Set USEC parameters
0174      */
0175     /* Set USEC counter on PCU*/
0176     usec = clock - 1;
0177     usec = AR5K_REG_SM(usec, AR5K_USEC_1);
0178 
0179     /* Set usec duration on DCU */
0180     if (ah->ah_version != AR5K_AR5210)
0181         AR5K_REG_WRITE_BITS(ah, AR5K_DCU_GBL_IFS_MISC,
0182                     AR5K_DCU_GBL_IFS_MISC_USEC_DUR,
0183                     clock);
0184 
0185     /* Set 32MHz USEC counter */
0186     if ((ah->ah_radio == AR5K_RF5112) ||
0187         (ah->ah_radio == AR5K_RF2413) ||
0188         (ah->ah_radio == AR5K_RF5413) ||
0189         (ah->ah_radio == AR5K_RF2316) ||
0190         (ah->ah_radio == AR5K_RF2317))
0191         /* Remain on 40MHz clock ? */
0192         sclock = 40 - 1;
0193     else
0194         sclock = 32 - 1;
0195     sclock = AR5K_REG_SM(sclock, AR5K_USEC_32);
0196 
0197     /*
0198      * Set tx/rx latencies
0199      */
0200     usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
0201     txlat = AR5K_REG_MS(usec_reg, AR5K_USEC_TX_LATENCY_5211);
0202     rxlat = AR5K_REG_MS(usec_reg, AR5K_USEC_RX_LATENCY_5211);
0203 
0204     /*
0205      * Set default Tx frame to Tx data start delay
0206      */
0207     txf2txs = AR5K_INIT_TXF2TXD_START_DEFAULT;
0208 
0209     /*
0210      * 5210 initvals don't include usec settings
0211      * so we need to use magic values here for
0212      * tx/rx latencies
0213      */
0214     if (ah->ah_version == AR5K_AR5210) {
0215         /* same for turbo */
0216         txlat = AR5K_INIT_TX_LATENCY_5210;
0217         rxlat = AR5K_INIT_RX_LATENCY_5210;
0218     }
0219 
0220     if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
0221         /* 5311 has different tx/rx latency masks
0222          * from 5211, since we deal 5311 the same
0223          * as 5211 when setting initvals, shift
0224          * values here to their proper locations
0225          *
0226          * Note: Initvals indicate tx/rx/ latencies
0227          * are the same for turbo mode */
0228         txlat = AR5K_REG_SM(txlat, AR5K_USEC_TX_LATENCY_5210);
0229         rxlat = AR5K_REG_SM(rxlat, AR5K_USEC_RX_LATENCY_5210);
0230     } else
0231     switch (ah->ah_bwmode) {
0232     case AR5K_BWMODE_10MHZ:
0233         txlat = AR5K_REG_SM(txlat * 2,
0234                 AR5K_USEC_TX_LATENCY_5211);
0235         rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
0236                 AR5K_USEC_RX_LATENCY_5211);
0237         txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_10MHZ;
0238         break;
0239     case AR5K_BWMODE_5MHZ:
0240         txlat = AR5K_REG_SM(txlat * 4,
0241                 AR5K_USEC_TX_LATENCY_5211);
0242         rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
0243                 AR5K_USEC_RX_LATENCY_5211);
0244         txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_5MHZ;
0245         break;
0246     case AR5K_BWMODE_40MHZ:
0247         txlat = AR5K_INIT_TX_LAT_MIN;
0248         rxlat = AR5K_REG_SM(rxlat / 2,
0249                 AR5K_USEC_RX_LATENCY_5211);
0250         txf2txs = AR5K_INIT_TXF2TXD_START_DEFAULT;
0251         break;
0252     default:
0253         break;
0254     }
0255 
0256     usec_reg = (usec | sclock | txlat | rxlat);
0257     ath5k_hw_reg_write(ah, usec_reg, AR5K_USEC);
0258 
0259     /* On 5112 set tx frame to tx data start delay */
0260     if (ah->ah_radio == AR5K_RF5112) {
0261         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL2,
0262                     AR5K_PHY_RF_CTL2_TXF2TXD_START,
0263                     txf2txs);
0264     }
0265 }
0266 
0267 /**
0268  * ath5k_hw_set_sleep_clock() - Setup sleep clock operation
0269  * @ah: The &struct ath5k_hw
0270  * @enable: Enable sleep clock operation (false to disable)
0271  *
0272  * If there is an external 32KHz crystal available, use it
0273  * as ref. clock instead of 32/40MHz clock and baseband clocks
0274  * to save power during sleep or restore normal 32/40MHz
0275  * operation.
0276  *
0277  * NOTE: When operating on 32KHz certain PHY registers (27 - 31,
0278  * 123 - 127) require delay on access.
0279  */
0280 static void
0281 ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
0282 {
0283     struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
0284     u32 scal, spending, sclock;
0285 
0286     /* Only set 32KHz settings if we have an external
0287      * 32KHz crystal present */
0288     if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
0289     AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&
0290     enable) {
0291 
0292         /* 1 usec/cycle */
0293         AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1);
0294         /* Set up tsf increment on each cycle */
0295         AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61);
0296 
0297         /* Set baseband sleep control registers
0298          * and sleep control rate */
0299         ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
0300 
0301         if ((ah->ah_radio == AR5K_RF5112) ||
0302         (ah->ah_radio == AR5K_RF5413) ||
0303         (ah->ah_radio == AR5K_RF2316) ||
0304         (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
0305             spending = 0x14;
0306         else
0307             spending = 0x18;
0308         ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
0309 
0310         if ((ah->ah_radio == AR5K_RF5112) ||
0311         (ah->ah_radio == AR5K_RF5413) ||
0312         (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
0313             ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT);
0314             ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL);
0315             ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK);
0316             ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY);
0317             AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
0318                 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02);
0319         } else {
0320             ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT);
0321             ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL);
0322             ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK);
0323             ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY);
0324             AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
0325                 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03);
0326         }
0327 
0328         /* Enable sleep clock operation */
0329         AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,
0330                 AR5K_PCICFG_SLEEP_CLOCK_EN);
0331 
0332     } else {
0333 
0334         /* Disable sleep clock operation and
0335          * restore default parameters */
0336         AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
0337                 AR5K_PCICFG_SLEEP_CLOCK_EN);
0338 
0339         AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
0340                 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0);
0341 
0342         /* Set DAC/ADC delays */
0343         ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
0344         ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
0345 
0346         if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
0347             scal = AR5K_PHY_SCAL_32MHZ_2417;
0348         else if (ee->ee_is_hb63)
0349             scal = AR5K_PHY_SCAL_32MHZ_HB63;
0350         else
0351             scal = AR5K_PHY_SCAL_32MHZ;
0352         ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
0353 
0354         ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
0355         ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
0356 
0357         if ((ah->ah_radio == AR5K_RF5112) ||
0358         (ah->ah_radio == AR5K_RF5413) ||
0359         (ah->ah_radio == AR5K_RF2316) ||
0360         (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
0361             spending = 0x14;
0362         else
0363             spending = 0x18;
0364         ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
0365 
0366         /* Set up tsf increment on each cycle */
0367         AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
0368 
0369         if ((ah->ah_radio == AR5K_RF5112) ||
0370             (ah->ah_radio == AR5K_RF5413) ||
0371             (ah->ah_radio == AR5K_RF2316) ||
0372             (ah->ah_radio == AR5K_RF2317))
0373             sclock = 40 - 1;
0374         else
0375             sclock = 32 - 1;
0376         AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, sclock);
0377     }
0378 }
0379 
0380 
0381 /*********************\
0382 * Reset/Sleep control *
0383 \*********************/
0384 
0385 /**
0386  * ath5k_hw_nic_reset() - Reset the various chipset units
0387  * @ah: The &struct ath5k_hw
0388  * @val: Mask to indicate what units to reset
0389  *
0390  * To reset the various chipset units we need to write
0391  * the mask to AR5K_RESET_CTL and poll the register until
0392  * all flags are cleared.
0393  *
0394  * Returns 0 if we are O.K. or -EAGAIN (from athk5_hw_register_timeout)
0395  */
0396 static int
0397 ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
0398 {
0399     int ret;
0400     u32 mask = val ? val : ~0U;
0401 
0402     /* Read-and-clear RX Descriptor Pointer*/
0403     ath5k_hw_reg_read(ah, AR5K_RXDP);
0404 
0405     /*
0406      * Reset the device and wait until success
0407      */
0408     ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
0409 
0410     /* Wait at least 128 PCI clocks */
0411     usleep_range(15, 20);
0412 
0413     if (ah->ah_version == AR5K_AR5210) {
0414         val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
0415             | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
0416         mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
0417             | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
0418     } else {
0419         val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
0420         mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
0421     }
0422 
0423     ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);
0424 
0425     /*
0426      * Reset configuration register (for hw byte-swap). Note that this
0427      * is only set for big endian. We do the necessary magic in
0428      * AR5K_INIT_CFG.
0429      */
0430     if ((val & AR5K_RESET_CTL_PCU) == 0)
0431         ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
0432 
0433     return ret;
0434 }
0435 
0436 /**
0437  * ath5k_hw_wisoc_reset() -  Reset AHB chipset
0438  * @ah: The &struct ath5k_hw
0439  * @flags: Mask to indicate what units to reset
0440  *
0441  * Same as ath5k_hw_nic_reset but for AHB based devices
0442  *
0443  * Returns 0 if we are O.K. or -EAGAIN (from athk5_hw_register_timeout)
0444  */
0445 static int
0446 ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags)
0447 {
0448     u32 mask = flags ? flags : ~0U;
0449     u32 __iomem *reg;
0450     u32 regval;
0451     u32 val = 0;
0452 
0453     /* ah->ah_mac_srev is not available at this point yet */
0454     if (ah->devid >= AR5K_SREV_AR2315_R6) {
0455         reg = (u32 __iomem *) AR5K_AR2315_RESET;
0456         if (mask & AR5K_RESET_CTL_PCU)
0457             val |= AR5K_AR2315_RESET_WMAC;
0458         if (mask & AR5K_RESET_CTL_BASEBAND)
0459             val |= AR5K_AR2315_RESET_BB_WARM;
0460     } else {
0461         reg = (u32 __iomem *) AR5K_AR5312_RESET;
0462         if (to_platform_device(ah->dev)->id == 0) {
0463             if (mask & AR5K_RESET_CTL_PCU)
0464                 val |= AR5K_AR5312_RESET_WMAC0;
0465             if (mask & AR5K_RESET_CTL_BASEBAND)
0466                 val |= AR5K_AR5312_RESET_BB0_COLD |
0467                        AR5K_AR5312_RESET_BB0_WARM;
0468         } else {
0469             if (mask & AR5K_RESET_CTL_PCU)
0470                 val |= AR5K_AR5312_RESET_WMAC1;
0471             if (mask & AR5K_RESET_CTL_BASEBAND)
0472                 val |= AR5K_AR5312_RESET_BB1_COLD |
0473                        AR5K_AR5312_RESET_BB1_WARM;
0474         }
0475     }
0476 
0477     /* Put BB/MAC into reset */
0478     regval = ioread32(reg);
0479     iowrite32(regval | val, reg);
0480     regval = ioread32(reg);
0481     udelay(100);    /* NB: should be atomic */
0482 
0483     /* Bring BB/MAC out of reset */
0484     iowrite32(regval & ~val, reg);
0485     regval = ioread32(reg);
0486 
0487     /*
0488      * Reset configuration register (for hw byte-swap). Note that this
0489      * is only set for big endian. We do the necessary magic in
0490      * AR5K_INIT_CFG.
0491      */
0492     if ((flags & AR5K_RESET_CTL_PCU) == 0)
0493         ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
0494 
0495     return 0;
0496 }
0497 
0498 /**
0499  * ath5k_hw_set_power_mode() - Set power mode
0500  * @ah: The &struct ath5k_hw
0501  * @mode: One of enum ath5k_power_mode
0502  * @set_chip: Set to true to write sleep control register
0503  * @sleep_duration: How much time the device is allowed to sleep
0504  * when sleep logic is enabled (in 128 microsecond increments).
0505  *
0506  * This function is used to configure sleep policy and allowed
0507  * sleep modes. For more information check out the sleep control
0508  * register on reg.h and STA_ID1.
0509  *
0510  * Returns 0 on success, -EIO if chip didn't wake up or -EINVAL if an invalid
0511  * mode is requested.
0512  */
0513 static int
0514 ath5k_hw_set_power_mode(struct ath5k_hw *ah, enum ath5k_power_mode mode,
0515                   bool set_chip, u16 sleep_duration)
0516 {
0517     unsigned int i;
0518     u32 staid, data;
0519 
0520     staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
0521 
0522     switch (mode) {
0523     case AR5K_PM_AUTO:
0524         staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
0525         fallthrough;
0526     case AR5K_PM_NETWORK_SLEEP:
0527         if (set_chip)
0528             ath5k_hw_reg_write(ah,
0529                 AR5K_SLEEP_CTL_SLE_ALLOW |
0530                 sleep_duration,
0531                 AR5K_SLEEP_CTL);
0532 
0533         staid |= AR5K_STA_ID1_PWR_SV;
0534         break;
0535 
0536     case AR5K_PM_FULL_SLEEP:
0537         if (set_chip)
0538             ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
0539                 AR5K_SLEEP_CTL);
0540 
0541         staid |= AR5K_STA_ID1_PWR_SV;
0542         break;
0543 
0544     case AR5K_PM_AWAKE:
0545 
0546         staid &= ~AR5K_STA_ID1_PWR_SV;
0547 
0548         if (!set_chip)
0549             goto commit;
0550 
0551         data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);
0552 
0553         /* If card is down we 'll get 0xffff... so we
0554          * need to clean this up before we write the register
0555          */
0556         if (data & 0xffc00000)
0557             data = 0;
0558         else
0559             /* Preserve sleep duration etc */
0560             data = data & ~AR5K_SLEEP_CTL_SLE;
0561 
0562         ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
0563                             AR5K_SLEEP_CTL);
0564         usleep_range(15, 20);
0565 
0566         for (i = 200; i > 0; i--) {
0567             /* Check if the chip did wake up */
0568             if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
0569                     AR5K_PCICFG_SPWR_DN) == 0)
0570                 break;
0571 
0572             /* Wait a bit and retry */
0573             usleep_range(50, 75);
0574             ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
0575                             AR5K_SLEEP_CTL);
0576         }
0577 
0578         /* Fail if the chip didn't wake up */
0579         if (i == 0)
0580             return -EIO;
0581 
0582         break;
0583 
0584     default:
0585         return -EINVAL;
0586     }
0587 
0588 commit:
0589     ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
0590 
0591     return 0;
0592 }
0593 
0594 /**
0595  * ath5k_hw_on_hold() - Put device on hold
0596  * @ah: The &struct ath5k_hw
0597  *
0598  * Put MAC and Baseband on warm reset and keep that state
0599  * (don't clean sleep control register). After this MAC
0600  * and Baseband are disabled and a full reset is needed
0601  * to come back. This way we save as much power as possible
0602  * without putting the card on full sleep.
0603  *
0604  * Returns 0 on success or -EIO on error
0605  */
0606 int
0607 ath5k_hw_on_hold(struct ath5k_hw *ah)
0608 {
0609     struct pci_dev *pdev = ah->pdev;
0610     u32 bus_flags;
0611     int ret;
0612 
0613     if (ath5k_get_bus_type(ah) == ATH_AHB)
0614         return 0;
0615 
0616     /* Make sure device is awake */
0617     ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);
0618     if (ret) {
0619         ATH5K_ERR(ah, "failed to wakeup the MAC Chip\n");
0620         return ret;
0621     }
0622 
0623     /*
0624      * Put chipset on warm reset...
0625      *
0626      * Note: putting PCI core on warm reset on PCI-E cards
0627      * results card to hang and always return 0xffff... so
0628      * we ignore that flag for PCI-E cards. On PCI cards
0629      * this flag gets cleared after 64 PCI clocks.
0630      */
0631     bus_flags = (pdev && pci_is_pcie(pdev)) ? 0 : AR5K_RESET_CTL_PCI;
0632 
0633     if (ah->ah_version == AR5K_AR5210) {
0634         ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
0635             AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
0636             AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
0637         usleep_range(2000, 2500);
0638     } else {
0639         ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
0640             AR5K_RESET_CTL_BASEBAND | bus_flags);
0641     }
0642 
0643     if (ret) {
0644         ATH5K_ERR(ah, "failed to put device on warm reset\n");
0645         return -EIO;
0646     }
0647 
0648     /* ...wakeup again!*/
0649     ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);
0650     if (ret) {
0651         ATH5K_ERR(ah, "failed to put device on hold\n");
0652         return ret;
0653     }
0654 
0655     return ret;
0656 }
0657 
0658 /**
0659  * ath5k_hw_nic_wakeup() - Force card out of sleep
0660  * @ah: The &struct ath5k_hw
0661  * @channel: The &struct ieee80211_channel
0662  *
0663  * Bring up MAC + PHY Chips and program PLL
0664  * NOTE: Channel is NULL for the initial wakeup.
0665  *
0666  * Returns 0 on success, -EIO on hw failure or -EINVAL for false channel infos
0667  */
0668 int
0669 ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel)
0670 {
0671     struct pci_dev *pdev = ah->pdev;
0672     u32 turbo, mode, clock, bus_flags;
0673     int ret;
0674 
0675     turbo = 0;
0676     mode = 0;
0677     clock = 0;
0678 
0679     if ((ath5k_get_bus_type(ah) != ATH_AHB) || channel) {
0680         /* Wakeup the device */
0681         ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);
0682         if (ret) {
0683             ATH5K_ERR(ah, "failed to wakeup the MAC Chip\n");
0684             return ret;
0685         }
0686     }
0687 
0688     /*
0689      * Put chipset on warm reset...
0690      *
0691      * Note: putting PCI core on warm reset on PCI-E cards
0692      * results card to hang and always return 0xffff... so
0693      * we ignore that flag for PCI-E cards. On PCI cards
0694      * this flag gets cleared after 64 PCI clocks.
0695      */
0696     bus_flags = (pdev && pci_is_pcie(pdev)) ? 0 : AR5K_RESET_CTL_PCI;
0697 
0698     if (ah->ah_version == AR5K_AR5210) {
0699         ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
0700             AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
0701             AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
0702         usleep_range(2000, 2500);
0703     } else {
0704         if (ath5k_get_bus_type(ah) == ATH_AHB)
0705             ret = ath5k_hw_wisoc_reset(ah, AR5K_RESET_CTL_PCU |
0706                 AR5K_RESET_CTL_BASEBAND);
0707         else
0708             ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
0709                 AR5K_RESET_CTL_BASEBAND | bus_flags);
0710     }
0711 
0712     if (ret) {
0713         ATH5K_ERR(ah, "failed to reset the MAC Chip\n");
0714         return -EIO;
0715     }
0716 
0717     /* ...wakeup again!...*/
0718     ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);
0719     if (ret) {
0720         ATH5K_ERR(ah, "failed to resume the MAC Chip\n");
0721         return ret;
0722     }
0723 
0724     /* ...reset configuration register on Wisoc ...
0725      * ...clear reset control register and pull device out of
0726      * warm reset on others */
0727     if (ath5k_get_bus_type(ah) == ATH_AHB)
0728         ret = ath5k_hw_wisoc_reset(ah, 0);
0729     else
0730         ret = ath5k_hw_nic_reset(ah, 0);
0731 
0732     if (ret) {
0733         ATH5K_ERR(ah, "failed to warm reset the MAC Chip\n");
0734         return -EIO;
0735     }
0736 
0737     /* On initialization skip PLL programming since we don't have
0738      * a channel / mode set yet */
0739     if (!channel)
0740         return 0;
0741 
0742     if (ah->ah_version != AR5K_AR5210) {
0743         /*
0744          * Get channel mode flags
0745          */
0746 
0747         if (ah->ah_radio >= AR5K_RF5112) {
0748             mode = AR5K_PHY_MODE_RAD_RF5112;
0749             clock = AR5K_PHY_PLL_RF5112;
0750         } else {
0751             mode = AR5K_PHY_MODE_RAD_RF5111;    /*Zero*/
0752             clock = AR5K_PHY_PLL_RF5111;        /*Zero*/
0753         }
0754 
0755         if (channel->band == NL80211_BAND_2GHZ) {
0756             mode |= AR5K_PHY_MODE_FREQ_2GHZ;
0757             clock |= AR5K_PHY_PLL_44MHZ;
0758 
0759             if (channel->hw_value == AR5K_MODE_11B) {
0760                 mode |= AR5K_PHY_MODE_MOD_CCK;
0761             } else {
0762                 /* XXX Dynamic OFDM/CCK is not supported by the
0763                  * AR5211 so we set MOD_OFDM for plain g (no
0764                  * CCK headers) operation. We need to test
0765                  * this, 5211 might support ofdm-only g after
0766                  * all, there are also initial register values
0767                  * in the code for g mode (see initvals.c).
0768                  */
0769                 if (ah->ah_version == AR5K_AR5211)
0770                     mode |= AR5K_PHY_MODE_MOD_OFDM;
0771                 else
0772                     mode |= AR5K_PHY_MODE_MOD_DYN;
0773             }
0774         } else if (channel->band == NL80211_BAND_5GHZ) {
0775             mode |= (AR5K_PHY_MODE_FREQ_5GHZ |
0776                  AR5K_PHY_MODE_MOD_OFDM);
0777 
0778             /* Different PLL setting for 5413 */
0779             if (ah->ah_radio == AR5K_RF5413)
0780                 clock = AR5K_PHY_PLL_40MHZ_5413;
0781             else
0782                 clock |= AR5K_PHY_PLL_40MHZ;
0783         } else {
0784             ATH5K_ERR(ah, "invalid radio frequency mode\n");
0785             return -EINVAL;
0786         }
0787 
0788         /*XXX: Can bwmode be used with dynamic mode ?
0789          * (I don't think it supports 44MHz) */
0790         /* On 2425 initvals TURBO_SHORT is not present */
0791         if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
0792             turbo = AR5K_PHY_TURBO_MODE;
0793             if (ah->ah_radio != AR5K_RF2425)
0794                 turbo |= AR5K_PHY_TURBO_SHORT;
0795         } else if (ah->ah_bwmode != AR5K_BWMODE_DEFAULT) {
0796             if (ah->ah_radio == AR5K_RF5413) {
0797                 mode |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
0798                     AR5K_PHY_MODE_HALF_RATE :
0799                     AR5K_PHY_MODE_QUARTER_RATE;
0800             } else if (ah->ah_version == AR5K_AR5212) {
0801                 clock |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
0802                     AR5K_PHY_PLL_HALF_RATE :
0803                     AR5K_PHY_PLL_QUARTER_RATE;
0804             }
0805         }
0806 
0807     } else { /* Reset the device */
0808 
0809         /* ...enable Atheros turbo mode if requested */
0810         if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
0811             ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
0812                     AR5K_PHY_TURBO);
0813     }
0814 
0815     if (ah->ah_version != AR5K_AR5210) {
0816 
0817         /* ...update PLL if needed */
0818         if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
0819             ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
0820             usleep_range(300, 350);
0821         }
0822 
0823         /* ...set the PHY operating mode */
0824         ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
0825         ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
0826     }
0827 
0828     return 0;
0829 }
0830 
0831 
0832 /**************************************\
0833 * Post-initvals register modifications *
0834 \**************************************/
0835 
0836 /**
0837  * ath5k_hw_tweak_initval_settings() - Tweak initial settings
0838  * @ah: The &struct ath5k_hw
0839  * @channel: The &struct ieee80211_channel
0840  *
0841  * Some settings are not handled on initvals, e.g. bwmode
0842  * settings, some phy settings, workarounds etc that in general
0843  * don't fit anywhere else or are too small to introduce a separate
0844  * function for each one. So we have this function to handle
0845  * them all during reset and complete card's initialization.
0846  */
0847 static void
0848 ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
0849                 struct ieee80211_channel *channel)
0850 {
0851     if (ah->ah_version == AR5K_AR5212 &&
0852         ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
0853 
0854         /* Setup ADC control */
0855         ath5k_hw_reg_write(ah,
0856                 (AR5K_REG_SM(2,
0857                 AR5K_PHY_ADC_CTL_INBUFGAIN_OFF) |
0858                 AR5K_REG_SM(2,
0859                 AR5K_PHY_ADC_CTL_INBUFGAIN_ON) |
0860                 AR5K_PHY_ADC_CTL_PWD_DAC_OFF |
0861                 AR5K_PHY_ADC_CTL_PWD_ADC_OFF),
0862                 AR5K_PHY_ADC_CTL);
0863 
0864 
0865 
0866         /* Disable barker RSSI threshold */
0867         AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
0868                 AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR);
0869 
0870         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
0871             AR5K_PHY_DAG_CCK_CTL_RSSI_THR, 2);
0872 
0873         /* Set the mute mask */
0874         ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);
0875     }
0876 
0877     /* Clear PHY_BLUETOOTH to allow RX_CLEAR line debug */
0878     if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212B)
0879         ath5k_hw_reg_write(ah, 0, AR5K_PHY_BLUETOOTH);
0880 
0881     /* Enable DCU double buffering */
0882     if (ah->ah_phy_revision > AR5K_SREV_PHY_5212B)
0883         AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
0884                 AR5K_TXCFG_DCU_DBL_BUF_DIS);
0885 
0886     /* Set fast ADC */
0887     if ((ah->ah_radio == AR5K_RF5413) ||
0888         (ah->ah_radio == AR5K_RF2317) ||
0889         (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
0890         u32 fast_adc = true;
0891 
0892         if (channel->center_freq == 2462 ||
0893         channel->center_freq == 2467)
0894             fast_adc = 0;
0895 
0896         /* Only update if needed */
0897         if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc)
0898                 ath5k_hw_reg_write(ah, fast_adc,
0899                         AR5K_PHY_FAST_ADC);
0900     }
0901 
0902     /* Fix for first revision of the RF5112 RF chipset */
0903     if (ah->ah_radio == AR5K_RF5112 &&
0904             ah->ah_radio_5ghz_revision <
0905             AR5K_SREV_RAD_5112A) {
0906         u32 data;
0907         ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
0908                 AR5K_PHY_CCKTXCTL);
0909         if (channel->band == NL80211_BAND_5GHZ)
0910             data = 0xffb81020;
0911         else
0912             data = 0xffb80d20;
0913         ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
0914     }
0915 
0916     if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
0917         /* Clear QCU/DCU clock gating register */
0918         ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT);
0919         /* Set DAC/ADC delays */
0920         ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ_5311,
0921                         AR5K_PHY_SCAL);
0922         /* Enable PCU FIFO corruption ECO */
0923         AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
0924                     AR5K_DIAG_SW_ECO_ENABLE);
0925     }
0926 
0927     if (ah->ah_bwmode) {
0928         /* Increase PHY switch and AGC settling time
0929          * on turbo mode (ath5k_hw_commit_eeprom_settings
0930          * will override settling time if available) */
0931         if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
0932 
0933             AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
0934                         AR5K_PHY_SETTLING_AGC,
0935                         AR5K_AGC_SETTLING_TURBO);
0936 
0937             /* XXX: Initvals indicate we only increase
0938              * switch time on AR5212, 5211 and 5210
0939              * only change agc time (bug?) */
0940             if (ah->ah_version == AR5K_AR5212)
0941                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
0942                         AR5K_PHY_SETTLING_SWITCH,
0943                         AR5K_SWITCH_SETTLING_TURBO);
0944 
0945             if (ah->ah_version == AR5K_AR5210) {
0946                 /* Set Frame Control Register */
0947                 ath5k_hw_reg_write(ah,
0948                     (AR5K_PHY_FRAME_CTL_INI |
0949                     AR5K_PHY_TURBO_MODE |
0950                     AR5K_PHY_TURBO_SHORT | 0x2020),
0951                     AR5K_PHY_FRAME_CTL_5210);
0952             }
0953         /* On 5413 PHY force window length for half/quarter rate*/
0954         } else if ((ah->ah_mac_srev >= AR5K_SREV_AR5424) &&
0955         (ah->ah_mac_srev <= AR5K_SREV_AR5414)) {
0956             AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL_5211,
0957                         AR5K_PHY_FRAME_CTL_WIN_LEN,
0958                         3);
0959         }
0960     } else if (ah->ah_version == AR5K_AR5210) {
0961         /* Set Frame Control Register for normal operation */
0962         ath5k_hw_reg_write(ah, (AR5K_PHY_FRAME_CTL_INI | 0x1020),
0963                         AR5K_PHY_FRAME_CTL_5210);
0964     }
0965 }
0966 
0967 /**
0968  * ath5k_hw_commit_eeprom_settings() - Commit settings from EEPROM
0969  * @ah: The &struct ath5k_hw
0970  * @channel: The &struct ieee80211_channel
0971  *
0972  * Use settings stored on EEPROM to properly initialize the card
0973  * based on various infos and per-mode calibration data.
0974  */
0975 static void
0976 ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
0977         struct ieee80211_channel *channel)
0978 {
0979     struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
0980     s16 cck_ofdm_pwr_delta;
0981     u8 ee_mode;
0982 
0983     /* TODO: Add support for AR5210 EEPROM */
0984     if (ah->ah_version == AR5K_AR5210)
0985         return;
0986 
0987     ee_mode = ath5k_eeprom_mode_from_channel(ah, channel);
0988 
0989     /* Adjust power delta for channel 14 */
0990     if (channel->center_freq == 2484)
0991         cck_ofdm_pwr_delta =
0992             ((ee->ee_cck_ofdm_power_delta -
0993             ee->ee_scaled_cck_delta) * 2) / 10;
0994     else
0995         cck_ofdm_pwr_delta =
0996             (ee->ee_cck_ofdm_power_delta * 2) / 10;
0997 
0998     /* Set CCK to OFDM power delta on tx power
0999      * adjustment register */
1000     if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
1001         if (channel->hw_value == AR5K_MODE_11G)
1002             ath5k_hw_reg_write(ah,
1003             AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1),
1004                 AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA) |
1005             AR5K_REG_SM((cck_ofdm_pwr_delta * -1),
1006                 AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX),
1007                 AR5K_PHY_TX_PWR_ADJ);
1008         else
1009             ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ);
1010     } else {
1011         /* For older revs we scale power on sw during tx power
1012          * setup */
1013         ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta;
1014         ah->ah_txpower.txp_cck_ofdm_gainf_delta =
1015                         ee->ee_cck_ofdm_gain_delta;
1016     }
1017 
1018     /* XXX: necessary here? is called from ath5k_hw_set_antenna_mode()
1019      * too */
1020     ath5k_hw_set_antenna_switch(ah, ee_mode);
1021 
1022     /* Noise floor threshold */
1023     ath5k_hw_reg_write(ah,
1024         AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
1025         AR5K_PHY_NFTHRES);
1026 
1027     if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&
1028     (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) {
1029         /* Switch settling time (Turbo) */
1030         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
1031                 AR5K_PHY_SETTLING_SWITCH,
1032                 ee->ee_switch_settling_turbo[ee_mode]);
1033 
1034         /* Tx/Rx attenuation (Turbo) */
1035         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
1036                 AR5K_PHY_GAIN_TXRX_ATTEN,
1037                 ee->ee_atn_tx_rx_turbo[ee_mode]);
1038 
1039         /* ADC/PGA desired size (Turbo) */
1040         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
1041                 AR5K_PHY_DESIRED_SIZE_ADC,
1042                 ee->ee_adc_desired_size_turbo[ee_mode]);
1043 
1044         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
1045                 AR5K_PHY_DESIRED_SIZE_PGA,
1046                 ee->ee_pga_desired_size_turbo[ee_mode]);
1047 
1048         /* Tx/Rx margin (Turbo) */
1049         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
1050                 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
1051                 ee->ee_margin_tx_rx_turbo[ee_mode]);
1052 
1053     } else {
1054         /* Switch settling time */
1055         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
1056                 AR5K_PHY_SETTLING_SWITCH,
1057                 ee->ee_switch_settling[ee_mode]);
1058 
1059         /* Tx/Rx attenuation */
1060         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
1061                 AR5K_PHY_GAIN_TXRX_ATTEN,
1062                 ee->ee_atn_tx_rx[ee_mode]);
1063 
1064         /* ADC/PGA desired size */
1065         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
1066                 AR5K_PHY_DESIRED_SIZE_ADC,
1067                 ee->ee_adc_desired_size[ee_mode]);
1068 
1069         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
1070                 AR5K_PHY_DESIRED_SIZE_PGA,
1071                 ee->ee_pga_desired_size[ee_mode]);
1072 
1073         /* Tx/Rx margin */
1074         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
1075             AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
1076                 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
1077                 ee->ee_margin_tx_rx[ee_mode]);
1078     }
1079 
1080     /* XPA delays */
1081     ath5k_hw_reg_write(ah,
1082         (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
1083         (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
1084         (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
1085         (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4);
1086 
1087     /* XLNA delay */
1088     AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL3,
1089             AR5K_PHY_RF_CTL3_TXE2XLNA_ON,
1090             ee->ee_tx_end2xlna_enable[ee_mode]);
1091 
1092     /* Thresh64 (ANI) */
1093     AR5K_REG_WRITE_BITS(ah, AR5K_PHY_NF,
1094             AR5K_PHY_NF_THRESH62,
1095             ee->ee_thr_62[ee_mode]);
1096 
1097     /* False detect backoff for channels
1098      * that have spur noise. Write the new
1099      * cyclic power RSSI threshold. */
1100     if (ath5k_hw_chan_has_spur_noise(ah, channel))
1101         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
1102                 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
1103                 AR5K_INIT_CYCRSSI_THR1 +
1104                 ee->ee_false_detect[ee_mode]);
1105     else
1106         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
1107                 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
1108                 AR5K_INIT_CYCRSSI_THR1);
1109 
1110     /* I/Q correction (set enable bit last to match HAL sources) */
1111     /* TODO: Per channel i/q infos ? */
1112     if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
1113         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF,
1114                 ee->ee_i_cal[ee_mode]);
1115         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF,
1116                 ee->ee_q_cal[ee_mode]);
1117         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
1118     }
1119 
1120     /* Heavy clipping -disable for now */
1121     if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1)
1122         ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE);
1123 }
1124 
1125 
1126 /*********************\
1127 * Main reset function *
1128 \*********************/
1129 
1130 /**
1131  * ath5k_hw_reset() - The main reset function
1132  * @ah: The &struct ath5k_hw
1133  * @op_mode: One of enum nl80211_iftype
1134  * @channel: The &struct ieee80211_channel
1135  * @fast: Enable fast channel switching
1136  * @skip_pcu: Skip pcu initialization
1137  *
1138  * This is the function we call each time we want to (re)initialize the
1139  * card and pass new settings to hw. We also call it when hw runs into
1140  * trouble to make it come back to a working state.
1141  *
1142  * Returns 0 on success, -EINVAL on false op_mode or channel infos, or -EIO
1143  * on failure.
1144  */
1145 int
1146 ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1147         struct ieee80211_channel *channel, bool fast, bool skip_pcu)
1148 {
1149     u32 s_seq[10], s_led[3], tsf_up, tsf_lo;
1150     u8 mode;
1151     int i, ret;
1152 
1153     tsf_up = 0;
1154     tsf_lo = 0;
1155     mode = 0;
1156 
1157     /*
1158      * Sanity check for fast flag
1159      * Fast channel change only available
1160      * on AR2413/AR5413.
1161      */
1162     if (fast && (ah->ah_radio != AR5K_RF2413) &&
1163     (ah->ah_radio != AR5K_RF5413))
1164         fast = false;
1165 
1166     /* Disable sleep clock operation
1167      * to avoid register access delay on certain
1168      * PHY registers */
1169     if (ah->ah_version == AR5K_AR5212)
1170         ath5k_hw_set_sleep_clock(ah, false);
1171 
1172     mode = channel->hw_value;
1173     switch (mode) {
1174     case AR5K_MODE_11A:
1175         break;
1176     case AR5K_MODE_11G:
1177         if (ah->ah_version <= AR5K_AR5211) {
1178             ATH5K_ERR(ah,
1179                 "G mode not available on 5210/5211");
1180             return -EINVAL;
1181         }
1182         break;
1183     case AR5K_MODE_11B:
1184         if (ah->ah_version < AR5K_AR5211) {
1185             ATH5K_ERR(ah,
1186                 "B mode not available on 5210");
1187             return -EINVAL;
1188         }
1189         break;
1190     default:
1191         ATH5K_ERR(ah,
1192             "invalid channel: %d\n", channel->center_freq);
1193         return -EINVAL;
1194     }
1195 
1196     /*
1197      * If driver requested fast channel change and DMA has stopped
1198      * go on. If it fails continue with a normal reset.
1199      */
1200     if (fast) {
1201         ret = ath5k_hw_phy_init(ah, channel, mode, true);
1202         if (ret) {
1203             ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1204                 "fast chan change failed, falling back to normal reset\n");
1205             /* Non fatal, can happen eg.
1206              * on mode change */
1207             ret = 0;
1208         } else {
1209             ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1210                 "fast chan change successful\n");
1211             return 0;
1212         }
1213     }
1214 
1215     /*
1216      * Save some registers before a reset
1217      */
1218     if (ah->ah_version != AR5K_AR5210) {
1219         /*
1220          * Save frame sequence count
1221          * For revs. after Oahu, only save
1222          * seq num for DCU 0 (Global seq num)
1223          */
1224         if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
1225 
1226             for (i = 0; i < 10; i++)
1227                 s_seq[i] = ath5k_hw_reg_read(ah,
1228                     AR5K_QUEUE_DCU_SEQNUM(i));
1229 
1230         } else {
1231             s_seq[0] = ath5k_hw_reg_read(ah,
1232                     AR5K_QUEUE_DCU_SEQNUM(0));
1233         }
1234 
1235         /* TSF accelerates on AR5211 during reset
1236          * As a workaround save it here and restore
1237          * it later so that it's back in time after
1238          * reset. This way it'll get re-synced on the
1239          * next beacon without breaking ad-hoc.
1240          *
1241          * On AR5212 TSF is almost preserved across a
1242          * reset so it stays back in time anyway and
1243          * we don't have to save/restore it.
1244          *
1245          * XXX: Since this breaks power saving we have
1246          * to disable power saving until we receive the
1247          * next beacon, so we can resync beacon timers */
1248         if (ah->ah_version == AR5K_AR5211) {
1249             tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
1250             tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
1251         }
1252     }
1253 
1254 
1255     /*GPIOs*/
1256     s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) &
1257                     AR5K_PCICFG_LEDSTATE;
1258     s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
1259     s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
1260 
1261 
1262     /*
1263      * Since we are going to write rf buffer
1264      * check if we have any pending gain_F
1265      * optimization settings
1266      */
1267     if (ah->ah_version == AR5K_AR5212 &&
1268     (ah->ah_radio <= AR5K_RF5112)) {
1269         if (!fast && ah->ah_rf_banks != NULL)
1270                 ath5k_hw_gainf_calibrate(ah);
1271     }
1272 
1273     /* Wakeup the device */
1274     ret = ath5k_hw_nic_wakeup(ah, channel);
1275     if (ret)
1276         return ret;
1277 
1278     /* PHY access enable */
1279     if (ah->ah_mac_srev >= AR5K_SREV_AR5211)
1280         ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1281     else
1282         ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40,
1283                             AR5K_PHY(0));
1284 
1285     /* Write initial settings */
1286     ret = ath5k_hw_write_initvals(ah, mode, skip_pcu);
1287     if (ret)
1288         return ret;
1289 
1290     /* Initialize core clock settings */
1291     ath5k_hw_init_core_clock(ah);
1292 
1293     /*
1294      * Tweak initval settings for revised
1295      * chipsets and add some more config
1296      * bits
1297      */
1298     ath5k_hw_tweak_initval_settings(ah, channel);
1299 
1300     /* Commit values from EEPROM */
1301     ath5k_hw_commit_eeprom_settings(ah, channel);
1302 
1303 
1304     /*
1305      * Restore saved values
1306      */
1307 
1308     /* Seqnum, TSF */
1309     if (ah->ah_version != AR5K_AR5210) {
1310         if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
1311             for (i = 0; i < 10; i++)
1312                 ath5k_hw_reg_write(ah, s_seq[i],
1313                     AR5K_QUEUE_DCU_SEQNUM(i));
1314         } else {
1315             ath5k_hw_reg_write(ah, s_seq[0],
1316                 AR5K_QUEUE_DCU_SEQNUM(0));
1317         }
1318 
1319         if (ah->ah_version == AR5K_AR5211) {
1320             ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32);
1321             ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32);
1322         }
1323     }
1324 
1325     /* Ledstate */
1326     AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
1327 
1328     /* Gpio settings */
1329     ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
1330     ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
1331 
1332     /*
1333      * Initialize PCU
1334      */
1335     ath5k_hw_pcu_init(ah, op_mode);
1336 
1337     /*
1338      * Initialize PHY
1339      */
1340     ret = ath5k_hw_phy_init(ah, channel, mode, false);
1341     if (ret) {
1342         ATH5K_ERR(ah,
1343             "failed to initialize PHY (%i) !\n", ret);
1344         return ret;
1345     }
1346 
1347     /*
1348      * Configure QCUs/DCUs
1349      */
1350     ret = ath5k_hw_init_queues(ah);
1351     if (ret)
1352         return ret;
1353 
1354 
1355     /*
1356      * Initialize DMA/Interrupts
1357      */
1358     ath5k_hw_dma_init(ah);
1359 
1360 
1361     /*
1362      * Enable 32KHz clock function for AR5212+ chips
1363      * Set clocks to 32KHz operation and use an
1364      * external 32KHz crystal when sleeping if one
1365      * exists.
1366      * Disabled by default because it is also disabled in
1367      * other drivers and it is known to cause stability
1368      * issues on some devices
1369      */
1370     if (ah->ah_use_32khz_clock && ah->ah_version == AR5K_AR5212 &&
1371         op_mode != NL80211_IFTYPE_AP)
1372         ath5k_hw_set_sleep_clock(ah, true);
1373 
1374     /*
1375      * Disable beacons and reset the TSF
1376      */
1377     AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE);
1378     ath5k_hw_reset_tsf(ah);
1379     return 0;
1380 }
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