ath/ath5k/pci.c

0001 /*
0002  * Copyright (c) 2008-2009 Atheros Communications Inc.
0003  *
0004  * Permission to use, copy, modify, and/or distribute this software for any
0005  * purpose with or without fee is hereby granted, provided that the above
0006  * copyright notice and this permission notice appear in all copies.
0007  *
0008  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0009  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0010  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0011  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0012  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0013  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0014  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0015  */
0016
0017 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0018
0019 #include <linux/nl80211.h>
0020 #include <linux/pci.h>
0021 #include <linux/etherdevice.h>
0022 #include <linux/module.h>
0023 #include "../ath.h"
0024 #include "ath5k.h"
0025 #include "debug.h"
0026 #include "base.h"
0027 #include "reg.h"
0028
0029 /* Known PCI ids */
0030 static const struct pci_device_id ath5k_pci_id_table[] = {
0031     { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
0032     { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
0033     { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
0034     { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
0035     { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
0036     { PCI_VDEVICE(3COM_2,  0x0013) }, /* 3com 5212 */
0037     { PCI_VDEVICE(3COM,    0x0013) }, /* 3com 3CRDAG675 5212 */
0038     { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
0039     { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 compatible */
0040     { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 compatible */
0041     { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 compatible */
0042     { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 compatible */
0043     { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 compatible */
0044     { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 compatible */
0045     { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
0046     { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
0047     { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
0048     { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
0049     { PCI_VDEVICE(ATHEROS, 0xff1b) }, /* AR5BXB63 */
0050     { 0 }
0051 };
0052 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
0053
0054 /* return bus cachesize in 4B word units */
0055 static void ath5k_pci_read_cachesize(struct ath_common *common, int *csz)
0056 {
0057     struct ath5k_hw *ah = (struct ath5k_hw *) common->priv;
0058     u8 u8tmp;
0059
0060     pci_read_config_byte(ah->pdev, PCI_CACHE_LINE_SIZE, &u8tmp);
0061     *csz = (int)u8tmp;
0062
0063     /*
0064      * This check was put in to avoid "unpleasant" consequences if
0065      * the bootrom has not fully initialized all PCI devices.
0066      * Sometimes the cache line size register is not set
0067      */
0068
0069     if (*csz == 0)
0070         *csz = L1_CACHE_BYTES >> 2;   /* Use the default size */
0071 }
0072
0073 /*
0074  * Read from eeprom
0075  */
0076 static bool
0077 ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data)
0078 {
0079     struct ath5k_hw *ah = (struct ath5k_hw *) common->ah;
0080     u32 status, timeout;
0081
0082     /*
0083      * Initialize EEPROM access
0084      */
0085     if (ah->ah_version == AR5K_AR5210) {
0086         AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
0087         (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
0088     } else {
0089         ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
0090         AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
0091                 AR5K_EEPROM_CMD_READ);
0092     }
0093
0094     for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
0095         status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
0096         if (status & AR5K_EEPROM_STAT_RDDONE) {
0097             if (status & AR5K_EEPROM_STAT_RDERR)
0098                 return false;
0099             *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
0100                     0xffff);
0101             return true;
0102         }
0103         usleep_range(15, 20);
0104     }
0105
0106     return false;
0107 }
0108
0109 int ath5k_hw_read_srev(struct ath5k_hw *ah)
0110 {
0111     ah->ah_mac_srev = ath5k_hw_reg_read(ah, AR5K_SREV);
0112     return 0;
0113 }
0114
0115 /*
0116  * Read the MAC address from eeprom or platform_data
0117  */
0118 static int ath5k_pci_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
0119 {
0120     u8 mac_d[ETH_ALEN] = {};
0121     u32 total, offset;
0122     u16 data;
0123     int octet;
0124
0125     AR5K_EEPROM_READ(0x20, data);
0126
0127     for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
0128         AR5K_EEPROM_READ(offset, data);
0129
0130         total += data;
0131         mac_d[octet + 1] = data & 0xff;
0132         mac_d[octet] = data >> 8;
0133         octet += 2;
0134     }
0135
0136     if (!total || total == 3 * 0xffff)
0137         return -EINVAL;
0138
0139     memcpy(mac, mac_d, ETH_ALEN);
0140
0141     return 0;
0142 }
0143
0144
0145 /* Common ath_bus_opts structure */
0146 static const struct ath_bus_ops ath_pci_bus_ops = {
0147     .ath_bus_type = ATH_PCI,
0148     .read_cachesize = ath5k_pci_read_cachesize,
0149     .eeprom_read = ath5k_pci_eeprom_read,
0150     .eeprom_read_mac = ath5k_pci_eeprom_read_mac,
0151 };
0152
0153 /********************\
0154 * PCI Initialization *
0155 \********************/
0156
0157 static int
0158 ath5k_pci_probe(struct pci_dev *pdev,
0159         const struct pci_device_id *id)
0160 {
0161     void __iomem *mem;
0162     struct ath5k_hw *ah;
0163     struct ieee80211_hw *hw;
0164     int ret;
0165     u8 csz;
0166
0167     /*
0168      * L0s needs to be disabled on all ath5k cards.
0169      *
0170      * For distributions shipping with CONFIG_PCIEASPM (this will be enabled
0171      * by default in the future in 2.6.36) this will also mean both L1 and
0172      * L0s will be disabled when a pre 1.1 PCIe device is detected. We do
0173      * know L1 works correctly even for all ath5k pre 1.1 PCIe devices
0174      * though but cannot currently undue the effect of a blacklist, for
0175      * details you can read pcie_aspm_sanity_check() and see how it adjusts
0176      * the device link capability.
0177      *
0178      * It may be possible in the future to implement some PCI API to allow
0179      * drivers to override blacklists for pre 1.1 PCIe but for now it is
0180      * best to accept that both L0s and L1 will be disabled completely for
0181      * distributions shipping with CONFIG_PCIEASPM rather than having this
0182      * issue present. Motivation for adding this new API will be to help
0183      * with power consumption for some of these devices.
0184      */
0185     pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);
0186
0187     ret = pci_enable_device(pdev);
0188     if (ret) {
0189         dev_err(&pdev->dev, "can't enable device\n");
0190         goto err;
0191     }
0192
0193     /* XXX 32-bit addressing only */
0194     ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
0195     if (ret) {
0196         dev_err(&pdev->dev, "32-bit DMA not available\n");
0197         goto err_dis;
0198     }
0199
0200     /*
0201      * Cache line size is used to size and align various
0202      * structures used to communicate with the hardware.
0203      */
0204     pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
0205     if (csz == 0) {
0206         /*
0207          * Linux 2.4.18 (at least) writes the cache line size
0208          * register as a 16-bit wide register which is wrong.
0209          * We must have this setup properly for rx buffer
0210          * DMA to work so force a reasonable value here if it
0211          * comes up zero.
0212          */
0213         csz = L1_CACHE_BYTES >> 2;
0214         pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
0215     }
0216     /*
0217      * The default setting of latency timer yields poor results,
0218      * set it to the value used by other systems.  It may be worth
0219      * tweaking this setting more.
0220      */
0221     pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
0222
0223     /* Enable bus mastering */
0224     pci_set_master(pdev);
0225
0226     /*
0227      * Disable the RETRY_TIMEOUT register (0x41) to keep
0228      * PCI Tx retries from interfering with C3 CPU state.
0229      */
0230     pci_write_config_byte(pdev, 0x41, 0);
0231
0232     ret = pci_request_region(pdev, 0, "ath5k");
0233     if (ret) {
0234         dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
0235         goto err_dis;
0236     }
0237
0238     mem = pci_iomap(pdev, 0, 0);
0239     if (!mem) {
0240         dev_err(&pdev->dev, "cannot remap PCI memory region\n");
0241         ret = -EIO;
0242         goto err_reg;
0243     }
0244
0245     /*
0246      * Allocate hw (mac80211 main struct)
0247      * and hw->priv (driver private data)
0248      */
0249     hw = ieee80211_alloc_hw(sizeof(*ah), &ath5k_hw_ops);
0250     if (hw == NULL) {
0251         dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
0252         ret = -ENOMEM;
0253         goto err_map;
0254     }
0255
0256     dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
0257
0258     ah = hw->priv;
0259     ah->hw = hw;
0260     ah->pdev = pdev;
0261     ah->dev = &pdev->dev;
0262     ah->irq = pdev->irq;
0263     ah->devid = id->device;
0264     ah->iobase = mem; /* So we can unmap it on detach */
0265
0266     /* Initialize */
0267     ret = ath5k_init_ah(ah, &ath_pci_bus_ops);
0268     if (ret)
0269         goto err_free;
0270
0271     /* Set private data */
0272     pci_set_drvdata(pdev, hw);
0273
0274     return 0;
0275 err_free:
0276     ieee80211_free_hw(hw);
0277 err_map:
0278     pci_iounmap(pdev, mem);
0279 err_reg:
0280     pci_release_region(pdev, 0);
0281 err_dis:
0282     pci_disable_device(pdev);
0283 err:
0284     return ret;
0285 }
0286
0287 static void
0288 ath5k_pci_remove(struct pci_dev *pdev)
0289 {
0290     struct ieee80211_hw *hw = pci_get_drvdata(pdev);
0291     struct ath5k_hw *ah = hw->priv;
0292
0293     ath5k_deinit_ah(ah);
0294     pci_iounmap(pdev, ah->iobase);
0295     pci_release_region(pdev, 0);
0296     pci_disable_device(pdev);
0297     ieee80211_free_hw(hw);
0298 }
0299
0300 #ifdef CONFIG_PM_SLEEP
0301 static int ath5k_pci_suspend(struct device *dev)
0302 {
0303     struct ieee80211_hw *hw = dev_get_drvdata(dev);
0304     struct ath5k_hw *ah = hw->priv;
0305
0306     ath5k_led_off(ah);
0307     return 0;
0308 }
0309
0310 static int ath5k_pci_resume(struct device *dev)
0311 {
0312     struct pci_dev *pdev = to_pci_dev(dev);
0313     struct ieee80211_hw *hw = pci_get_drvdata(pdev);
0314     struct ath5k_hw *ah = hw->priv;
0315
0316     /*
0317      * Suspend/Resume resets the PCI configuration space, so we have to
0318      * re-disable the RETRY_TIMEOUT register (0x41) to keep
0319      * PCI Tx retries from interfering with C3 CPU state
0320      */
0321     pci_write_config_byte(pdev, 0x41, 0);
0322
0323     ath5k_led_enable(ah);
0324     return 0;
0325 }
0326
0327 static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
0328 #define ATH5K_PM_OPS    (&ath5k_pm_ops)
0329 #else
0330 #define ATH5K_PM_OPS    NULL
0331 #endif /* CONFIG_PM_SLEEP */
0332
0333 static struct pci_driver ath5k_pci_driver = {
0334     .name       = KBUILD_MODNAME,
0335     .id_table   = ath5k_pci_id_table,
0336     .probe      = ath5k_pci_probe,
0337     .remove     = ath5k_pci_remove,
0338     .driver.pm  = ATH5K_PM_OPS,
0339 };
0340
0341 module_pci_driver(ath5k_pci_driver);